MCU downtime protection circuit

Abstract

The utility model discloses an MCU downtime protection circuit, which comprises an MCU, a watchdog circuit, an LTO circuit and a protection circuit, and is characterized in that the MCU is connected with a main loop to supply power to work. The watchdog circuit is electrically connected with the MCU and the LTO circuit and used for receiving a dog feeding signal provided by the MCU and outputting a low-level RST signal to reset the MCU when the dog feeding signal is not received, and meanwhile the low-level RST signal is transmitted to the LTO circuit. When reset of the MCU is unsuccessful and normal dog feeding cannot be carried out all the time, the LTO circuit is electrically connected with the protection circuit in a delayed mode, and the LTO circuit is used for enabling the main loop to be powered off after the protection circuit receives the signal level. According to the MCU downtime protection circuit provided by the invention, the MCU is monitored by arranging the external independent watchdog, and when the MCU is detected not to send waves, the main loop is powered off, so that the effect of protecting the safety of the whole battery pack system is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of BMS battery management systems, and particularly relates to an MCU downtime system out-of-control protection circuit. Background Art

[0002] In a BMS battery management system, it is usually a complex system with an MCU as the core. The MCU is a microcontroller unit (MCU). Due to reasons such as power supply system fluctuations and faults (such as external static electricity, electromagnetic effects, or other reasons), the program execution of the MCU may go awry abnormally, causing the program execution to fall into an infinite loop, and ultimately leading to system crashes and unpredictable consequences. In the prior art, to meet functional safety requirements, generally a second MCU is used to monitor whether the first MCU is working abnormally. Once there is an abnormality, the second MCU will reset the first MCU. However, such a dual-core MCU system requires high costs and the application circuit is also very complex. Content of the Utility Model

[0003] To overcome the above drawbacks, the purpose of the present utility model is to provide an MCU downtime protection circuit to solve the problems raised in the above background art.

[0004] To achieve the above purpose, the technical solution adopted by the present utility model is an MCU downtime protection circuit, including an MCU, a watchdog circuit, an LTO circuit, and a protection circuit, wherein: the MCU is connected to the main circuit for power supply and operation. The watchdog circuit is electrically connected to the MCU and the LTO circuit respectively, and is used to receive the dog feeding signal provided by the MCU, and when the dog feeding signal is not received, delay the output of the RST signal level to the LTO circuit. The LTO circuit is electrically connected to the protection circuit, and is used to cut off the power supply of the main circuit after the protection circuit receives the signal level.

[0005] Preferably, the watchdog circuit includes a watchdog chip U9, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, and a third capacitor; the watchdog chip U9 includes nine ports. The first port is respectively connected to the operating voltage terminal and one end of the second capacitor, and the other end of the second capacitor is grounded to GND; the second port is connected in series with the first capacitor and grounded to GND; the third port is suspended; the fourth port is grounded to GND; the fifth port is respectively connected to one end of the second resistor and one end of the third resistor. The other end of the second resistor is connected to the operating voltage terminal, and the other end of the second resistor is grounded to GND. Both ends of the third capacitor are respectively connected to the fifth port and the other end of the second resistor; the sixth port is a signal input port and is connected to the MCU; the seventh port is a signal output port; the eighth port is connected in series with the first resistor and connected to the operating voltage terminal; the ninth port is grounded to GND.

[0006] Preferably, the LTO circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor, a first diode, and a first triode; the base of the first triode is connected in series with the fifth resistor and accesses the seventh port, the emitter is connected to the operating voltage terminal, and the collector is sequentially connected in series with the eighth resistor and the first diode and accesses the LTO. Both ends of the fourth resistor are respectively connected to the emitter and the base; one end of the fourth capacitor accesses the node between the eighth resistor and the first diode, and the other end is grounded to GND; both the fifth capacitor and the seventh resistor are connected in parallel across both ends of the fourth capacitor.

[0007] Preferably, the protection circuit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a sixth capacitor, a first field-effect transistor, and a second diode; the gate of the first field-effect transistor is connected in series with the eleventh resistor and accesses the negative terminal of the second diode, the source is grounded to GND, and the drain is sequentially connected in series with the ninth resistor and the tenth resistor and accesses the 12V power supply voltage; the positive terminal of the second diode is connected to the LTO; both the sixth capacitor and the twelfth resistor are connected in parallel across the gate and the source of the first field-effect transistor.

[0008] Preferably, the protection circuit further includes a thirteenth resistor, a first zener diode, and a second field-effect transistor; the gate of the second field-effect transistor is connected to the node between the ninth resistor and the tenth resistor, the source is connected to the 12V power supply voltage, and the drain is connected to one end of the thirteenth resistor; the first zener diode is connected in parallel across the gate and the source of the second field-effect transistor.

[0009] Preferably, the protection circuit further includes a fourteenth resistor, a seventh capacitor, a second zener diode, a third diode, a third field-effect transistor, a first connector, and a fuse group; the gate of the third field-effect transistor is connected to the other end of the thirteenth resistor, the source is grounded to GND, and the drain is connected to the negative terminal of the third diode; the positive terminal of the third diode is connected to the fuse group through the first connector; the fourteenth resistor, the seventh capacitor, and the second zener diode are all connected in parallel between the gate and the source of the third field-effect transistor.

[0010] Preferably, the fuse group is connected in series to the main circuit and includes a first fuse, a second fuse, and a third fuse connected in parallel.

[0011] Preferably, the first triode is a PNP type triode.

[0012] Preferably, the second field-effect transistor is a P-type MOS transistor, and the first field-effect transistor and the third field-effect transistor are both N-type MOS transistors.

[0013] Compared with the prior art, the advantages of the MCU crash protection circuit provided by the present invention are as follows: by setting an external independent watchdog to monitor the MCU, when it is detected that the MCU does not send waves, after a delay for a period of time, the MCU is given sufficient opportunity to revive. If it still cannot work properly, the main circuit fuse is resolutely blown to cut off the power, which plays a role in protecting the safety of the entire battery pack system. And the components used in the solution are of low cost and the circuit structure is simple and clear compared with the dual-core MCU system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is the circuit diagram of the watchdog circuit of an embodiment of an MCU crash protection circuit of the present invention;

[0015] Figure 2 is the circuit diagram of the LTO circuit of an embodiment of an MCU crash protection circuit of the present invention;

[0016] Figure 3 is the circuit diagram of the protection circuit of an embodiment of an MCU crash protection circuit of the present invention;

[0017] Figure 4 is the circuit diagram of the single-chip microcomputer programming of an embodiment of an MCU crash protection circuit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following describes in detail the preferred embodiments of the present invention with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a more clear and definite definition of the protection scope of the present invention.

[0019] ReferenceFigures 1 to 4 , Figure 1 shows the circuit diagram of the watchdog circuit of an MCU crash protection circuit provided by an embodiment of the present invention; Figure 2 shows the circuit diagram of the LTO circuit of an MCU crash protection circuit provided by an embodiment of the present invention; Figure 3 shows the circuit diagram of an MCU crash protection circuit provided by an embodiment of the present invention; Figure 4 shows the circuit diagram of the single-chip microcomputer programming of an MCU crash protection circuit provided by an embodiment of the present invention.

[0020] As Figures 1 to 4 shown, the technical solution provided by the present application is an MCU crash protection circuit, including an MCU, a watchdog circuit, an LTO circuit, and a protection circuit, where: the MCU is connected to the main circuit for power supply and operation. The watchdog circuit is electrically connected to the MCU and the LTO circuit respectively, and is used to receive the dog feeding signal provided by the MCU, and output a signal level to the LTO circuit when the dog feeding signal is not received. The LTO circuit is electrically connected to the protection circuit, and is used to cut off the power supply of the main circuit after the protection circuit receives the signal level.

[0021] The MCU crash protection circuit provided by the present application monitors the MCU by setting an external independent watchdog. When it is detected that the MCU does not send waves, after a delay period, the MCU is given sufficient opportunity to revive. If it still cannot work properly, the fuse of the main circuit is resolutely blown to cut off the power supply, which plays the role of protecting the safety of the entire battery pack system.

[0022] Furthermore, during the program debugging process of the MCU of the BMS, when an unknown error occurs in the program or the BMS runs in a complex environment (such as being affected by strong magnetic interference, static electricity, etc.) resulting in program crashes, if the BMS cannot be shut down in time, when the BMS is in the discharging state, it may burn out the load or over-discharge the lithium battery, posing a risk of fire. Therefore, the circuit provided by the embodiment of the present invention solves the problem that when the MCU runs away due to interference from the peripheral environment, the system can be automatically shut down.

[0023] In some embodiments, refer to Figures 1 to 3, the watchdog circuit includes a watchdog chip U9, a first resistor R231, a second resistor R45, a third resistor R58, a first capacitor C101, a second capacitor C102, and a third capacitor C124. The watchdog chip U9 includes 9 ports. The 1st port is respectively connected to the working voltage terminal and one end of the second capacitor C102, and the other end of the second capacitor C102 is grounded to GND. The 2nd port is connected in series with the first capacitor C101 and grounded to GND. The 3rd port is suspended. The 4th port is grounded to GND. The 5th port is respectively connected to one end of the second resistor R45 and one end of the third resistor R58. The other end of the second resistor R45 is connected to the working voltage terminal, the other end of the second resistor R58 is grounded to GND, and both ends of the third capacitor C124 are respectively connected to the 5th port and the other end of the second resistor R58. The 6th port is a signal input port and is connected to the MCU. The 7th port is a signal output port. The 8th port is connected in series with the first resistor R231 and connected to the working voltage terminal. The 9th port is grounded to GND.

[0024] Exemplarily, in this embodiment, the selected model of the watchdog chip U9 is SGM820B of Siling Micro. SGM820B is a high-precision monitoring circuit with a programmable watchdog timer. Due to its precise hysteresis characteristics, SGM820 is very suitable for use with strict tolerance systems. And SGM820 has a programmable watchdog timer, and users can program the timeout through an external capacitor or the default factory settings.

[0025] Further, the 1st port of the watchdog chip U9 corresponds to the Vcc pin and is used to connect the working voltage of 3.3V. The 2nd port corresponds to the CWD pin and is used for programmable timeout input to program the timeout time of the watchdog. If the dog is not fed within this time, it will cause the watchdog to detect an error state, and then trigger the setting operation of WDO. The 3rd port corresponds to the nMR pin and is used for manual reset. The 4th port and the 9th port both correspond to the GND pin. The 5th port corresponds to the SET pin and is used to receive the write enable signal for logic input, select the scaling ratio of the watchdog timer, and enable or disable the watchdog. The 6th port corresponds to the WDI pin and is used for watchdog input. The 7th port corresponds to the nWDO pin and is used for watchdog output. The 8th port corresponds to the nRESET pin, and the nRESET delay of SGM820 has a high-precision delay timing. Due to its precise hysteresis characteristics, SGM820 is very suitable for use with strict tolerance systems.

[0026] Specifically, the resistance value of the first resistor R231 is 100 KΩ, the resistance value of the second resistor R45 is 10 KΩ, and the resistance value of the third resistor R58 is 100 KΩ. The capacitance value of the first capacitor C101 is 47 nF to 100 nF, the capacitance value of the second capacitor C102 is 0.1 μF, and the capacitance value of the third capacitor C124 is 0.1 μF. This circuit monitors the logic control module of the ISO13849-certified LTO Class II architecture. At the same time, it must meet the pull-down requirement of the third resistor R58 to prevent the watchdog from being enabled during program burning, which would prevent the program from being burned. Also, when the MCU crashes, the watchdog should be able to instantaneously charge the third capacitor C124 through the second resistor R45, delay the enabling of the output low-level signal, and not be affected by the MCU's watchdog RST reset function, meeting the 5 s time redundancy for burning, but not maintaining a high level continuously, which would enable the watchdog and affect the burning. The reset RST delay time tWD_extended (ms) = 78.3 × 100 (nF) + 51 (ms) = 7.881 s, and 7.881 s > 5 s, meeting the requirement of no restart during burning. The downtime hold time (100 KΩ * 0.1 μF) = 0.01 s (10 k * 0.1 μF) = 0.001 s, and 0.01 s > 0.001 s, meeting the watchdog downtime hold requirement.

[0027] In some embodiments, referring to Figures 1 to 3 , the LTO circuit includes a fourth resistor R701, a fifth resistor R702, a sixth resistor R703, a seventh resistor R704, an eighth resistor R706, a fourth capacitor C701, a fifth capacitor C702, a first diode D702, and a first triode Q701. The base of the first triode Q701 is connected in series with the fifth resistor R702 to the 7th port, the emitter is connected to the working voltage terminal, and the collector is connected in series with the eighth resistor R706 and the first diode D702 to LTO. Both ends of the fourth resistor R701 are respectively connected to the emitter and the base. One end of the fourth capacitor C701 is connected to the node between the eighth resistor R706 and the first diode D702, and the other end is grounded to GND. The fifth capacitor C702 and the seventh resistor R704 are both connected in parallel across both ends of the fourth capacitor C701.

[0028] Exemplarily, after receiving the intermittent low-level signal from the WDT circuit, the eighth resistor R706 continuously limits the current and delays the charging of the fourth capacitor C701 and the fifth capacitor C702, and the voltage at the LTO terminal continuously accumulates and rises.

[0029] Specifically, the resistance value of the fourth resistor R701 is 100 KΩ, the resistance value of the fifth resistor R702 is 100 KΩ, the resistance value of the sixth resistor R703 is 10 KΩ, the resistance value of the seventh resistor R704 is 1 MΩ, and the resistance value of the eighth resistor R706 is 100 KΩ. The capacitance value of the fourth capacitor C701 is 10 μF, and the capacitance value of the fifth capacitor C702 is 10 μF. The model of the first diode D702 is BAT46W Schottky diode. The start-up protection delay is 100 K×(10 + 10) uF×5τ = 10 s.

[0030] In some embodiments, referring to Figures 1 to 3 , the protection circuit includes a ninth resistor R34, a tenth resistor R44, an eleventh resistor R49, a twelfth resistor R55, a sixth capacitor C31, a first field-effect transistor Q21, and a second diode D16. The gate of the first field-effect transistor Q21 is connected in series with the eleventh resistor R49 to the negative terminal of the second diode D16, the source is grounded to GND, and the drain is connected in series with the ninth resistor R34 and the tenth resistor R44 to the 12V power supply voltage. The positive terminal of the second diode D16 is connected to LTO. The sixth capacitor C31 and the twelfth resistor R55 are both connected in parallel between the gate and the source of the first field-effect transistor Q21.

[0031] Specifically, the resistance value of the ninth resistor R34 is 510 KΩ, the resistance value of the tenth resistor R44 is 1 MΩ, the resistance value of the eleventh resistor R49 is 100 KΩ, and the resistance value of the twelfth resistor R55 is 1 MΩ. The capacitance value of the sixth capacitor C31 is 10 μF, and the model of the second diode D16 is BAT46W Schottky diode.

[0032] The protection circuit further includes a thirteenth resistor R56, a first zener diode ZD1, and a second field-effect transistor Q16. The gate of the second field-effect transistor Q16 is connected to the node between the ninth resistor R34 and the tenth resistor R44, the source is connected to the 12V power supply voltage, and the drain is connected to one end of the thirteenth resistor R56. The first zener diode ZD1 is connected in parallel between the gate and the source of the second field-effect transistor Q16.

[0033] Specifically, the resistance value of the thirteenth resistor R56 is 100 K, and the voltage value of the first zener diode ZD1 is 12V.

[0034] The protection circuit further includes a fourteenth resistor R46, a seventh capacitor C33, a second zener diode ZD2, a third diode D701, a third field-effect transistor Q22, a first connector J701, and a fuse set. The gate of the third field-effect transistor Q22 is connected to the other end of the thirteenth resistor R56, the source is grounded to GND, and the drain is connected to the negative terminal of the third diode D701. The positive terminal of the third diode D701 is connected to the fuse set through the first connector J701. The fourteenth resistor R46, the seventh capacitor C33, and the second zener diode ZD2 are all connected in parallel between the gate and the source of the third field-effect transistor Q22.

[0035] Specifically, the resistance value of the fourteenth resistor R46 is 200 KΩ, the capacitance value of the seventh capacitor C33 is 0.1 μF, and the voltage value of the second zener diode ZD2 is 10 V.

[0036] The fuse set is connected in series in the main circuit and includes a first fuse F1, a second fuse F2, and a third fuse F3 that are arranged in parallel.

[0037] Exemplarily, when after a delay period, the MCU reset is still not normal, and at the same time the LTO voltage reaches the threshold voltage of 2 V of the first field-effect transistor Q21, the function of fusing the three-terminal fuse is started, and the third field-effect transistor Q22 is voltage-divided by about 8 V, playing a role in protecting the safety of the system.

[0038] In some embodiments, the first triode is a PNP type triode. The second field-effect transistor is a P-type MOS transistor, and the first and third field-effect transistors are both N-type MOS transistors.

[0039] The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it. It cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. An MCU crash protection circuit, characterized in that, It includes an MCU, a watchdog circuit, an LTO circuit, and a protection circuit, where: The MCU is connected to the main circuit for power supply and operation; the watchdog circuit is electrically connected to the MCU and the LTO circuit respectively, and is used to receive the watchdog signal provided by the MCU and output a signal level to the LTO circuit when the watchdog signal is not received; the LTO circuit is electrically connected to the protection circuit, and is used to cut off the power supply of the main circuit after the protection circuit receives the signal level.

2. The MCU downtime protection circuit according to claim 1, wherein The watchdog circuit includes a watchdog chip U9, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, and a third capacitor; the watchdog chip U9 includes 9 ports. The first port is respectively connected to the working voltage terminal and one end of the second capacitor, and the other end of the second capacitor is grounded to GND; the second port is connected in series with the first capacitor and grounded to GND; the third port is suspended; the fourth port is grounded to GND; the fifth port is respectively connected to one end of the second resistor and one end of the third resistor. The other end of the second resistor is connected to the working voltage terminal, and the other end of the second resistor is grounded to GND. Both ends of the third capacitor are respectively connected to the fifth port and the other end of the second resistor; the sixth port is a signal input port and is connected to the MCU; the seventh port is a signal output port; the eighth port is connected in series with the first resistor and connected to the working voltage terminal; the ninth port is grounded to GND.

3. The MCU crash protection circuit according to claim 2, wherein, The LTO circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor, a first diode, and a first triode; the base of the first triode is connected in series with the fifth resistor and accesses the seventh port, the emitter is connected to the working voltage terminal, and the collector is successively connected in series with the eighth resistor and the first diode and accesses the LTO. Both ends of the fourth resistor are respectively connected to the emitter and the base; one end of the fourth capacitor accesses the node between the eighth resistor and the first diode, and the other end is grounded to GND; the fifth capacitor and the seventh resistor are both connected in parallel across both ends of the fourth capacitor.

4. The MCU downtime protection circuit according to claim 3, characterized in that, The protection circuit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a sixth capacitor, a first field-effect transistor, and a second diode; the gate of the first field-effect transistor is connected in series with the eleventh resistor and accesses the negative terminal of the second diode, the source is grounded to GND, and the drain is successively connected in series with the ninth resistor and the tenth resistor and accesses the 12V power supply voltage; the positive terminal of the second diode is connected to the LTO; the sixth capacitor and the twelfth resistor are both connected in parallel across between the gate and the source of the first field-effect transistor.

5. The MCU downtime protection circuit according to claim 4, wherein The protection circuit further includes a thirteenth resistor, a first zener diode, and a second field-effect transistor; the gate of the second field-effect transistor is connected to the node between the ninth resistor and the tenth resistor, the source is connected to the 12V power supply voltage, and the drain is connected to one end of the thirteenth resistor; the first zener diode is connected in parallel across between the gate and the source of the second field-effect transistor.

6. The MCU downtime protection circuit according to claim 5, characterized in that, The protection circuit further includes a fourteenth resistor, a seventh capacitor, a second zener diode, a third diode, a third field-effect transistor, a first connector, and a fuse set; the gate of the third field-effect transistor is connected to the other end of the thirteenth resistor, the source is grounded to GND, and the drain is connected to the negative terminal of the third diode; the positive terminal of the third diode is connected to the fuse set through the first connector; the fourteenth resistor, the seventh capacitor, and the second zener diode are all connected in parallel between the gate and the source of the third field-effect transistor.

7. The MCU crash protection circuit according to claim 6, wherein, The fuse set is connected in series in the main circuit and includes a first fuse, a second fuse, and a third fuse connected in parallel.

8. The MCU crash protection circuit according to claim 3, characterized in that, The first triode is a PNP type triode.

9. The MCU downtime protection circuit according to claim 6, wherein The second field-effect transistor is a P-type MOS transistor, and the first field-effect transistor and the third field-effect transistor are both N-type MOS transistors.

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