Chip standby power adaptive circuit
Through the combination of the main power judgment circuit and the main power/support selection circuit, the power path of the SOC chip is monitored and switched in real time, which solves the problem of short button battery usage time, and realizes the efficient utilization of the backup power supply and the simplified design of the SOC chip.
Patent Information
- Application Number
- CN202422309735.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-09-23
AI Technical Summary
The prior art has problems such as power consumption and performance trade-offs, increased complexity or abnormal backflow current in improving the use time of button batteries, making it difficult to effectively extend the use time of the SOC chip power supply.
The main power judgment circuit and main power/support selection circuit are used to monitor the main power supply voltage in real time, and control the power path switching using PMOS transistors and non-overlapping circuits to ensure that the main power is used when the main power is normal, and switch to the backup power when it is too low to avoid the diode conduction voltage drop and abnormal backflow current.
It realizes reducing backup power consumption within the reasonable range of the main power supply, extending the usage time of backup power supply, and avoids abnormal current and voltage drop during power switching, simplifying the SOC chip design.
Smart Images
Figure CN223124654U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of chips, and particularly relates to a chip backup power supply adaptive circuit. Background Art
[0002] In an SOC chip, there are usually two power supplies, namely the main power supply and the backup power supply. The main power supply usually refers to the core power supply, which is usually provided by an external switching power supply or a regulated power supply of the chip, and the backup power supply refers to the standby or auxiliary power supply, which is usually provided by a button battery. The design of the main power supply and the backup power supply is crucial for ensuring the stable operation of the SOC chip. For example, in a GNSS SOC chip, the main power supply usually needs to meet the voltage and current requirements of the radio frequency receiver, the digital baseband, and the core logic circuit, while the backup power supply is usually used to support the low-power mode or other auxiliary functions. Due to the limitation of the charge amount of the button battery, for example, the capacity of a CR2032 type button battery is generally about 200 mAh, and the capacity of a small battery such as CR2016 is generally about 75 mAh. Therefore, in order to increase the usage time of the button battery, it is usually necessary to reduce the power consumption of the backup power supply part of the SOC chip.
[0003] In order to increase the usage time of the button battery and reduce the power consumption of the backup power supply part of the SOC chip, the prior art can reduce the circuit power consumption in the backup power supply area of the chip through some methods, which requires a comprehensive trade-off between power consumption and circuit performance. Reducing the circuit power consumption generally sacrifices some performance of the corresponding circuit. In addition, a specific charging chip can be used to connect the main power supply and the backup power supply of the SOC chip. When the charge amount of the backup power supply part is insufficient, the main power supply charges the backup power supply, or this part of the charging function is integrated into the SOC, which requires more area of the SOC and also increases the complexity of the SOC design. Another way is to connect the main power supply and the backup power supply of the chip through a forward diode. When the charge amount of the backup power supply is insufficient, the backup power supply area of the chip is provided by the main power supply. When the charge amount of the backup power supply is sufficient, due to the reverse bias effect of the diode, the main power supply and the backup power supply are equivalent to an open circuit. This way will generate abnormal reverse leakage current from the main power supply to the backup power supply in some cases, and the diode will also consume a certain voltage, reducing the voltage value of the actual backup power supply area of the SOC chip. Summary of the Utility Model
[0004] The purpose of the utility model is to provide a chip backup power supply adaptive circuit, which can monitor and judge the main power supply in real time. When the main power supply is within a reasonable range, all modules in the backup power supply area of the chip use the main power supply. When the main power supply is too low, all modules in the backup power supply area of the chip will use the backup power supply, so as to reduce the consumption of the backup power supply and extend the usage time of the backup power supply, so as to solve the problems put forward in the above background art.
[0005] To achieve the above object, the present utility model adopts the following technical solutions: A chip backup power supply adaptive circuit, comprising:
[0006] A main power supply judgment circuit, configured to monitor the main power supply voltage in real time and judge whether the main power supply is within a reasonable range according to a set threshold;
[0007] A main power / backup power selection circuit, selectively connecting the main power supply or the backup power supply to the backup power area of the SOC chip according to the output signal of the main power judgment circuit;
[0008] A comparator circuit, whose positive input terminal is connected to the main power divided voltage signal, and the negative input terminal is connected to the internal reference voltage signal, for comparing the main power divided voltage with the reference voltage;
[0009] A debounce circuit, configured to eliminate the jitter in the output signal of the comparator circuit;
[0010] A non-overlapping circuit, generating a phase control signal based on the output signal of the debounce circuit;
[0011] Four PMOS transistors, wherein the source terminal of the first PMOS transistor is connected to the backup power supply, the gate terminal is connected to the phase 1 control signal generated by the non-overlapping circuit, and the drain terminal is connected to the drain terminal of the second PMOS transistor; the gate terminal of the second PMOS transistor is connected to the phase 2 control signal generated by the non-overlapping circuit, and the source terminal is connected to the chip backup power area; the source terminal of the third PMOS transistor is connected to the main power supply, the gate terminal is connected to the phase 3 control signal generated by the non-overlapping circuit, and the drain terminal is connected to the drain terminal of the fourth PMOS transistor; the gate terminal of the fourth PMOS transistor is connected to the phase 4 control signal generated by the non-overlapping circuit, and the source terminal is connected to the chip backup power area;
[0012] A first resistor and a second resistor, used to form a voltage division network of the main power supply, and the output of the voltage division network is connected to the positive input terminal of the comparator circuit.
[0013] Preferably, the main power supply obtains the main power divided voltage signal through a voltage division network formed by the first resistor and the second resistor.
[0014] Preferably, the non-overlapping circuit can generate four phase control signals under different conditions according to the output signal of the debounce circuit to control the switching states of the four PMOS transistors.
[0015] Preferably, when the main power voltage is normal, the non-overlapping circuit outputs high-level phase 1 and phase 2 control signals, and low-level phase 3 and phase 4 control signals, so that the first PMOS transistor and the second PMOS transistor are turned off, and the third PMOS transistor and the fourth PMOS transistor are turned on.
[0016] Preferably, when the main power supply voltage is too low, the non-overlapping circuit outputs low-level control signals for phase 1 and phase 2, and high-level control signals for phase 3 and phase 4, causing the first PMOS transistor and the second PMOS transistor to turn on, and the third PMOS transistor and the fourth PMOS transistor to turn off.
[0017] Preferably, the debounce circuit is further configured to eliminate the instantaneous fluctuations caused by the change of the main power supply voltage.
[0018] Preferably, when the main power supply voltage is normal, the non-overlapping circuit forms a fully-conductive path between the main power supply and the chip backup power area, and there is no diode conduction voltage drop.
[0019] Preferably, when the main power supply voltage is too low, the non-overlapping circuit forms a fully-conductive path between the backup power supply and the chip backup power area, and there is no diode conduction voltage drop.
[0020] Technical effects and advantages of the present utility model: An adaptive circuit for chip backup power proposed by the present utility model has the following advantages compared with the prior art:
[0021] In the backup power area of the chip of the present utility model, a main power judgment circuit and a main power / backup power selection circuit are added, which can monitor and judge the main power supply in real time. When the main power supply is within a reasonable range, all modules in the chip's backup power area use the main power supply. When the main power supply is too low, all modules in the chip's backup power area will use the backup power supply, which can reduce the consumption of the backup power supply and extend the usage time of the backup power supply. Description of the Drawings
[0022] Figure 1 is the structural block diagram of the adaptive circuit for chip backup power of the present utility model;
[0023] Figure 2 is the circuit diagram of the main power judgment circuit of the present utility model;
[0024] Figure 3 is the circuit structure diagram of the main power / backup power selection circuit of the present utility model;
[0025] Figure 4 is the overall circuit diagram of the adaptive circuit for chip backup power of the present utility model. Detailed Embodiments
[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.
[0027] The present invention provides a chip backup power supply adaptive circuit, including: a main power supply judgment circuit and a main power supply / backup power supply selection circuit. The main power supply judgment circuit includes a comparator circuit, a debounce circuit, and a non-overlap circuit. The main power supply / backup power supply selection circuit includes a switch array composed of four PMOS transistors. Specifically as follows:
[0028] Exemplarily, the main power supply judgment circuit is used to monitor the main power supply voltage in real time and judge whether the main power supply is within a reasonable range according to the set threshold.
[0029] Exemplarily, the main power supply / backup power supply selection circuit selectively connects the main power supply or the backup power supply to the backup power supply area of the SOC chip according to the output signal of the main power supply judgment circuit; the main power supply obtains the main power supply voltage division signal through the voltage division network formed by the first resistor and the second resistor.
[0030] Exemplarily, the positive input terminal of the comparator circuit is connected to the main power supply voltage division signal, and the negative input terminal is connected to the internal reference voltage signal, which is used to compare the main power supply voltage division with the reference voltage;
[0031] Exemplarily, the debounce circuit is used to eliminate the jitter in the output signal of the comparator circuit; in addition, the debounce circuit is also used to eliminate the instantaneous fluctuation caused by the change of the main power supply voltage.
[0032] Exemplarily, the non-overlap circuit generates a phase control signal based on the output signal of the debounce circuit; the non-overlap circuit can generate four phase control signals under different conditions according to the output signal of the debounce circuit to control the switching states of the four PMOS transistors, as follows:
[0033] When the main power supply voltage is normal, the phase 1 and phase 2 control signals output by the non-overlap circuit are high levels, and the phase 3 and phase 4 control signals are low levels, so that the first PMOS transistor and the second PMOS transistor are turned off, and the third PMOS transistor and the fourth PMOS transistor are turned on.
[0034] When the main power supply voltage is too low, the non-overlapping circuit outputs control signals for phase 1 and phase 2 as low levels, and control signals for phase 3 and phase 4 as high levels, causing the first PMOS transistor and the second PMOS transistor to turn on, and the third PMOS transistor and the fourth PMOS transistor to turn off.
[0035] In one embodiment, when the main power supply voltage is normal, the non-overlapping circuit forms a fully conductive path between the main power supply and the chip backup power supply area, and there is no diode conduction voltage drop.
[0036] In one embodiment, when the main power supply voltage is too low, the non-overlapping circuit forms a fully conductive path between the backup power supply and the chip backup power supply area, and there is no diode conduction voltage drop.
[0037] Exemplarily, the source terminal of the first PMOS transistor is connected to the backup power supply, the gate terminal is connected to the phase 1 control signal generated by the non-overlapping circuit, and the drain terminal is connected to the drain terminal of the second PMOS transistor; the gate terminal of the second PMOS transistor is connected to the phase 2 control signal generated by the non-overlapping circuit, and the source terminal is connected to the chip backup power supply area; the source terminal of the third PMOS transistor is connected to the main power supply, the gate terminal is connected to the phase 3 control signal generated by the non-overlapping circuit, and the drain terminal is connected to the drain terminal of the fourth PMOS transistor; the gate terminal of the fourth PMOS transistor is connected to the phase 4 control signal generated by the non-overlapping circuit, and the source terminal is connected to the chip backup power supply area;
[0038] Exemplarily, the first resistor and the second resistor are used to form a voltage division network of the main power supply, and the output of the voltage division network is connected to the positive terminal input of the comparator circuit.
[0039] The following will be described in detail with reference to the accompanying drawings:
[0040] As Figures 1-4 shown, the circuit structure of this embodiment includes a comparator circuit, a debounce circuit, a non-overlapping circuit, 4 PMOSs and 2 resistors.
[0041] The source terminal of the first PMOS is connected to the backup power supply, the gate terminal is connected to the phase 1 control signal, and the drain terminal is connected to the drain terminal of the second PMOS. The drain terminal of the second PMOS is connected to the drain terminal of the first PMOS, the gate terminal is connected to the phase 2 control signal, and the source terminal is connected to the chip backup power supply area. The source terminal of the third PMOS is connected to the main power supply, the gate terminal is connected to the phase 3 control signal, and the drain terminal is connected to the drain terminal of the fourth PMOS. The drain terminal of the fourth PMOS is connected to the drain terminal of the third PMOS, the gate terminal is connected to the phase 4 control signal, and the source terminal is connected to the chip backup power supply area.
[0042] The main power supply is also connected to the ground through a first resistor and a second resistor. According to the principle of resistor voltage division, the divided main power value is equal to the main power voltage multiplied by the value of the second resistor divided by the sum of the resistances of the first resistor and the second resistor. The divided main power is connected to the positive input of the comparator circuit, the internal reference voltage of the chip is connected to the negative input of the comparator circuit, and the output of the comparator circuit is connected to a debounce circuit, which is used to eliminate the misjudgment caused by the jitter of the main power supply. The input of the debounce circuit is connected to the input of the non-overlapping circuit, which is used to generate different control signals from phase 1 to phase 4 to control the corresponding PMOS to turn on or off.
[0043] The working process of this embodiment is as follows:
[0044] Turn on the backup power self-adaptive circuit of the embodiment.
[0045] Monitor the main power supply of the chip: that is, the main power supply is divided by the first resistor and the second resistor to obtain the divided main power. The divided main power is compared with the reference voltage inside the chip. When the output result of the comparator is high, it indicates that the main power voltage is normal. When the output result of the comparator is low, it indicates that the main power voltage is too low. In order to eliminate the influence caused by the jitter of the main power supply, the output of the comparator circuit needs to be processed by the debounce circuit. When the input of the debounce circuit is continuously at a logic high level for a period of time, the output of the debounce circuit is at a high level. When the input of the debounce circuit is continuously at a logic low level for a period of time, the output of the debounce circuit is at a low level, so as to eliminate the misjudgment caused by the jitter of the main power supply.
[0046] Generate corresponding control signals according to the output of the debounce circuit: when the output of the debounce circuit is at a logic high level, it indicates that the main power voltage is normal, and the backup power area of the chip should select the main power supply as its power supply. The outputs of the non-overlapping circuit are that the phase 1 control signal and the phase 2 control signal are at a logic high level, and the phase 3 and phase 4 control signals are at a logic low level, that is, the first PMOS and the second PMOS are turned off, and the third PMOS and the fourth PMOS are turned on. When the output of the debounce circuit is at a logic low level, it indicates that the main power voltage is too low, and the backup power area of the chip should select the backup power supply as its power supply. The outputs of the non-overlapping circuit are that the phase 1 control signal and the phase 2 control signal are at a logic low level, and the phase 3 and phase 4 control signals are at a logic high level, that is, the first PMOS and the second PMOS are turned on, and the third PMOS and the fourth PMOS are turned off.
[0047] Power supply voltage selection for the backup power supply area: When the phase 1 control signal and the phase 2 control signal are at logic high level, and the phase 3 and phase 4 control signals are at logic low level, the backup power supply is connected to the backup power supply area through an equivalent reverse-biased diode and a forward-biased diode, which can effectively isolate the backup power supply from the backup power supply area. The main power supply and the backup power supply area are connected through two fully open PMOSs, that is, the main power supply and the backup power supply area are in a fully conducting state, there is no conduction voltage drop of the diode, and at the same time, there will be no abnormal reverse current from the main power supply to the backup power supply or from the backup power supply to the main power supply. When the phase 1 control signal and the phase 2 control signal are at logic low level, and the phase 3 and phase 4 control signals are at logic high level, the main power supply is connected to the backup power supply area through an equivalent reverse-biased diode and a forward-biased diode, which can effectively isolate the main power supply from the backup power supply area. The backup power supply and the backup power supply area are connected through two fully open PMOSs, that is, the backup power supply and the backup power supply area are in a fully conducting state, there is no conduction voltage drop of the diode, and at the same time, there will be no abnormal reverse current from the main power supply to the backup power supply or from the backup power supply to the main power supply.
[0048] In this way, this embodiment can monitor and judge the main power supply in real time. When the main power supply is within a reasonable range, all modules in the backup power supply area of the chip use the main power supply. When the main power supply is too low, all modules in the backup power supply area of the chip will use the backup power supply. This can reduce the consumption of the backup power supply and extend the service life of the backup power supply.
[0049] The utility model can monitor the main power supply in real time. When the main power supply is within a reasonable range, all modules of the chip use the main power supply, which can reduce the consumption of the backup power supply and extend the service life of the backup power supply. It can be integrated inside the chip without an additional power chip, which is beneficial to the design integration inside the SOC. Through the description of the working process, no abnormal reverse current from the main power supply to the backup power supply or from the backup power supply to the main power supply will be generated in this embodiment. Through the description of the working process, when the main power supply is connected to the backup power supply area and the backup power supply is connected to the backup power supply area, it is in a fully conducting state, and there is no conduction voltage drop of the diode.
[0050] Finally, it should be noted that the above are only the preferred embodiments of the utility model and are not used to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.
Claims
1. A chip backup power supply adaptive circuit, characterized in that, Including: The main power supply judgment circuit is used to monitor the main power supply voltage in real time and judge whether the main power supply is within a reasonable range according to the set threshold; The main power / backup power selection circuit selectively connects the main power supply or the backup power supply to the backup power area of the SOC chip according to the output signal of the main power judgment circuit; The comparator circuit, whose positive terminal input is connected to the main power divided voltage signal and the negative terminal input is connected to the internal reference voltage signal, is used to compare the main power divided voltage with the reference voltage; The debounce circuit is used to eliminate the jitter in the output signal of the comparator circuit; The non-overlap circuit generates a phase control signal based on the output signal of the debounce circuit; Four PMOS transistors, where the source terminal of the first PMOS transistor is connected to the backup power supply, the gate terminal is connected to the phase 1 control signal generated by the non-overlap circuit, and the drain terminal is connected to the drain terminal of the second PMOS transistor; the gate terminal of the second PMOS transistor is connected to the phase 2 control signal generated by the non-overlap circuit, and the source terminal is connected to the chip backup power area; the source terminal of the third PMOS transistor is connected to the main power supply, the gate terminal is connected to the phase 3 control signal generated by the non-overlap circuit, and the drain terminal is connected to the drain terminal of the fourth PMOS transistor; the gate terminal of the fourth PMOS transistor is connected to the phase 4 control signal generated by the non-overlap circuit, and the source terminal is connected to the chip backup power area; The first resistor and the second resistor are used to form a voltage division network of the main power supply, and the output of the voltage division network is connected to the positive terminal input of the comparator circuit.
2. The chip power backup adaptive circuit according to claim 1, characterized in that The main power supply obtains the main power divided voltage signal through the voltage division network formed by the first resistor and the second resistor.
3. The chip backup power supply adaptive circuit according to claim 1, characterized in that, The non-overlap circuit can generate four phase control signals under different conditions according to the output signal of the debounce circuit to control the switching states of the four PMOS transistors.
4. The chip backup power supply adaptive circuit according to claim 3, wherein When the main power voltage is normal, the non-overlap circuit outputs high-level phase 1 and phase 2 control signals and low-level phase 3 and phase 4 control signals, so that the first PMOS transistor and the second PMOS transistor are turned off, and the third PMOS transistor and the fourth PMOS transistor are turned on.
5. The chip backup power supply adaptive circuit according to claim 3, characterized in that, When the main power voltage is too low, the non-overlap circuit outputs low-level phase 1 and phase 2 control signals and high-level phase 3 and phase 4 control signals, so that the first PMOS transistor and the second PMOS transistor are turned on, and the third PMOS transistor and the fourth PMOS transistor are turned off.
6. The chip power backup adaptive circuit according to claim 1, wherein The debounce circuit is also used to eliminate the instantaneous fluctuation caused by the change of the main power supply voltage.
7. The self-adaptive circuit for chip backup power supply according to claim 1, characterized in that When the main power voltage is normal, the non-overlap circuit forms a fully conductive path between the main power supply and the chip backup power area, and there is no diode conduction voltage drop.
8. The chip backup power supply adaptive circuit according to claim 1, wherein When the main power voltage is too low, the non-overlap circuit forms a fully conductive path between the backup power supply and the chip backup power area, and there is no diode conduction voltage drop.