Multi-port multi-protocol high-speed switching equipment based on FPGA (Field Programmable Gate Array)

Abstract

The utility model discloses a multi-port multi-protocol high-speed switching device based on an FPGA. The multi-port multi-protocol high-speed switching device comprises an MCU, a plurality of FPGA modules, a plurality of ASM interfaces, a CPLD module, a plurality of QSPINOR modules and a QSPI channel control module. Wherein the MCU is electrically connected with the plurality of FPGA modules, the plurality of FPGA modules are connected in series, the plurality of ASM interfaces are electrically connected with the plurality of FPGA modules, the MCU is electrically connected with the plurality of ASM interfaces, one end of the CPLD module is electrically connected with the MCU, the other end of the CPLD module is electrically connected with the plurality of FPGA modules, and the plurality of QSPI NOR modules are electrically connected with the MCU and the plurality of FPGA modules through the QSPI channel control module. According to the multi-port multi-protocol high-speed switching equipment based on the FPGA provided by the invention, a plurality of ASM interfaces can be extended through a plurality of FPGA modules, so that the ports of the switch are sufficient, and therefore, multi-protocol conversion or resource expansion can be carried out.

Description

Technical Field

[0001] This application relates to the technical field of switches, and specifically relates to a multi-port multi-protocol high-speed switching device based on FPGA. Background Art

[0002] A switch is a network device used to connect different computers and other network devices in a local area network. It plays an important role in the network, can effectively manage data streams, and ensure that information is transmitted between the correct devices.

[0003] Currently, conventional switch devices can usually only convert one protocol and cannot convert multiple protocols, which limits their flexibility in dealing with multiple network protocols. When facing multiple downstream devices or devices with different protocols, the switch has no extra ports for interaction, facing the problem of insufficient ports, which affects the effective communication between devices. In addition, the signal rate of conventional switches is often difficult to guarantee, resulting in high latency. In contrast, when the CPU on the server motherboard performs data exchange through the built-in interconnect interface, the latency is low, but it is also difficult to achieve high speed, low latency, and good quality when communicating between multiple servers. Summary of the Utility Model

[0004] Therefore, this application provides a multi-port multi-protocol high-speed switching device based on FPGA to solve the problem of insufficient switch ports existing in the prior art.

[0005] To achieve the above purpose, this application provides the following technical solutions:

[0006] A multi-port multi-protocol high-speed switching device based on FPGA includes an MCU, multiple FPGA modules, multiple ASM interfaces, a JTAG interface module, a CPLD module, multiple QSPINOR modules, a QSPI channel control module, an EMMC module, an RJ45 network interface module, a URAT serial port module, a button module, a fan, a power module, and an EEPROM module;

[0007] The MCU is electrically connected to multiple FPGA modules. The multiple FPGA modules are connected in series. Multiple ASM interfaces are electrically connected to the multiple FPGA modules. The output ends of the multiple FPGA modules are electrically connected to the input end of the JTAG interface module. The output end of the MCU is electrically connected to the input ends of the multiple ASM interfaces. One end of the CPLD module is electrically connected to the MCU, and the other end is electrically connected to the multiple FPGA modules. Multiple QSPINOR modules are electrically connected to the MCU and the multiple FPGA modules through the QSPI channel control module. The EMMC module, the RJ45 network interface module, the URAT serial port module, the button module, the fan, the power supply module, and the EEPROM module are all electrically connected to the MCU.

[0008] Preferably, the FPGA modules include a first FPGA module and a second FPGA module. The QSPI NOR modules include a first QSPI NOR module and a second QSPI NOR module. There are 24 ASM interfaces. The MCU is electrically connected to the first FPGA module and the second FPGA module. The first FPGA module and the second FPGA module are connected in series. The first QSPINOR module and the second QSPI NOR module are respectively electrically connected to the MCU, the first FPGA module, and the second FPGA module through the QSPI channel control module. One end of the CPLD module is electrically connected to the MCU, and the other end is electrically connected to the first FPGA module and the second FPGA module. 12 of the ASM interfaces are electrically connected to the first FPGA module, and the other 12 ASM interfaces are electrically connected to the second FPGA module.

[0009] Preferably, the QSPI channel control module includes a first switch selector, a second switch selector, and a third switch selector. The first end of the first switch selector is electrically connected to the first QSPI NOR module. The second end of the first switch selector is electrically connected to the output end of the MCU. The third end of the first switch selector is electrically connected to the first FPGA module. The fourth end of the first switch selector is electrically connected to the third end of the third switch selector. The first and second ends of the third switch selector are electrically connected to the MCU. The fourth end of the third switch selector is electrically connected to the third end of the second switch selector. The first end of the second switch selector is electrically connected to the second QSPINOR module. The second end of the second switch selector is electrically connected to the output end of the MCU. The fourth end of the second switch selector is electrically connected to the second FPGA module.

[0010] Preferably, the models of the first switch selector, the second switch selector, and the third switch selector are all: RS0204YQ.

[0011] Preferably, it further includes an ETH PHY module, and the RJ45 network interface module is electrically connected to the MCU through the ETH PHY module.

[0012] Preferably, the interface signals of the multiple ASM interfaces are one or more of PCIE signals or CXL signals.

[0013] Preferably, the model of the MCU is: R7FA6M4AD3CFB.

[0014] Preferably, the model of the FPGA module is: XCVU13P.

[0015] Compared with the prior art, the present application has at least the following beneficial effects:

[0016] The present application provides a multi-port multi-protocol high-speed switching device based on FPGA, including an MCU, multiple FPGA modules, multiple ASM interfaces, a JTAG interface module, a CPLD module, multiple QSPINOR modules, a QSPI channel control module, an EMMC module, an RJ45 network interface module, a URAT serial port module, a button module, a fan, a power module, and an EEPROM module; wherein, the MCU is electrically connected to multiple FPGA modules, the multiple FPGA modules are connected in series, the multiple ASM interfaces are electrically connected to the multiple FPGA modules, the output ends of the multiple FPGA modules are electrically connected to the input end of the JTAG interface module, the output end of the MCU is electrically connected to the input ends of the multiple ASM interfaces, one end of the CPLD module is electrically connected to the MCU, and the other end is electrically connected to the multiple FPGA modules, the multiple QSPINOR modules are electrically connected to the MCU and the multiple FPGA modules through the QSPI channel control module, and the EMMC module, the RJ45 network interface module, the URAT serial port module, the button module, the fan, the power module, and the EEPROM module are all electrically connected to the MCU, and the EEPROM module is also electrically connected to the power module. The multi-port multi-protocol high-speed switching device based on FPGA provided by the present application can extend multiple ASM interfaces through multiple FPGA modules, and the multiple ASM interfaces make the switch ports sufficient, so that various protocol conversions or resource expansions can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more intuitively illustrate the existing technology and this application, the following exemplary drawings are provided. It should be understood that the specific shapes and structures shown in the drawings generally should not be regarded as limiting conditions when implementing this application; for example, those skilled in the art are capable of making routine adjustments or further optimizations to the addition / deletion / attribution division of certain units (components), specific shapes, positional relationships, connection methods, dimensional proportional relationships, etc. based on the technical concept disclosed in this application and the exemplary drawings.

[0018] Figure 1 It is a structural principle block diagram of a multi-port multi-protocol high-speed switching device based on FPGA provided by this application;

[0019] Figure 2 It is the schematic diagram of the first part of the circuit of the MCU provided by this application;

[0020] Figure 3 It is the schematic diagram of the second part of the circuit of the MCU provided by this application;

[0021] Figure 4 It is the schematic diagram of the third part of the circuit of the MCU provided by this application;

[0022] Figure 5 It is the schematic diagram of the first part of the circuit of the FPGA module provided by this application;

[0023] Figure 6 It is the schematic diagram of the second part of the circuit of the FPGA module provided by this application;

[0024] Figure 7 It is the schematic diagram of the third part of the circuit of the FPGA module provided by this application;

[0025] Figure 8 It is the schematic diagram of the fourth part of the circuit of the FPGA module provided by this application;

[0026] Figure 9 It is the schematic diagram of the ASM interface circuit provided by this application;

[0027] Figure 10 It is the schematic diagram of the CPLD module circuit provided by this application;

[0028] Figure 11 It is the schematic diagram of the switch selector circuit provided by this application;

[0029] Figure 12 It is the schematic diagram of the EMMC module circuit provided by this application;

[0030] Figure 13 It is the schematic diagram of the RJ45 network interface module circuit provided by this application;

[0031] Figure 14The circuit schematic diagram of the URAT serial port module provided for this application;

[0032] Figure 15 The circuit schematic diagram of the key module provided for this application;

[0033] Figure 16 The circuit schematic diagram of the fan control provided for this application;

[0034] Figure 17 The circuit schematic diagram of the ETH PHY module provided for this application. Detailed implementation manners

[0035] The following further details this application through specific embodiments in conjunction with the accompanying drawings.

[0036] In the description of this application: Unless otherwise specified, "a plurality of" means two or more. Terms such as "first", "second", "third", etc. in this application are intended to distinguish the objects being referred to, and do not have special significance in terms of technical connotations (for example, it should not be understood as emphasizing the importance level or order, etc.). Expressions such as "including", "comprising", "having", etc. also mean "not limited to" (certain units, components, materials, steps, etc.).

[0037] Terms such as "upper", "lower", "left", "right", "middle", etc. cited in this application are usually indications of the general relative position relationship for the convenience of intuitively understanding with reference to the accompanying drawings, and are not absolute limitations on the position relationship in the actual product.

[0038] Please refer to Figure 1 , this application provides a multi-port multi-protocol high-speed switching device based on FPGA, including an MCU, a plurality of FPGA modules, a plurality of ASM interfaces, a JTAG interface module, a CPLD module, a plurality of QSPI NOR modules, a QSPI channel control module, an EMMC module, an RJ45 network interface module, a URAT serial port module, a key module (PWRKEY), a fan (FANS), a power supply module (PUS), and an EEPROM module (EEPROM).

[0039] Among them, the MCU is electrically connected to multiple FPGA modules, the multiple FPGA modules are connected in series, multiple ASM interfaces are electrically connected to the multiple FPGA modules, the output ends of the multiple FPGA modules are electrically connected to the input end of the JTAG interface module, the output end of the MCU is electrically connected to the input ends of the multiple ASM interfaces, one end of the CPLD module is electrically connected to the MCU, and the other end is electrically connected to the multiple FPGA modules. The multiple QSPINOR modules are electrically connected to the MCU and the multiple FPGA modules through the QSPI channel control module. The EMMC module, RJ45 network interface module, URAT serial port module, button module, fan, power supply module, and EEPROM module are all electrically connected to the MCU.

[0040] In this application, there are two FPGA modules, including a first FPGA module and a second FPGA module. The first FPGA module and the second FPGA module interact through the internal logic of the FPGA, and 24 ASM interfaces can be extended. Correspondingly, there are also two QSPINOR modules, including a first QSPINOR module and a second QSPINOR module. Among them, the MCU is electrically connected to the first FPGA module and the second FPGA module. The first FPGA module and the second FPGA module are connected in series. The first QSPINOR module and the second QSPINOR module are electrically connected to the MCU, the first FPGA module, and the second FPGA module through the QSPI channel control module respectively. One end of the CPLD module is electrically connected to the MCU, and the other end is electrically connected to the first FPGA module and the second FPGA module. 12 ASM interfaces are electrically connected to the first FPGA module, and the other 12 ASM interfaces are electrically connected to the second FPGA module. In this application, the two FPGA modules are the core of the multi-port. Through the internal logic of the FPGA, 24 ASM interfaces can be extended, which can be PCIE signals or CXL signals. Different expansions can be achieved through these ASM interfaces. For example, a memory resource pool can be connected downstream for memory expansion; or a GPU or CPU can be connected to achieve the interconnection of the GPU and CPU.

[0041] In this application, the QSPI channel control module includes a first switch selector SW1, a second switch selector SW2, and a third switch selector SW3. The first end of the first switch selector SW1 is electrically connected to the first QSPI NOR module, the second end of the first switch selector SW1 is electrically connected to the output end of the MCU, the third end of the first switch selector SW1 is electrically connected to the first FPGA module, the fourth end of the first switch selector SW1 is electrically connected to the third end of the third switch selector SW3, the first and second ends of the third switch selector SW3 are electrically connected to the MCU, the fourth end of the third switch selector SW3 is electrically connected to the third end of the second switch selector SW2, the first end of the second switch selector SW2 is electrically connected to the second QSPI NOR module, the second end of the second switch selector SW2 is electrically connected to the output end of the MCU, and the fourth end of the second switch selector SW2 is electrically connected to the second FPGA module.

[0042] Specifically, please refer to Figure 2 , Figure 3 and Figure 4 . In this application, the MCU is used to implement the startup of the entire board, program update, status debugging, and fan speed, etc. The preferred model of the MCU is: R7FA6M4AD3CFB, which belongs to the RA6M4 series of chips. This MCU is suitable for Internet of Things applications that require Ethernet connection, future security protection, large-capacity embedded RAM, and low power consumption (as low as 99 uA / MHz when running algorithms). It also supports a capacitive sensing unit, has 20 channels, and has a built-in security encryption engine, providing a secure element function.

[0043] Specifically, please refer to Figure 5 , Figure 6 , Figure 7 and Figure 8, in this application, the preferred model of the FPGA module is: XCVU13P. XCVU13P is an FPGA (Field Programmable Gate Array) model in the AMD (formerly Xilinx) Virtex UltraScale+ series. FPGAs in this series are renowned for their high performance and high integration, and are suitable for compute-intensive applications such as high-speed networking, machine learning, radar / early warning systems, etc. The features of the Virtex UltraScale+ FPGA series include: 3D-on-3D integration technology, achieving high density and high bandwidth using FinFET technology; enhanced DSP cores, providing up to 38TOPs of computing performance, optimized for fixed-point and floating-point calculations; high-speed serial transceivers, supporting a data transfer rate of 32.75Gb / s, with up to 128 transceivers on the device; integrated PCIe blocks, supporting 100G applications; high-speed memory support, including DDR4 and on-chip caches, as well as up to 8GB of integrated HBM Gen2 memory within the package. The XCVU13P model specifically provides: 3.78M system logic units, 12,288 DSP slices, 455Mb of internal memory, and 128 GTY / GTM serial transceivers (32.75 / 58Gb / s).

[0044] Specifically, please refer to Figure 9 , in this application, the ASM interface is an application-specific module interface. In this application, 24 ASM interfaces can be extended through interaction with the internal logic of the FPGA. These interfaces can be PCIE signals or CXL signals, and different expansions can be achieved through these ASM interfaces.

[0045] Specifically, the JTAG interface module (JTAG CON) is a standard interface for connecting digital circuits, commonly used for debugging and testing. JTAG CON is an important hardware interface for implementing JTAG test and debugging functions, and is widely used in the design, testing, and maintenance of electronic products.

[0046] Specifically, please refer to Figure 10 , in this application, the CPLD module is a complex programmable logic device used to control timing. When the entire device is powered on, pressing the key module (PWRKEY) notifies the MCU that it can power on. The MCU will send a signal to the CPLD, and then the CPLD starts the power-on process. The CPLD module is a system that controls the power-on logic of the entire board and is also a system for level conversion of the entire board. Through the CPLD, the power-on and power-off times can be strictly controlled to ensure the normal startup of the FPGA. In this application, the MCU is in the 3.3V voltage domain, and the FPGA is in the 1.8V voltage domain. Therefore, the signal interaction between them is achieved through the CPLD for level conversion.

[0047] Specifically, in this application, the QSPINOR module is a high-speed non-volatile memory interface and memory type. QSPINOR refers to a NOR Flash memory using the QSPI interface. It combines the high-speed data transfer capability of the QSPI protocol and the random access characteristics of NOR Flash. Using the QSPI interface can significantly improve the data transfer rate of NOR Flash, making it suitable for embedded systems and storage applications with higher performance requirements.

[0048] Specifically, please refer to Figure 11 , in this application, the QSPI channel control module includes a first switch selector SW1, a second switch selector SW2, and a third switch selector SW3. The first switch selector SW1, the second switch selector SW2, and the third switch selector SW3 are the same, and their model numbers are all: RS0204YQ, and the package form is TSSOP-14.

[0049] Specifically, please refer to Figure 12 , in this application, the EMMC module is an embedded multimedia card, which is commonly used in mobile devices, consumer electronics products, and embedded systems. The EMMC provides non-volatile storage functions for storing operating systems, application programs, and user data. In this application, the EMMC is the place where the FPGA module runs log storage.

[0050] Specifically, please refer to Figure 13 , this application can burn the program of the FPGA through the RJ45 network port module to update the program. The program of the FPGA is saved in the QSPIFLUSH (i.e., the QSPINOR module). The MCU controls the QSPI channel through the high and low of the SW signal. By default, the QPSIFLUSH is connected to the FPGA. When the program needs to be updated, the QSPIFLUSH is connected to the MCU, and the download and burning are performed online through the RJ45. After completion, the QSPI channel is switched back to the FPGA.

[0051] Specifically, please refer to Figure 14 , the URAT serial port module is a URAT serial port provided by the MCU. The current status of the FPGA can be viewed through the URAT serial port, and debugging can also be performed.

[0052] Specifically, please refer to Figure 15 , the key module (PWRKEY) is mainly used for startup. After the device is powered on, it is started by pressing the PWRKEY button.

[0053] Specifically, please refer to Figure 16, in this application, the MCU receives the core temperature of the FPGA through the SPI signal and controls the rotation speed of the fan (FANS) through PWM. By default, the fan runs at full speed. It should be noted that multiple fans can be set.

[0054] A multi-port multi-protocol high-speed switching device based on FPGA provided by this application further includes an ETH PHY module, and the circuit schematic diagram of the ETH PHY module is as Figure 17 shown. In this application, the RJ45 network interface module is electrically connected to the MCU through the ETH PHY module, and the ETH PHY module is an Ethernet physical layer device.

[0055] In a multi-port multi-protocol high-speed switching device based on FPGA provided by this application, the MCU can view the status of each device through I2C, such as: PSU power supply, peripherals of the FPGA downstream port, clock chip status, etc.

[0056] A multi-port multi-protocol high-speed switching device based on FPGA provided by this application can extend multiple ASM interfaces through multiple FPGA modules. The multiple ASM interfaces make the switch ports sufficient, so that various protocol conversions or resource expansions can be carried out, thereby ensuring effective communication between devices, and the entire device has the advantages of high speed, low latency and good quality.

[0057] Specifically, the multi-port multi-protocol high-speed switching device based on FPGA provided by this application has sufficient ports, can perform resource expansion, and can support multi-protocol diffusion, such as: PCIE and CXL, etc., and can also support devices with multiple upstream and downstream ports, and the signal quality can be guaranteed. When the CPU resources are insufficient, the resources can be expanded through this device; the number of device interactions has been upgraded, supporting 24 ASM downstream ports; the signal processing isolates the high-speed line and the low-speed line, ensuring the signal quality and integrity; through the signal multiplexing technology, the resource utilization rate is optimized, enabling the switching device to efficiently process multi-protocol data.

[0058] The technical features of the above embodiments can be combined arbitrarily (as long as there is no contradiction in the combination of these technical features). For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described; these embodiments not explicitly written should also be considered as within the scope described in this specification.

Claims

1. A multi-port multi-protocol high-speed switching device based on FPGA, characterized in that It includes an MCU, multiple FPGA modules, multiple ASM interfaces, a JTAG interface module, a CPLD module, multiple QSPINOR modules, a QSPI channel control module, an EMMC module, an RJ45 network interface module, a URAT serial port module, a button module, a fan, a power supply module, and an EEPROM module; The MCU is electrically connected to the multiple FPGA modules. The multiple FPGA modules are connected in series. The multiple ASM interfaces are electrically connected to the multiple FPGA modules. The output ends of the multiple FPGA modules are electrically connected to the input end of the JTAG interface module. The output end of the MCU is electrically connected to the input ends of the multiple ASM interfaces. One end of the CPLD module is electrically connected to the MCU, and the other end is electrically connected to the multiple FPGA modules. The multiple QSPINOR modules are electrically connected to the MCU and the multiple FPGA modules through the QSPI channel control module. The EMMC module, the RJ45 network interface module, the URAT serial port module, the button module, the fan, the power supply module, and the EEPROM module are all electrically connected to the MCU.

2. The multi-port multi-protocol high-speed switching device based on FPGA according to claim 1, characterized in that, The FPGA module includes a first FPGA module and a second FPGA module. The QSPI NOR module includes a first QSPINOR module and a second QSPINOR module. There are 24 ASM interfaces. The MCU is electrically connected to the first FPGA module and the second FPGA module. The first FPGA module and the second FPGA module are connected in series. The first QSPINOR module and the second QSPINOR module are electrically connected to the MCU, the first FPGA module, and the second FPGA module respectively through the QSPI channel control module. One end of the CPLD module is electrically connected to the MCU, and the other end is electrically connected to the first FPGA module and the second FPGA module. 12 of the ASM interfaces are electrically connected to the first FPGA module, and the other 12 ASM interfaces are electrically connected to the second FPGA module.

3. The multi-port multi-protocol high-speed switching device based on FPGA according to claim 2, wherein The QSPI channel control module includes a first switch selector, a second switch selector, and a third switch selector. The first end of the first switch selector is electrically connected to the first QSPINOR module. The second end of the first switch selector is electrically connected to the output end of the MCU. The third end of the first switch selector is electrically connected to the first FPGA module. The fourth end of the first switch selector is electrically connected to the third end of the third switch selector. The first and second ends of the third switch selector are electrically connected to the MCU. The fourth end of the third switch selector is electrically connected to the third end of the second switch selector. The first end of the second switch selector is electrically connected to the second QSPI NOR module. The second end of the second switch selector is electrically connected to the output end of the MCU. The fourth end of the second switch selector is electrically connected to the second FPGA module.

4. The multi-port multi-protocol high-speed switching device based on FPGA according to claim 3, wherein The models of the first switch selector, the second switch selector, and the third switch selector are all: RS0204YQ.

5. The multi-port multi-protocol high-speed switching device based on FPGA according to claim 1, characterized in that It further includes an ETH PHY module, and the RJ45 network interface module is electrically connected to the MCU through the ETH PHY module.

6. The multi-port multi-protocol high-speed switching device based on FPGA according to claim 1, characterized in that, The interface signals of multiple said ASM interfaces are one or more of PCIE signals or CXL signals.

7. The multi-port multi-protocol high-speed switching device based on FPGA according to claim 1, wherein The model of the MCU is: R7FA6M4AD3CFB.

8. The multi-port multi-protocol high-speed switching device based on FPGA according to claim 1, characterized in that, The model of the FPGA module is: XCVU13P.

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