Signal generating device and testing machine
By using a combination of arbitrary waveform generator and an external clock chip control module in semiconductor testing, the problem of frequency in DDS technology is solved, flexible waveform generation is achieved, and the convenience and efficiency of the test machine are improved.
Patent Information
- Application Number
- CN202421324489.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-11
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-06-11
AI Technical Summary
In semiconductor testing, traditional DDS technology cannot flexibly set the signal frequency due to the limitation of the fixed reference clock, resulting in low testing convenience and cannot meet the test requirements of high precision and high frequency.
The external clock chip control module is adopted to control the external clock chip output sampling clock through the external clock chip control module, and the waveform data is converted across the clock domain with any waveform generator to achieve flexible adjustment of frequency, length and shape.
It improves the testing convenience and efficiency of the test machine, and can generate waveform signals of any frequency, any length, and any shape, meet different test needs and save preparation time.
Smart Images
Figure CN223139674U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technologies, and particularly to a signal generating device and a tester. Background Art
[0002] Semiconductor automatic testing refers to using Automatic Test Equipment (ATE) to detect various parameter indicators of a Device Under Test (DUT), and eliminating defective products to control the ex-factory quality of semiconductor devices. In analog testing, especially high-speed analog testing, there are often very high requirements for test signals transmitted to the device under test, such as harmonics, signal-to-noise ratio, amplitude, signal frequency, etc.
[0003] Traditional test signal generation schemes adopt DDS (Direct Digital Synthesizer) technology. DDS mainly consists of a phase accumulator and a ROM waveform lookup table, using a clock with a fixed frequency accuracy as a reference clock, and generating an output signal with adjustable frequency and phase through digital signal processing technology. By controlling the phase of the waveform to read the waveform file in the ROM, waveforms with different frequencies are generated. Due to the limitation of the fixed reference clock, DDS cannot flexibly set the signal frequency, cannot meet the test requirements, and has the disadvantage of low test convenience. Summary of the Utility Model
[0004] Based on this, it is necessary to provide a signal generating device and a tester that can improve test convenience for the above problems.
[0005] In the first aspect of this application, a signal generating device is provided, including: at least one arbitrary waveform generator, an external clock chip control module, an external clock chip, and a storage device;
[0006] The external clock chip control module is connected to the external clock chip and controls the external clock chip to output a sampling clock according to a clock configuration instruction;
[0007] The arbitrary waveform generator is connected to the external clock chip and the storage device, reads waveform data from the storage device according to a waveform configuration instruction, and performs clock domain conversion on the waveform data based on the sampling clock output by the external clock chip.
[0008] In one of the embodiments, the arbitrary waveform generator includes:
[0009] A waveform request module, connected to a first read / write control module and a waveform transmission control module, sends a data read instruction to the first read / write control module according to the received waveform configuration instruction, and sends the waveform data returned by the first read / write control module to the waveform transmission control module;
[0010] The first read / write control module, connected to the storage device, reads waveform data from the storage device according to the data read instruction and returns it to the waveform request module;
[0011] The waveform transmission control module, connected to the external clock chip, performs cross-clock domain conversion on the waveform data according to the sampling clock output by the external clock chip.
[0012] In one embodiment, the arbitrary waveform generator further includes:
[0013] A waveform data processing module, connected to the waveform request module and the waveform transmission control module, processes the received waveform data and sends it to the waveform transmission control module.
[0014] In one embodiment, the waveform data processing module includes an amplitude selection unit, a DC calibration unit, and / or an AC calibration unit.
[0015] In one embodiment, the waveform transmission control module includes a FIFO buffer unit, and the FIFO buffer outputs the waveform data after cross-clock domain conversion after receiving a trigger signal.
[0016] In one embodiment, the arbitrary waveform generator further includes:
[0017] A RAM storage control module, connected to the waveform request module and the waveform data processing module;
[0018] When the waveform length in the waveform configuration instruction is greater than or equal to a preset threshold length, the waveform request module sends the waveform data read from the storage device to the waveform data processing module;
[0019] When the waveform length is less than the preset threshold length, the waveform request module stores the waveform data read from the storage device in the RAM storage control module for the waveform data processing module to read the waveform data.
[0020] In one embodiment, the signal generating device further includes:
[0021] A second read / write control module, which writes the waveform file sent by the host computer into the storage device;
[0022] The service decoding module is connected to the host computer, the external clock chip control module, the waveform request module, the first read / write control module, and the second read / write control module. It parses and generates the clock configuration instruction, the first read / write control instruction, the second read / write control instruction, and the waveform configuration instruction according to the control instructions issued by the host computer, and sends the clock configuration instruction, the first read / write control instruction, the second read / write control instruction, and the waveform configuration instruction to the external clock chip control module, the first read / write control module, the second read / write control module, and the waveform request module respectively.
[0023] In one embodiment, the signal generating device further includes:
[0024] An arbitration module, connected to the first read / write control module, the second read / write control module, and the storage device, for arbitrating and controlling the first read / write control instruction and the second read / write control instruction.
[0025] In one embodiment, the external clock chip control module is connected to the external clock chip through an SPI interface.
[0026] In one embodiment, the signal generating device further includes an external crystal oscillator, and the external crystal oscillator is connected to the arbitrary waveform generator to output a system clock to the arbitrary waveform generator.
[0027] A second aspect of the present application provides a testing machine, including:
[0028] A host computer;
[0029] The above-mentioned signal generating device, which receives the control instructions and waveform files issued by the host computer and generates waveform data for cross-clock domain conversion.
[0030] The above-mentioned signal generating device and testing machine control the external clock chip to output a sampling clock according to the clock configuration instruction through the external clock chip control module, and perform cross-clock domain conversion on the read waveform data in combination with the arbitrary waveform generator. The frequency of the output waveform data can be adjusted according to actual needs to meet different testing requirements and improve testing convenience. Description of the Drawings
[0031] Figure 1 Is a structural block diagram of the signal generating device in one embodiment;
[0032] Figure 2 Is a structural schematic diagram of the signal generating device in one embodiment;
[0033] Figure 3 Is a structural schematic diagram of the testing machine in one embodiment. Detailed Embodiments
[0034] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0036] It can be understood that in the following embodiments, "connection", if there is an electrical signal or data transfer between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc.
[0037] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, wholes, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.
[0038] At present, due to the limitation of the fixed reference clock, the waveforms generated by the DDS cannot achieve a very high frequency accuracy, and the waveforms generated can only be an integer number of sampling points within a period, and the signal frequency cannot be flexibly set, and the design requirements for high-frequency signals of any frequency cannot be flexibly met. Based on this, the present application provides a signal generating device, including at least one arbitrary waveform generator (AWG), an external clock chip control module, an external clock chip and a storage device. The external clock chip control module controls the external clock chip to output a sampling clock according to a clock configuration instruction, and combines the arbitrary waveform generator to perform cross-clock domain conversion on the read waveform data, and the frequency of the output waveform data can be adjusted according to actual needs, and waveforms of any frequency, any length and any shape can be generated, which saves a large amount of preparation time during the use of the tester and greatly improves the test efficiency of the tester, meeting different test requirements.
[0039] In one embodiment, as Figure 1As shown in the figure, a signal generating device 100 is provided, which includes an arbitrary waveform generator 110, an external clock chip control module 111, an external clock chip 120, and a storage device 130. The number of the arbitrary waveform generators 110 can be one or more. The external clock chip control module 111 is connected to the external clock chip 120, the arbitrary waveform generator 110 is connected to the external clock chip 120 and the storage device 130, and the external clock chip control module 111 controls the external clock chip 120 to output a sampling clock according to a clock configuration instruction; the arbitrary waveform generator 110 reads waveform data from the storage device 130 according to a waveform configuration instruction, and performs clock domain conversion on the waveform data based on the sampling clock output by the external clock chip 120.
[0040] Among them, as Figure 2 shown, the arbitrary waveform generator 110 includes a waveform request module 112, a first read / write control module 113, and a waveform transmission control module 114. The waveform request module 112 is connected to the first read / write control module 113 and the waveform transmission control module 114. The first read / write control module 113 is connected to the storage device 130, and the waveform transmission control module 114 is connected to the external clock chip 120. In addition, the signal generating device 100 may further include a digital-to-analog conversion device 140. The digital-to-analog conversion device 140 is connected to the external clock chip 120 and the waveform transmission control module 114. The number of the digital-to-analog conversion devices 140 can be one, or two or more, specifically corresponding one-to-one to the number of the arbitrary waveform generators 110. Each arbitrary waveform generator 110 outputs the waveform data after cross-clock domain conversion to the corresponding digital-to-analog conversion device 140.
[0041] Among them, the external clock chip control module 111 controls the external clock chip 120 to output a sampling clock according to a clock configuration instruction. The waveform request module 112 sends a data reading instruction to the first read / write control module 113 according to the received waveform configuration instruction. The first read / write control module 113 reads waveform data from the storage device 130 according to the data reading instruction and returns it to the waveform request module 112. The waveform request module 112 sends the waveform data returned by the first read / write control module 113 to the waveform transmission control module 114. The waveform transmission control module 114 performs cross-clock domain conversion on the waveform data according to the sampling clock output by the external clock chip 120. The digital-to-analog conversion device 140 receives the waveform data after cross-clock domain conversion output by the waveform transmission control module 114, and performs digital-to-analog conversion on the waveform data after cross-clock domain conversion according to the sampling clock output by the external clock chip 120.
[0042] Among them, the external clock chip control module 111 can receive the clock configuration instructions sent by the host computer. The clock configuration instructions can include parameters such as the integer multiple frequency and decimal multiple frequency of the clock. The arbitrary waveform generator 110 and the external clock chip control module 111 can be set inside the FPGA (Field-Programmable Gate Array), and the external clock chip 120, the storage device 130, and the digital-to-analog conversion device 140 are located outside the FPGA. The host computer can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, and portable wearable devices. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, etc. In addition, as Figure 2 shown, the signal generating device 100 may further include an external crystal oscillator 150. The external crystal oscillator 150 is also located outside the FPGA. The external crystal oscillator 150 is connected to the arbitrary waveform generator 110 and outputs a system clock to the arbitrary waveform generator 110 for relevant modules in the arbitrary waveform generator 110 to perform corresponding functions.
[0043] Specifically, the external clock chip control module 111 can be connected to the external clock chip 120 through an SPI (Serial Peripheral Interface) interface. Taking the arbitrary waveform generator 110 located inside the FPGA as an example, accurate sampling clocks cannot be generated inside the FPGA. Therefore, the external clock chip 120 is used to provide sampling clock signals. The external clock chip 120 can adopt a clock chip with an output frequency range of 1M to 200M and a clock frequency accuracy of the mHz level to meet the requirements of a large sampling clock frequency range and high accuracy requirements of the testing machine. When the external clock chip 120 is powered on and initialized, it can output a clock signal with a fixed frequency of 200M. The external clock chip control module 111 controls the external clock chip 120 according to the clock configuration instructions sent by the host computer to make it output sampling clocks with different frequencies. The external clock chip 120 outputs two paths of sampling clocks. One path is sent to the digital-to-analog conversion device 140, and the other path is sent to the waveform sending control module 114. After the host computer sends the clock configuration instructions to the external clock chip control module 111, the external clock chip control module 111 performs read and write operations on the registers of the external clock chip 120 through the SPI interface. At this time, the external clock chip control module 111 stores the read and write related parameters separately to avoid problems caused by simultaneous read and write conflicts. In addition, the locking state of the external clock chip 120 can also be monitored by sending instructions from the host computer.
[0044] The waveform configuration instruction may specifically include the waveform start address, waveform length, and number of repetitions, and may also include parameters such as a preparation instruction, a trigger instruction, a stop instruction, and a trigger mode. The arbitrary waveform generator 110 may receive the waveform configuration instruction sent by the host computer or the waveform configuration instruction customarily input by the operator. According to the received waveform configuration instruction, the waveform request module 112 sends a corresponding data reading instruction to the first read / write control module 113, and the first read / write control module 113 reads data in the storage device 130. After receiving the waveform data returned by the first read / write control module 113, the waveform request module 112 may also send the waveform data to the waveform sending control module 114 according to the trigger signal and the number of repetitions sent by the host computer.
[0045] Since the sampling clock of the digital-to-analog conversion device 140 is provided by the external clock chip 120, the data sent to the digital-to-analog conversion device 140 should also be sent with the sampling clock as the reference clock. Therefore, it is necessary to cache the read waveform data in the waveform sending control module 114 and convert it to the clock domain of the sampling clock. The waveform sending control module 114 may specifically include a FIFO (First Input First Output) buffer to cache the waveform data for cross-clock domain conversion, converting from the system clock to the clock domain of the sampling clock, and then sending the converted waveform data to the digital-to-analog conversion device 140 for digital-to-analog conversion to generate a waveform signal. The digital-to-analog conversion device 140 may specifically adopt a high-speed digital-to-analog converter to perform digital-to-analog conversion processing on the received waveform data according to the sampling clock to obtain an analog waveform signal output.
[0046] Among them, the waveform request module 112 is default in the idle state when powered on. After receiving the preparation instruction, it starts to request waveform data. The requested address is the waveform start address, the requested length is the waveform length, and the requested number of repetitions is the number of repetitions sent by the host computer. When the storage device 130 returns the requested waveform data, the waveform request module 112 jumps to the ready-to-start state. When in the ready-to-start state, after receiving the trigger signal, the waveform request module 112 jumps to the sending state and starts to send the waveform data to the digital-to-analog conversion device 140. When receiving the stop instruction, the waveform request module 112 jumps to the idle state, stops the data request state, and clears the cached data. When in the sending state, when there is no data in the local cache, the waveform request module 112 jumps to the send-complete state; when in the send-complete state, when the trigger mode is external trigger, it automatically requests data from the storage device 130, and when there is data in the local cache, it jumps to the ready-to-start state. When the trigger mode is internal trigger, the waveform request module 112 jumps back to the idle state.
[0047] Further, the storage device 130 is a DDR (Double Data Rate) storage device. Specifically, the DDR storage device can be a DDR3 storage device, which stores the waveform files generated by the host computer or the custom waveform files. The DDR storage device can store multiple waveform files with large data volumes and supports the storage of custom waveform files, improving the test efficiency of the tester.
[0048] In one embodiment, as Figure 2 shown, the arbitrary waveform generator 110 further includes a waveform data processing module 115. The waveform data processing module 115 is connected to the waveform request module 112 and the waveform transmission control module 114, and sends the received waveform data to the waveform transmission control module 114 after data processing. Among them, the waveform data processing module 115 may include an amplitude selection unit, a DC (direct current) calibration unit, and / or an AC (alternating current) calibration unit, which perform amplitude selection, DC calibration, AC calibration, etc. on the received waveform data. The processed waveform data is sent to the waveform transmission control module 114 for cross-clock domain conversion. Among them, amplitude selection is that the host computer selects different amplitude signals for output according to different requirements; DC calibration is to compensate for the DC precision loss of the hardware link so that it can meet certain DC precision requirements; AC calibration is to compensate for the AC precision loss of the hardware link so that the AC precision at any frequency point meets the AC precision requirements.
[0049] In addition, the arbitrary waveform generator 110 further includes a RAM (Random Access Memory) storage control module 116. The RAM storage control module 116 is connected to the waveform request module 112 and the waveform data processing module 115. When the waveform length in the waveform configuration instruction is greater than or equal to the preset threshold length, the waveform request module 112 sends the waveform data read from the storage device 130 to the waveform data processing module 115. When the waveform length is less than the preset threshold length, the waveform request module 112 stores the waveform data read from the storage device 130 in the RAM storage control module 116 for the waveform data processing module 115 to read the waveform data.
[0050] The specific value of the preset threshold length is not unique and can be set according to actual needs. When the waveform length is greater than or equal to the preset threshold length, the waveform request module 112 directly sends the waveform data read from the storage device 130 to the waveform data processing module 115; when the waveform length is less than the preset threshold length, the waveform request module 112 sends the read waveform data to the RAM storage control module 116 for storage, and the waveform data processing module 115 reads the waveform data from the RAM storage control module 116. After obtaining the waveform data in the waveform request module 112 or the RAM storage control module 116, the waveform data processing module 115 performs processing such as amplitude selection, DC calibration, and AC calibration on the waveform data and then outputs it to the waveform sending control module 114.
[0051] After reading the data, if the waveform length is less than the preset threshold length, the waveform request module 112 stores the waveform data read from the storage device 130 into the local RAM storage control module 116 to reduce the large sacrifice of DDR bandwidth for small data (since the waveform length may be very small, the DDR bandwidth utilization rate is very low for a very short clock, which is not sufficient to support the continuous output of the waveform. At this time, the waveform file needs to be stored in the RAM storage control module 116, and the waveform data output is controlled from the RAM storage control module 116). The RAM storage control module 116 can support waveform repeated reading operations, support continuous waveform data output, and also support stop reading operations. When the waveform length is relatively small, the waveform data is stored in the RAM storage control module 116, and the RAM storage control module 116 is used to achieve continuous output of the waveform.
[0052] Furthermore, the waveform sending control module 114 can also first store the waveform data after cross-clock domain conversion into the FIFO buffer, and immediately read out the waveform data after cross-clock domain conversion and send it to the digital-to-analog conversion device 140 after receiving the trigger (TRIG) signal, which can minimize the trigger delay. The trigger signal can be sent through the sending control module, and the sending control module can be the upper computer or a separate functional module. At the same time, the sending control module is also used to control the synchronization signal between channels, and the control logic is: if only one data channel is enabled, the trigger signal takes effect immediately; if multiple data channels are enabled simultaneously, the two trigger signals are ORed bitwise and then take effect, which can ensure the synchronization of the waveform data output by the two data channels. The output control of the waveform is realized according to the instructions issued by the upper computer, and single trigger and external continuous trigger functions can also be realized according to different trigger modes, controlling the output points and repetition times of the waveform, etc. Among them, single trigger means triggering the digital waveform to output a waveform for one cycle, and the clock of the output digital waveform at this time is the sampling clock; continuous trigger means outputting waveforms for multiple consecutive cycles.
[0053] Continue to refer toFigure 2 The signal generating device 100 further includes a second read / write control module 117. The second read / write control module 117 is directly or indirectly connected to the storage device 130, and can receive a waveform file sent by a host computer or a waveform file custom-input by an operator, and store the waveform file in the storage device 130.
[0054] The signal generating device 100 may further include a service decoding module 118. The service decoding module 118 is connected to the host computer, the external clock chip control module 111, the waveform request module 112, the first read / write control module 113, and the second read / write control module 117. It parses and generates a clock configuration instruction, a first read / write control instruction, a second read / write control instruction, and a waveform configuration instruction according to the control instruction sent by the host computer, and sends the clock configuration instruction, the first read / write control instruction, the second read / write control instruction, and the waveform configuration instruction to the external clock chip control module 111, the first read / write control module 113, the second read / write control module 117, and the waveform request module 112 respectively.
[0055] Communicate with the host computer through the service decoding module 118, decode the control instruction sent by the host computer according to the communication protocol format. The control instruction mainly includes: a clock configuration instruction for controlling the external clock chip 120 to output different clocks, an instruction for reading whether the external clock chip 120 is locked, a DDR read / write control instruction (including a first read / write control instruction and a second read / write control instruction), a waveform configuration instruction, a sending status reading instruction, etc. The service decoding module 118 sends the parsed control instruction to the corresponding module to implement functions such as clock configuration, waveform configuration, and status monitoring.
[0056] In addition, the signal generating device 100 may further include an arbitration module 119. The arbitration module 119 is connected to the first read / write control module 113, the second read / write control module 117, and the storage device 130, and performs arbitration control on the first read / write control instruction and the second read / write control instruction. Specifically, any waveform generator 110, the external clock chip control module 111, the second read / write control module 117, the service decoding module 118, and the arbitration module 119 can be set in the same FPGA. The storage device 130 uses a DDR3 storage device, and its bandwidth is sufficient to support multi-channel simultaneous read / write operations. The arbitration module 119 can simultaneously arbitrate the first read / write control instruction and the second read / write control instruction, support arbitrating and writing the waveform file into the storage device 130 at the same moment, and arbitrating and writing the waveform data read from the storage device 130 into multiple waveform request modules 112, ensuring that multiple channels can simultaneously perform read / write operations on the storage device 130.
[0057] In one embodiment, as Figure 3As shown, a testing machine is also provided, which includes a host computer 210 and the above-mentioned signal generating device. The signal generating device receives the control instructions and waveform files issued by the host computer 210 and generates waveform data for cross-clock domain conversion.
[0058] For the above-mentioned signal generating device and testing machine, the host computer 210 can generate waveform files and store them in the DDR storage device. At this time, the waveform files can have any period and any amplitude. The sampling clock of the digital-to-analog conversion device 140 can be set to any fractional frequency, and the signal generating device can emit waveform signals of any frequency. Since the waveform files are stored in the DDR storage device, large amounts of waveform files can be stored, and custom waveform transmission can also be achieved.
[0059] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0060] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A signal generating device, characterized in that, Comprising: At least one arbitrary waveform generator, an external clock chip control module, an external clock chip, and a storage device; The external clock chip control module is connected to the external clock chip and controls the external clock chip to output a sampling clock according to a clock configuration instruction; The arbitrary waveform generator is connected to the external clock chip and the storage device, reads waveform data from the storage device according to a waveform configuration instruction, and performs clock domain conversion on the waveform data based on the sampling clock output by the external clock chip.
2. The signal generating device according to claim 1, characterized in that, The arbitrary waveform generator includes: A waveform request module, connected to a first read / write control module and a waveform transmission control module, sends a data read instruction to the first read / write control module according to a received waveform configuration instruction, and sends the waveform data returned by the first read / write control module to the waveform transmission control module; The first read / write control module is connected to the storage device, reads waveform data from the storage device according to the data read instruction, and returns it to the waveform request module; The waveform transmission control module is connected to the external clock chip and performs cross-clock domain conversion on the waveform data according to the sampling clock output by the external clock chip.
3. The signal generating device according to claim 2, wherein The arbitrary waveform generator further includes: A waveform data processing module, connected to the waveform request module and the waveform transmission control module, processes the received waveform data and sends it to the waveform transmission control module.
4. The signal generating device according to claim 3, characterized in that, The waveform data processing module includes an amplitude selection unit, a DC calibration unit, and / or an AC calibration unit.
5. The signal generating device according to claim 2, characterized in that, The waveform transmission control module includes a FIFO buffer, and the FIFO buffer outputs the waveform data after cross-clock domain conversion after receiving a trigger signal.
6. The signal generating device according to claim 3, wherein, The arbitrary waveform generator further includes: A RAM storage control module, connected to the waveform request module and the waveform data processing module; When the waveform length in the waveform configuration instruction is greater than or equal to a preset threshold length, the waveform request module sends the waveform data read from the storage device to the waveform data processing module; When the waveform length is less than the preset threshold length, the waveform request module stores the waveform data read from the storage device in the RAM storage control module for the waveform data processing module to read the waveform data.
7. The signal generating device according to claim 2, wherein The signal generating device further includes: A second read / write control module, which writes a waveform file sent by a host computer into the storage device; A service decoding module, connected to the host computer, the external clock chip control module, the waveform request module, the first read / write control module, and the second read / write control module, parses and generates the clock configuration instruction, the first read / write control instruction, the second read / write control instruction, and the waveform configuration instruction according to a control instruction sent by the host computer, and sends the clock configuration instruction, the first read / write control instruction, the second read / write control instruction, and the waveform configuration instruction to the external clock chip control module, the first read / write control module, the second read / write control module, and the waveform request module respectively.
8. The signal generating device according to claim 7, wherein The signal generating device further includes: An arbitration module, connected to the first read / write control module, the second read / write control module, and the storage device, performs arbitration control on the first read / write control instruction and the second read / write control instruction.
9. The signal generating device according to any one of claims 1-8, characterized in that, The external clock chip control module is connected to the external clock chip through an SPI interface.
10. The signal generating device according to any one of claims 1-8, characterized in that, The signal generating device further includes an external crystal oscillator, and the external crystal oscillator is connected to the arbitrary waveform generator to output a system clock to the arbitrary waveform generator.
11. A testing machine, characterized in that, Comprising: A host computer; The signal generating device according to any one of claims 1-10, receiving a control instruction and a waveform file issued by the host computer, and generating waveform data for cross-clock domain conversion.