Signal generation device and method, analog-digital hybrid test board, and test machine

Abstract

A signal generation device and method, an analog-digital hybrid test board, and a test machine. The signal generation device comprises: an arbitrary waveform generator, a read / write control module, an external clock chip, and a storage device; the external clock chip is configured to output a fixed-frequency sampling clock to a digital-to-analog conversion device; the read / write control module is connected to the arbitrary waveform generator and the storage device, and is configured to read an original waveform from the storage device on the basis of a received read request instruction, and return the read original waveform to the arbitrary waveform generator; and the arbitrary waveform generator is configured to perform resampling processing on the received original waveform to generate a reconstructed waveform matching the frequency of the sampling clock, wherein the reconstructed waveform is used by the digital-to-analog conversion device to perform digital-to-analog conversion on the basis of the sampling clock outputted by the external clock chip.

Description

Signal generation device, method, mixed analog-to-digital test board and test machine

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on October 18, 2024, application number 202411457686.7, entitled “Signal Generating Apparatus, Method, Analog-Digital Mixed Test Board and Tester”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor testing technology, and in particular to a signal generating device, method, mixed-signal test board, and test machine. Background Technology

[0004] Semiconductor automated testing refers to the use of automated test equipment (ATE) to inspect various parameters of the device under test (DUT), eliminating defective products and controlling the quality of semiconductor devices before they leave the factory. In analog testing, especially high-speed analog testing, the test signals sent to the DUT often have very high requirements in terms of harmonics, signal-to-noise ratio, amplitude, and signal frequency. When implementing IQ (in-phase and quadrature) functionality, the test equipment needs to ensure IQ channel synchronization.

[0005] Traditional test signal generation methods adjust the sampling clock phase of the DAC (Digital-to-Analog Converter) in the IQ channels by changing the frequency of the clock signal output by the clock circuit, thereby synchronizing the IQ channels. This method of outputting test signals by adjusting the DAC sampling clock phase has complex control logic, is cumbersome to operate, and suffers from low test efficiency.

[0006] There is currently no effective solution to the problems of complex control logic, cumbersome operation, and low testing efficiency in the output test signal methods of related technologies. Summary of the Invention

[0007] According to various embodiments of this application, a signal generating apparatus, method, mixed analog-to-digital test board, and test machine are provided.

[0008] The first aspect of this application provides a signal generating device, including: an arbitrary waveform generator, a read / write control module, an external clock chip, and a storage device;

[0009] The external clock chip is used to output a fixed-frequency sampling clock to the digital-to-analog converter.

[0010] The read / write control module connects the arbitrary waveform generator and the storage device, and is used to read the original waveform from the storage device according to the received read request instruction, and return the read original waveform to the arbitrary waveform generator;

[0011] The arbitrary waveform generator is used to resample the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock; wherein, the reconstructed waveform is used by the digital-to-analog converter to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

[0012] In one embodiment, the arbitrary waveform generator includes:

[0013] A waveform request module, connected to the read / write control module and the waveform data processing module, is used to send read request commands to the read / write control module and to send the raw waveform returned by the read / write control module to the waveform data processing module.

[0014] The waveform data processing module is used to resample the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock.

[0015] In one embodiment, the arbitrary waveform generator further includes:

[0016] The synchronization control module is connected to the waveform data processing module and is used to cache the reconstructed waveform in an internal cache module, and output the reconstructed waveform in the internal cache module after receiving a trigger signal.

[0017] In one embodiment, the waveform data processing module includes:

[0018] The calibration module, connected to the waveform request module, is used to calibrate the received raw waveform and output the calibrated waveform data.

[0019] A digital resampling module, connected to the calibration module, is used to resample the calibrated waveform data to generate a reconstructed waveform that matches the frequency of the sampling clock.

[0020] In one embodiment, the calibration module includes at least one of a DC (Direct Current) calibration module and an AC (Alternating Current) amplitude calibration module.

[0021] In one embodiment, the digital resampling module includes:

[0022] An input waveform data caching module is connected to the calibration module, the effective position calculation module, and the effective data caching module. It is used to cache the calibrated waveform data and send a start signal to the effective position calculation module when the number of cached data exceeds a set threshold. It also reads the effective data corresponding to the effective position from the cached data according to the received read enable signal and sends the read effective data to the effective data caching module for caching.

[0023] The effective position calculation module is connected to the effective coefficient generation module. After receiving the start signal, it calculates the effective position information according to the set step and initial phase, sends it to the effective coefficient generation module, and sends a read enable signal to the input waveform data buffer module.

[0024] The effective coefficient generation module is connected to the data calculation module and the effective data cache module. It is used to read coefficients from multiple pre-stored coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module.

[0025] The effective data caching module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal.

[0026] The data calculation module is used to perform convolution calculations based on the received effective coefficients and effective data to obtain the reconstructed waveform.

[0027] In one embodiment, the effective data caching module stores the effective data in parallel into consecutive internal cache units using a shifting method; and / or the effective coefficient generation module reads two adjacent sets of coefficients based on the integer position information of the effective position information, and calculates the effective coefficients by using a linear interpolation algorithm on the two sets of coefficients read based on the decimal position information of the effective position information.

[0028] In one embodiment, the data calculation module performs convolution calculations based on the received valid coefficients and valid data, including:

[0029] Wherein, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

[0030] In one embodiment, the signal generating device further includes:

[0031] The delay module connects the arbitrary waveform generator to the corresponding digital-to-analog converter. Each arbitrary waveform generator is also used to synchronously send valid data to the corresponding digital-to-analog converter according to the on-path clock sent by the digital-to-analog converter.

[0032] In one embodiment, the signal generating device further includes:

[0033] The service decoding module connects to the host computer, the external clock chip, the read / write control module, and the arbitrary waveform generator. It configures the parameters of the external clock chip and the arbitrary waveform generator according to the instructions issued by the host computer, and stores the original waveform to the storage device through the read / write control module.

[0034] A second aspect of this application provides a signal generation method, comprising:

[0035] An external clock chip outputs a fixed-frequency sampling clock to the digital-to-analog converter;

[0036] The read / write control module reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator;

[0037] The arbitrary waveform generator resamples the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock; wherein, the reconstructed waveform is used by the digital-to-analog converter to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

[0038] A third aspect of this application provides a mixed-signal test board, including the signal generating device described above.

[0039] The fourth aspect of this application provides a test machine, including a communication board, a backplane, and the aforementioned mixed analog-to-digital test board.

[0040] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0042] Figure 1 is a structural block diagram of a signal generating device in one embodiment.

[0043] Figure 2 is a schematic diagram of the signal generating device in one embodiment.

[0044] Figure 3 is a schematic diagram of the waveform data processing module in one embodiment.

[0045] Figure 4 is a schematic diagram of the principle of digital resampling in one embodiment.

[0046] Figure 5 is a flowchart of a signal generation method in one embodiment. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0049] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0050] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0051] In one embodiment, as shown in FIG1, a signal generating device is provided, including an arbitrary waveform generator (AWG) 110, a read / write control module 120, an external clock chip 130, and a storage device 140. The read / write control module 120 is connected to the arbitrary waveform generator 110 and the storage device 140. Further, the signal generating device may also include a digital-to-analog converter (DAC) 150 connected to the arbitrary waveform generator 110. The external clock chip 130 is used to output a fixed-frequency sampling clock to the DAC 150. The read / write control module 120 is used to read the original waveform from the storage device 140 according to a received read request instruction and return the read original waveform 140 to the arbitrary waveform generator 110. The arbitrary waveform generator 110 is used to resample the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock. The reconstructed waveform is used by the DAC 150 for digital-to-analog conversion based on the sampling clock output by the external clock chip 130.

[0052] The arbitrary waveform generator 110 generates a reconstructed waveform whose frequency matches the sampling clock. This can mean that the sampling rate of the reconstructed waveform is the same as the frequency of the sampling clock, or that the error between the sampling rate of the reconstructed waveform and the frequency of the sampling clock is within an allowable range. The external clock chip 130 can be a PLL (Phase Locked Loop) clock chip, and the storage device 140 can be a DDR (Double Data Rate) storage device composed of DDR4 chips. The number of arbitrary waveform generators 110 can be one or more, and the number of digital-to-analog converters 150 corresponds one-to-one with the number of arbitrary waveform generators 110. For example, for the IQ channel of the test machine, an arbitrary waveform generator 110 and a digital-to-analog converter 150 can be set up respectively. After the read / write control module 120 reads the original waveform according to the received read request instruction, it returns the read original waveform to the arbitrary waveform generator 110 of the corresponding channel. After receiving the original waveform, the arbitrary waveform generator 110 performs DC (direct current) calibration, AC (alternating current) calibration, resampling and other processing to generate a reconstructed waveform, which is sent to the corresponding digital-to-analog converter 150 for digital-to-analog conversion processing to obtain an analog waveform signal output, which is used to test semiconductor chips and other devices under test. Among them, in order to meet the requirements of the digital-to-analog converter 150, the frequency of the original waveform arbitrarily set by the user is less than or equal to the sampling clock frequency output by the external clock chip 130.

[0053] Furthermore, as shown in Figure 2, the signal generating device also includes a service decoding module 160. The service decoding module 160 is connected to a host computer, an external clock chip 130, a read / write control module 120, and an arbitrary waveform generator 110. It configures the parameters of the external clock chip 130 and the arbitrary waveform generator 110 according to instructions issued by the host computer, and stores the original waveform in a storage device 140 via the read / write control module 120. The read / write control module 120 and the storage device 140 can be connected via an Avalon interface.

[0054] Specifically, the arbitrary waveform generator 110, read / write control module 120, and service decoding module 160 can be housed within an FPGA (Field-Programmable Gate Array), while the external clock chip 130, storage device 140, and digital-to-analog converter 150 are located outside the FPGA. The service decoding module 160's port PLL_CTRL is connected to the external clock chip 130 via an SPI (Serial Peripheral Interface) interface. Parameters are configured for the external clock chip 130 to output a fixed-frequency sampling clock to the digital-to-analog converter 150. This configuration can be either setting the external clock chip 130 to output the sampling clock at the maximum allowed frequency (e.g., 400MHz) or at other frequencies. The service decoding module 160's port DDR_RQE is connected to the read / write control module 120, which controls the waveform read / write operation of the storage device 140. The AWG_CTRL port of the service decoding module 160 is connected to the arbitrary waveform generator 110, and sends control signal parameters to control the waveform resampling of the arbitrary waveform generator 110.

[0055] After the signal generator is powered on, the service decoding module 160 automatically configures the external clock chip 130 to output a sampling clock with a fixed frequency via the SPI interface. The host computer then writes the original waveform into the storage device 140 through the service decoding module 160 and the read / write control module 120. The host computer also sends control signal parameters to the arbitrary waveform generator 110 through the service decoding module 160. The arbitrary waveform generator 110 sends a read request command to the read / write control module 120 based on the received control signal parameters, and resamples the original waveform returned by the read / write control module 120 to generate a reconstructed waveform with a frequency matching the sampling clock.

[0056] Referring again to Figure 2, the IQ DAC chips are identical, and their sampling clock is set to a fixed maximum sampling clock (400MHz). Since the sampling rate of the original waveform in storage device 140 is arbitrarily set by the user, but the DAC chip operates at a fixed maximum sampling clock, the original waveform is resampled using arbitrary waveform generator 110. While ensuring the waveform information (amplitude, frequency) remains unchanged, the original waveform with the arbitrary sampling rate stored in storage device 140 is resampled to the fixed maximum sampling clock. The sampling rate of the resulting reconstructed waveform is the same as the sampling clock frequency of the DAC chip. Simultaneously, during the resampling process, the initial phase of the reconstructed waveform generated by resampling can be changed by setting the initial phase. The generated reconstructed waveform is output to the DAC chip, realizing the arbitrary sampling rate and arbitrary phase adjustable function of the IQ channel. Using two ordinary DAC chips, the IQ function can be implemented, and the functions of two non-IQ channels can also be implemented, without the need for external clock chip 130 to adjust the sampling clock frequency, simplifying operation and improving testing efficiency.

[0057] In one embodiment, the arbitrary waveform generator 110 includes a waveform request module 112 and a waveform data processing module 114. The waveform request module 112 is connected to the read / write control module 120 and the waveform data processing module 114, and is used to send a read request command to the read / write control module 120 and send the original waveform returned by the read / write control module 120 to the waveform data processing module 114. The waveform data processing module 114 is used to resample the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock.

[0058] The waveform request module 112 includes a waveform request unit 1122, a RAM (Random Access Memory) storage unit 1124, and a data selection unit 1126. The waveform request unit 1122 is connected to the read / write control module 120, the RAM storage unit 1124, and the data selection unit 1126. The data selection unit 1126 is connected to the RAM storage unit 1124 and the waveform data processing module 114. Furthermore, the waveform request unit 1122 and the data selection unit 1126 are also connected to the service decoding module 160.

[0059] The waveform request unit 1122 sends a read request command to the read / write control module 120 based on the control signal parameters (including PRE_START and AWG_CTRL_SIGNAL commands) issued by the service decoding module 160, requesting to read the corresponding raw waveform. The AWG_CTRL_SIGNAL command may include information such as waveform length, the starting address of the raw waveform in the storage device 140, and the number of times the waveform is repeatedly transmitted. When the PRE_START command is 1, only the raw waveform of channel I is requested from the read / write control module 120; when the PRE_START command is 2, only the raw waveform of channel Q is requested; and when the PRE_START command is 3, both channels I and Q are requested from the read / write control module 120. After the read / write control module 120 responds to the read request command, it outputs the raw waveforms of both channels I and Q to the waveform request unit 1122 according to the requested channel data information. After receiving the original waveform, the waveform request unit 1122 determines whether it needs to be written to the RAM storage unit 1124 based on the waveform length. If the waveform length is less than a preset threshold length (e.g., 1024), it is written to the RAM storage unit 1124; otherwise, the waveform request unit 1122 directly outputs the original waveform to the data selection unit 1126. The data selection unit 1126 determines the source of the original waveform based on the waveform length parameter (e.g., the AWG_Digital_CTRL_SIGNAL instruction) issued by the service decoding module 160. If the waveform length is less than the preset threshold length, the RAM storage unit 1124 outputs the original waveform; otherwise, the waveform request unit 1122 directly outputs the original waveform. The data selection unit 1126 then sends the original waveform to the waveform data processing module 114 for resampling processing.

[0060] Since the length of the original waveform may be very small, the DDR bandwidth utilization is very low when the original waveform length is small, which is insufficient to support continuous waveform output. In this case, the original waveform needs to be stored in the RAM storage unit 1124, and the output of the original waveform is controlled from the RAM storage unit 1124 to reduce the impact of the large DDR bandwidth sacrifice when sending small data. The RAM storage unit 1124 can support waveform repeated reading operations, continuous waveform output, and stop reading operations. When the waveform length is relatively small, the original waveform is stored in the RAM storage unit 1124, and the continuous output of the waveform is achieved using the RAM storage unit 1124.

[0061] In one embodiment, as shown in Figure 2, the arbitrary waveform generator 110 further includes a synchronization control module 116. The synchronization control module 116 is connected to the waveform data processing module 114 and is used to buffer the reconstructed waveform in an internal buffer module. Upon receiving a trigger signal, it outputs the reconstructed waveform from the internal buffer module. Specifically, the synchronization control module 116 is also connected to the service decoding module 160. The synchronization control module 116 buffers the received reconstructed waveform in an internal FIFO (First Input First Output) buffer. Upon receiving a trigger signal TRIG from the service decoding module 160, it outputs the reconstructed waveform from the FIFO buffer to the digital-to-analog converter 150. Similarly, taking a test machine including an IQ channel as an example, synchronization control can be performed through the synchronization control module 116 in the IQ channel, allowing the reconstructed waveforms of both channels to be synchronously sent to the IQ DAC chips.

[0062] It is understood that the specific structure of the waveform data processing module 114 is not unique. The waveform data processing module 114 may include a calibration module and a digital resampling module. The calibration module is connected to the waveform request module 112 and is used to calibrate the received raw waveform and output the calibrated waveform data. The digital resampling module is connected to the calibration module and is used to resample the calibrated waveform data to generate a reconstructed waveform that matches the frequency of the sampling clock.

[0063] As shown in Figure 3, the calibration module may specifically include at least one of a DC calibration module 41 and an AC amplitude calibration module 42. Taking a calibration module that includes both a DC calibration module 41 and an AC amplitude calibration module 42 as an example, both the DC calibration module 41 and the AC amplitude calibration module 42 are connected to the service decoding module 160. The DC calibration module 41 is connected to the data selection unit 1126 in the waveform request module 112, and the AC amplitude calibration module 42 is connected to the DC calibration module 41 and the digital resampling module. The DC calibration module 41 performs DC calibration on the received raw waveform according to the DC calibration coefficients issued by the service decoding module 160 and then sends it to the AC amplitude calibration module 42 to ensure that the amplitude accuracy of the channel data meets the requirements. Since the IQ channel has high requirements for AC flatness, the AC amplitude calibration module 42 is also used to perform AC amplitude calibration on the DC-calibrated waveform according to the AC calibration coefficients issued by the service decoding module 160 to ensure that the amplitude accuracy of the channel data meets the requirements. The AC amplitude calibration module 42 then sends the AC amplitude-calibrated waveform to the digital resampling module.

[0064] The storage device 140 stores the original waveform with a frequency set by the host computer (the frequency is variable, for example, 100MHz, which is the original waveform with any frequency set by the user), while the external clock chip 130 is set to a fixed maximum sampling clock frequency. The function of the digital resampling module is to resample the original waveform into a reconstructed waveform at a fixed maximum sampling clock frequency (400MHz) (both waveform data and sampling frequency are converted; based on the maximum sampling clock frequency, the original waveform is converted into a reconstructed waveform corresponding to the maximum sampling clock frequency).

[0065] The principle of resampling is to use the SINC function to recover the waveform of a continuous signal. Since the arbitrary waveform generator 110 resamples the original waveform of any frequency to a fixed maximum sampling frequency, its function can be summarized as an interpolation of an arbitrary decimal multiple. For a known continuous waveform x(n), to recover x(t) at any time, the Sinc function is used for data resampling recovery. The actual value of the recovered point is obtained by convolving the first 8 points and the last 8 points of the position of the effective point to be recovered with 16 Sinc continuous coefficients.

[0066] To recover the ideal SINC function, theoretically, an infinite number of coefficients need to be calculated, which is obviously impossible. Therefore, the SINC function model is divided into 1024 groups of coefficients, with 16 coefficients in each group, and stored in ROM. The effective coefficients are then read from ROM based on the effective position information. Since an infinite number of groups of coefficients cannot be stored, for higher accuracy, the stored coefficients are not used directly when calculating the effective coefficients. Instead, each segment of coefficients is considered to be continuous, and the effective coefficients at any point can be obtained by using a linear weighting algorithm.

[0067] Based on this, referring to Figure 3, the digital resampling module may include an input waveform data buffer module 43, an effective position calculation module 44, an effective coefficient generation module 45, an effective data buffer module 46, and a data calculation module 47. The input waveform data buffer module 43 is connected to the calibration module, the effective position calculation module 44, and the effective data buffer module 46. The effective position calculation module 44 is connected to the effective coefficient generation module 45. The effective coefficient generation module 45 is connected to the data calculation module 47 and the effective data buffer module 46. The effective data buffer module 46 is connected to the data calculation module 47.

[0068] The input waveform data caching module 43 is specifically connected to the AC amplitude calibration module 42 in the calibration module. It caches the calibrated waveform data and sends a start signal SINC_START to the valid position calculation module 44 when the number of cached data exceeds a set threshold. It also reads the valid data corresponding to the valid position from the cached data based on the received read enable signal and sends the read valid data to the valid data caching module 46 for caching. The valid position calculation module 44, upon receiving the start signal SINC_START, calculates the valid position information based on the set step and initial phase, sends it to the valid coefficient generation module 45, and sends a read enable signal to the input waveform data caching module 43. The valid coefficient generation module 45 reads coefficients from multiple pre-stored sets of coefficients based on the valid position information, obtains valid coefficients, sends them to the data calculation module 47, and sends a data read enable signal to the valid data caching module 46. The valid data caching module 46 reads the cached valid data based on the received data read enable signal and sends it to the data calculation module 47. The data calculation module 47 performs convolution calculations based on the received valid coefficients and valid data to obtain the reconstructed waveform. The convolution formula is as follows:

[0069] Wherein, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the effective coefficients corresponding to the effective positions of the reconstruction points (a total of 16 effective coefficients), and DATA_IN represents the effective data corresponding to this effective position (also 16 points, the first 8 points and the last 8 points of this effective position). After multiplying and accumulating the effective coefficients and the original waveform 16 times, the reconstruction point of the corresponding reconstructed waveform is calculated.

[0070] The value of the threshold number is not unique and can be set according to actual needs. The service decoding module 160 is connected to the effective position calculation module 44 to configure the step and initial phase. By controlling the step and initial phase, the digital resampling module can resample the initial waveform with a variable sampling frequency into a reconstructed waveform with a fixed maximum sampling frequency. At the same time, because the digital resampling module performs digital resampling, it can also achieve phase adjustment of the output waveform with an accuracy of up to 1ps.

[0071] Specifically, after receiving the calibrated waveform data output by the AC amplitude calibration module 42, the input waveform data buffer module 43 can buffer it in an internal buffer unit (such as a FIFO). When the number of buffered data exceeds a set threshold (such as 16), the input waveform data buffer module 43 sends a start signal SINC_START to the valid position calculation module 44. Upon receiving the start signal SINC_START, the valid position calculation module 44 begins operation, calculating the valid position based on the STEP and initial phase PHASE information sent by the service decoding module 160. The valid position can be understood as the position of the reconstructed waveform points. The calculated valid position information consists of a 16-bit integer and a 48-bit decimal. The initial position of the reconstructed waveform is determined by the initial phase PHASE, which refers to the valid position of the first point of the reconstructed waveform. The relationship between the reconstructed waveform point position and the original waveform point position is: Reconstructed waveform point position = (Original waveform point position - 1) * STEP + 1 + PHASE. The original waveform point position is also the position of the calibrated waveform data points; DC calibration and AC amplitude calibration do not change the position of the original waveform points.

[0072] The step STEP is calculated as: User-set sampling rate (original waveform sampling rate) / Fixed maximum sampling rate (sampling clock frequency). Since the user-set sampling rate is less than or equal to the fixed maximum sampling rate, the value of STEP is less than or equal to 1, which can be understood as an interpolation operation at any multiple. The step STEP consists of a 16-bit integer and a 48-bit decimal. Because the fixed maximum sampling rate is set to 400MHz, the 48-bit decimal supports up to 1 Hz, enabling resampling at sampling rates up to 1 Hz. Since the arbitrary waveform generator 110 outputs a fixed 400MHz sampling rate, 1 Hz adjustment can be achieved to achieve the desired sampling rate resolution. Assuming A = 400MHz = 400 * 2^10 * 2^10 Hz and B = 1µHz = (1 / 2^10 * 2^10) Hz, then A / B = 400 * 2^10 * 2^10 Hz / (1 / 2^10 * 2^10) Hz = 400 * 2^40 = 49 bits. Since the SINC algorithm divides the coefficients into 1024 parts, the minimum position information requires 400 * 2^40 / 1024 bits = 39 bits. This scheme uses 48 bits. The initial phase PHASE = number of points in one waveform cycle / (360° / phase of the reconstructed waveform). The output result is composed of a 16-bit integer and a 48-bit decimal, allowing for ps-level phase adjustment.

[0073] After obtaining the valid position information based on the set step and initial phase, the valid position calculation module 44 outputs the valid position information to the valid coefficient generation module 45. Simultaneously, it sends a read enable signal to the input waveform data buffer module 43 based on the determined valid position. The input waveform data buffer module 43 reads a data value based on the read enable signal sent by the valid position calculation module 44 and sends it to the valid data buffer module 46. At this time, the data stored in the valid data buffer module 46 is the valid data for that valid position. After the valid coefficient generation module 45 calculates the valid coefficient for that valid position, the valid data buffer module 46 reads the valid data and sends it to the data calculation module 47 for calculation.

[0074] The effective coefficient generation module 45 can store multiple sets (e.g., 1024 sets) of coefficients (16 coefficients per set) in the internal ROM (read-only memory) unit in advance. After receiving the effective position information, the effective coefficient generation module 45 can read out two adjacent sets of coefficients according to the integer position information of the effective position information, and calculate the effective coefficients by using a linear interpolation algorithm on the two sets of coefficients read according to the decimal position information of the effective position information.

[0075] Specifically, the effective coefficient generation module 45 reads the pre-stored coefficients from the ROM unit based on the effective position information. Since there are only 1024 pre-stored coefficients, which cannot meet the precision of 48-bit decimals, it reads two adjacent sets of coefficients (16 coefficients per set) based on the integer position information of the effective position information. Then, it calculates the two sets of coefficients based on the decimal position information of the effective position information using a linear interpolation algorithm: y_coe[n] = COE1[n] * tim_valid + COE2[n] * (1 - tim_valid), where n is between 0 and 15, to obtain the most accurate effective coefficients (16 coefficients). Here, COE1 represents the first set of coefficients in the two adjacent sets of coefficients read, COE2 represents the second set of coefficients in the two adjacent sets of coefficients read (both the first and second sets of coefficients have 16 coefficients), tim_valid represents the decimal position information in the effective position information, and y_coe represents the effective coefficients (16 coefficients) in the decimal position of the actual effective position information obtained by linear interpolation.

[0076] The valid data caching module 46 can store valid data in parallel into consecutive internal cache units (such as FIFOs) using a shifting method. Specifically, the valid data caching module 46 stores valid data in parallel into 16 FIFOs using a shifting method. The parallel storage is manifested in that the latest input data is stored in FIFO1, while the data in the original FIFO1 is stored in FIFO2, the data in the original FIFO2 is stored in FIFO3, and so on, that is, the 16 FIFOs store 16 consecutive data.

[0077] After the effective coefficient generation module 45 generates an effective coefficient, it outputs the effective coefficient to the data calculation module 47 and simultaneously sends a data read enable signal to the effective data buffer module 46. Based on the data read enable signal, the effective data buffer module 46 reads 16 effective data points from the 16 FIFOs and outputs them to the data calculation module 47. The data calculation module 47 performs a 16th-order convolution calculation based on the effective coefficient output by the effective coefficient generation module 45 and the effective data output by the effective data buffer module 46, calculating the resampled reconstructed waveform and outputting it to the subsequent synchronization control module 116.

[0078] The following example illustrates this. Assumptions: 1. The user sets the sampling rate (frequency of the original waveform) to 202MHz; 2. The phase of the reconstructed waveform is set to 3.6°; 3. The waveform file contains 100 points, representing 2 cycles. In this case: Step = User-set sampling rate / Fixed maximum sampling rate = 202 / 400 = 0.505; Initial phase PHASE = Number of points in one waveform cycle / (360° / Phase of the reconstructed waveform) = (100 / 2) / (360° / 3.6°) = 0.5. As shown in Figure 4, the effective position of the first point in the reconstructed waveform is determined by the initial phase PHASE, and the number of points in the reconstructed waveform corresponds to the effective position in the original waveform. The relationship between the reconstructed waveform point position and the original waveform point position is as follows: Reconstructed waveform point position = (Original waveform point position - 1) * STEP + 1 + PHASE = (Original waveform point position - 1) * 0.505 + 1 + 0.5, such as: 1----1.500, 2----2.005, 3----2.510, 4-----3.015. Figure 4 illustrates the effect of user-set frequency, waveform point number, and initial phase on resampling, and their relationship with the effective position.

[0079] In one embodiment, the signal generating device further includes a delay module. The arbitrary waveform generator 110 is connected to the corresponding digital-to-analog converter 150 via the delay module. Each arbitrary waveform generator 110 is also used to synchronously send valid data to the corresponding digital-to-analog converter 150 according to the accompanying clock sent by the digital-to-analog converter 150. As shown in Figure 2, the delay module may specifically include an IDELAY unit and an ODELAY unit. Since different traces will result in different delays, the IDELAY unit and ODELAY unit are used to adjust the delay of the reconstructed waveform transmission so that the DAC chip meets the setup and hold time requirements. The synchronization control module 116 in the arbitrary waveform generator 110 is connected to the corresponding digital-to-analog converter 150 via the delay module. The synchronization control module 116 and the delay module can be connected via an LVDS (Low-Voltage Differential Signaling) interface. The digital-to-analog converter 150 outputs the accompanying clock data_clk to the synchronization control module 116, and the synchronization control module 116 outputs the reconstructed waveform according to the accompanying clock data_clk.

[0080] Taking the test unit with dual IQ channels as an example, both DAC chips send their associated clock data_clk. Since the sampling clocks input to the two DAC chips are from the same source and have the same frequency, only one sampling clock can be used as the shared sampling clock for both DAC chips. The DAC chip outputs the associated clock data_clk to the synchronization control module 116, and the synchronization control module 116 outputs the reconstructed waveform to the DAC chip based on the associated clock data_clk.

[0081] To ensure data synchronization, upon receiving the trigger signal TRIG, the synchronization control module 116 first converts the TRIG across clock domains to the clock domain of the associated clock data_clk of the I-channel DAC chip. Then, based on the operating mode issued by the service decoding module 160, it determines whether the operating mode is IQ mode. If it is IQ mode, it determines that as long as the trigger signal TRIG of one channel is high, the synchronization control modules 116 of both channels simultaneously read data from the FIFO and output data using the associated clock data_clk of the I-channel DAC chip as the clock, thus achieving synchronous output of data from both I and Q channels. When the operating mode is not IQ mode, the synchronization control modules 116 of the two I and Q channels control the data output of both channels according to their respective received TRIG signals.

[0082] Referring to Figures 2 and 3, the complete processing procedure of the original waveform is described below: After the signal generator is powered on, the host computer communicates with the service decoding module 160, writes the original waveform into the storage device 140 through the service decoding module 160, configures the external clock chip 130 to output a sampling clock with a fixed frequency, and sends control signal parameters to the arbitrary waveform generator 110 for parameter configuration. Specifically, this includes configuring the control signal parameters of the waveform request unit 1122, the waveform length parameters of the data selection unit 1126, the DC calibration parameters of the DC calibration module 41, the AC calibration parameters of the AC amplitude calibration module 42, the step and initial phase of the effective position calculation module 44, etc.

[0083] The waveform request unit 1122 sends a read request command to the read / write control module 120 to request the reading of the original waveform based on the configured control signal parameters. Upon receiving the original waveform, the waveform request unit 1122 determines whether it needs to be written to the RAM storage unit 1124 based on the waveform length. If the waveform length is less than a preset threshold length, it is written to the RAM storage unit 1124; otherwise, the waveform request unit 1122 directly outputs the original waveform to the data selection unit 1126. The data selection unit 1126 determines the source of the original waveform based on the waveform length parameter issued by the service decoding module 160, and retrieves the original waveform from the RAM storage unit 1124 or the waveform request unit 1122, sending it to the waveform data processing module 114 for resampling processing.

[0084] In the waveform data processing module 114, the DC calibration module 41 and the AC amplitude calibration module 42 perform DC calibration and AC amplitude calibration on the original waveform sequentially according to the configured DC calibration coefficients and AC calibration coefficients, and then send the data to the input waveform data buffer module 43 for buffering. When the number of buffered data exceeds a set threshold, the input waveform data buffer module 43 sends a start signal SINC_START to the valid position calculation module 44. Upon receiving the start signal SINC_START, the valid position calculation module 44 calculates the valid position information according to the configured step and initial phase and sends it to the valid coefficient generation module 45, and also sends a read enable signal to the input waveform data buffer module 43. The input waveform data buffer module 43 reads the valid data corresponding to the valid position from the buffered data according to the received read enable signal, and sends the read valid data to the valid data buffer module 46 for buffering. The valid coefficient generation module 45 reads coefficients from multiple pre-stored sets of coefficients according to the valid position information, obtains the valid coefficients, sends them to the data calculation module 47, and sends a data read enable signal to the valid data buffer module 46. The effective data caching module 46 reads the cached effective data according to the received data read enable signal and sends it to the data calculation module 47. The data calculation module 47 performs convolution calculation based on the received effective coefficients and effective data to obtain the reconstructed waveform.

[0085] The reconstructed waveform calculated by the data calculation module 47 is sent to the synchronization control module 116 for buffering. Upon receiving the trigger signal TRIG from the service decoding module 160, the synchronization control module 116 uses the DAC chip's accompanying clock data_clk as its clock and sends the buffered reconstructed waveform to the DAC chip via a delay module. The DAC chip, based on the sampling clock output by the external clock chip 130, performs digital-to-analog conversion on the received reconstructed waveform, obtaining an analog waveform signal which is then output to the device under test (DUT) for testing.

[0086] In one embodiment, as shown in FIG5, a signal generation method is also provided, including:

[0087] Step S110: The external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog converter.

[0088] Step S120: The read / write control module reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator.

[0089] Step S130: The arbitrary waveform generator resamples the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock; wherein, the reconstructed waveform is used by the digital-to-analog converter to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

[0090] It is understood that the specific implementation of the above signal generation method has been explained in detail in the above signal generation device, and will not be repeated here.

[0091] In one embodiment, a mixed-signal test board is also provided, including the signal generating device described above.

[0092] In one embodiment, a test machine is also provided, including a communication board, a backplane, and the aforementioned mixed-signal test board. The communication board is connected to the mixed-signal test board via the backplane. Furthermore, the test machine also includes a host computer that communicates with the communication board. The host computer can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc.

[0093] The above-mentioned signal generation device, method, analog-to-digital mixed test board, and test machine have the following advantages:

[0094] 1. This application uses a DAC chip to fix the sampling clock frequency. After power-on initialization, there is no need to repeatedly configure the external clock chip, which reduces the clock chip lock-up time caused by changing the sampling clock and improves test efficiency.

[0095] 2. This application uses a DAC chip to fix the sampling clock frequency and performs resampling operations through a digital domain algorithm to achieve arbitrary sampling rate design. It can achieve sampling rate resolution adjustment in μHz, which is a requirement that is difficult to achieve by existing methods of adjusting the sampling rate through a clock chip.

[0096] 3. This application can implement both IQ and non-IQ functions, making it more flexible and convenient to use and improving the efficiency of equipment use.

[0097] 4. The control method of this application facilitates the expansion, reuse, and portability of program channels. It can be directly used in other projects. For program updates, it is only necessary to add or remove channels, which facilitates program code maintenance.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A signal generating device, characterized by include: Arbitrary waveform generator, read / write control module, external clock chip and storage device; The external clock chip is used to output a fixed-frequency sampling clock to the digital-to-analog converter. The read / write control module connects the arbitrary waveform generator and the storage device, and is used to read the original waveform from the storage device according to the received read request instruction, and return the read original waveform to the arbitrary waveform generator; The arbitrary waveform generator is used to resample the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock; wherein, the reconstructed waveform is used by the digital-to-analog converter to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

2. The signal generating device of claim 1, wherein, The arbitrary waveform generator includes: A waveform request module, connected to the read / write control module and the waveform data processing module, is used to send read request commands to the read / write control module and to send the raw waveform returned by the read / write control module to the waveform data processing module. The waveform data processing module is used to resample the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock.

3. The signal generating device of claim 2, wherein, The arbitrary waveform generator also includes: The synchronization control module is connected to the waveform data processing module and is used to cache the reconstructed waveform in an internal cache module, and output the reconstructed waveform in the internal cache module after receiving a trigger signal.

4. The signal generating device of claim 2, wherein, The waveform data processing module includes: The calibration module, connected to the waveform request module, is used to calibrate the received raw waveform and output the calibrated waveform data. A digital resampling module, connected to the calibration module, is used to resample the calibrated waveform data to generate a reconstructed waveform that matches the frequency of the sampling clock.

5. The signal generating device of claim 4, wherein, The calibration module includes at least one of a DC calibration module and an AC amplitude calibration module.

6. The signal generating device of claim 4, wherein, The digital resampling module includes: An input waveform data caching module is connected to the calibration module, the effective position calculation module, and the effective data caching module. It is used to cache the calibrated waveform data and send a start signal to the effective position calculation module when the number of cached data exceeds a set threshold. It also reads the effective data corresponding to the effective position from the cached data according to the received read enable signal and sends the read effective data to the effective data caching module for caching. The effective position calculation module is connected to the effective coefficient generation module. After receiving the start signal, it calculates the effective position information according to the set step and initial phase, sends it to the effective coefficient generation module, and sends a read enable signal to the input waveform data buffer module. The effective coefficient generation module is connected to the data calculation module and the effective data cache module. It is used to read coefficients from multiple pre-stored coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module. The effective data caching module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal. The data calculation module is used to perform convolution calculations based on the received effective coefficients and effective data to obtain the reconstructed waveform.

7. The signal generating device of claim 6, wherein, The effective data caching module stores the effective data in parallel into consecutive internal cache units using a shifting method; And / or the effective coefficient generation module reads two adjacent sets of coefficients based on the integer position information of the effective position information, and calculates the effective coefficients by using a linear interpolation algorithm on the two sets of coefficients read based on the decimal position information of the effective position information.

8. The signal generating device of claim 6, wherein, The data calculation module performs convolution calculation according to the received effective coefficient and effective data, including: Wherein, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

9. The signal generating device of any of claims 1-8, wherein, Also includes: The delay module connects the arbitrary waveform generator to the corresponding digital-to-analog converter. Each arbitrary waveform generator is also used to synchronously send valid data to the corresponding digital-to-analog converter according to the on-path clock sent by the digital-to-analog converter.

10. The signal generating device of any of claims 1-8, wherein, Also includes: The service decoding module connects to the host computer, the external clock chip, the read / write control module, and the arbitrary waveform generator. It configures the parameters of the external clock chip and the arbitrary waveform generator according to the instructions issued by the host computer, and stores the original waveform to the storage device through the read / write control module.

11. A signal generating method characterized by comprising: include: An external clock chip outputs a fixed-frequency sampling clock to the digital-to-analog converter; The read / write control module reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator; The arbitrary waveform generator resamples the received original waveform to generate a reconstructed waveform with a frequency matching the sampling clock; wherein, the reconstructed waveform is used by the digital-to-analog converter to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

12. An analog-digital hybrid test board card, characterized by Includes the signal generating device according to any one of claims 1-10.

13. A testing machine characterized by, It includes a communication board, a backplane, and the mixed analog-to-digital test board as described in claim 12.

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