Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel. The array substrate comprises a gate metal wire, an SD metal wire and a driving IC. Forming a film on the SD metal line above the gate metal line; the SD metal wire and the gate metal wire penetrate through the fan-shaped region of the display panel and are electrically connected with the driving IC; the SD metal wire and the gate metal wire respectively comprise a first SD wiring part and a first gate wiring part; the first SD wiring part and the first grid wiring part are arranged in a non-frame glue area of the fan-shaped area; and the first SD wiring part and the first gate wiring part are arranged in a vertically staggered manner up and down. The grid metal wires and the SD metal wires are arranged in the non-frame glue area of the fan-shaped area in a staggered mode, RC loading of wiring in the fan-shaped area is reduced, the grid metal wires and the SD metal wires are arranged in an up-down overlapped mode in the frame glue area, and the problem that the frame glue effect is reduced due to the fact that the grid metal wires and the SD metal wires are arranged in a staggered mode is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of display panels, and particularly relates to an array substrate and a display panel. Background Art

[0002] Narrow bezel liquid crystal display panels are favored by users due to their high screen-to-body ratio, and have also become the focus of research and development by display panel manufacturers. In the display area of narrow bezel liquid crystal display panels, there are generally many signal lines, such as data lines, touch signal lines, gate lines, etc. These signal lines generally need to be connected to an integrated circuit (IC) through a fanout area. The display area, the driving IC, and the fanout area located between the display area and the IC. The signal lines in the display area are electrically connected to the IC through the connecting lines in the fanout area, and the connecting lines in the fanout area are distributed in a fan shape.

[0003] However, due to the relatively dense wiring in the Fanout area of the display screen, there are two layers of metal wiring, resulting in a relatively large RC Loading in the Fanout area, and the light transmittance is relatively low when the frame glue is cured, resulting in a relatively low frame glue curing effect on the display screen, thereby reducing the display quality.

[0004] Therefore, there is an urgent need for a solution that can reduce the RC Loading in the Fanout area while increasing the frame glue curing effect, so as to improve the display effect and thus enhance the product competitiveness. Summary of the Utility Model

[0005] The existing wiring in the Fanout area of liquid crystal display panels has problems of relatively large RC Loading and poor frame glue curing effect.

[0006] In view of the above problems, an array substrate and a display panel are proposed. By staggering the gate metal traces and the SD metal traces in the non-frame glue area of the fanout area, the RC Loading of the wiring in the fanout area is reduced, and the gate metal traces and the SD metal traces are also overlapped vertically in the frame glue area, solving the problem of the decrease in the frame glue curing effect caused by all staggered traces.

[0007] In a first aspect, an array substrate includes:

[0008] Gate metal lines;

[0009] SD metal lines;

[0010] A driving IC;

[0011] The SD metal lines are formed above the gate metal lines;

[0012] The SD metal line and the gate metal line pass through the sector area of the display panel and are electrically connected to the driving IC;

[0013] The SD metal line and the gate metal line respectively include a first SD routing portion and a first gate routing portion;

[0014] The first SD wiring portion and the first gate wiring portion are wired in the non-frame glue area of the fan-shaped area;

[0015] The first SD wiring portion and the first gate wiring portion are vertically staggered in wiring.

[0016] In combination with the array substrate of the present invention, in a first possible implementation manner, the SD metal line and the gate metal line further include:

[0017] A second SD wiring portion and a second gate wiring portion;

[0018] The second SD wiring portion and the second gate wiring portion are wired in the frame glue area of the fan-shaped area;

[0019] The second SD wiring portion and the second gate wiring portion are vertically overlapped and wired.

[0020] In combination with the first possible implementation manner of the utility model, in a second possible implementation manner, the first SD routing portion is an upper fan-shaped segment SD routing, and the second SD routing portion is a straight segment SD routing;

[0021] The first SD wiring portion is formed on an upper end of the second SD wiring portion.

[0022] In combination with the first possible implementation manner of the utility model, in a third possible implementation manner, the first SD routing portion is a lower fan-shaped segment SD routing, and the second SD routing portion is a straight segment SD routing;

[0023] The first SD wiring portion is formed at a lower end of the second SD wiring portion.

[0024] In combination with the first possible implementation manner of the utility model, in a fourth possible implementation manner, the first gate wiring portion is an upper fan-shaped segment gate wiring, and the second gate wiring portion is a straight segment gate wiring;

[0025] The first gate wiring portion is formed on an upper end of the second gate wiring portion.

[0026] In combination with the first possible implementation manner of the utility model, in a fifth possible implementation manner, the first gate wiring portion is a lower fan-shaped segment gate wiring, and the second gate wiring portion is a straight segment gate wiring;

[0027] The first gate trace portion is formed on the lower end of the second gate trace portion.

[0028] In a second aspect, a display panel includes the array substrate described in the first aspect.

[0029] By implementing the array substrate and the display panel of the present utility model, by staggering the gate metal traces and the SD metal traces in the non-frame-bonding area of the fan-shaped area, the RC Loading of the wiring in the fan-shaped area is reduced, and the gate metal traces and the SD metal traces are also overlapped vertically and horizontally in the frame-bonding area, solving the problem of the decline in the frame-bonding effect caused by all staggered traces. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 Schematic diagram of a display panel in the prior art;

[0032] Figure 2 Schematic diagram of the wiring in the fan-shaped area of the array substrate in the present utility model;

[0033] Figure 3 Schematic diagram of the film layer structure in the non-frame-bonding area of the array substrate in the present utility model;

[0034] Figure 4 Schematic diagram of the film layer structure in the frame-bonding area of the array substrate in the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] The following will clearly and completely describe the technical solutions in the present utility model with reference to the drawings in the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, rather than all embodiments. Based on the embodiments in the present utility model, other embodiments obtained by those of ordinary skill in the art without creative efforts all belong to the scope of protection of the present utility model.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the description of the present utility model in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0037] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0038] It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0039] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0040] There are problems with the wiring in the Fanout area of the existing liquid crystal display panel, such as a relatively large RC Loading and poor curing effect of the frame glue.

[0041] In view of the above problems, an array substrate and a display panel are proposed.

[0042] In a first aspect, an array substrate includes gate metal lines, SD metal lines, and a driving IC; the SD metal lines are formed above the gate metal lines; the SD metal lines and the gate metal lines pass through the fan-shaped area (Fan out) 120 of the display panel and are electrically connected to the driving IC; the SD metal lines and the gate metal lines respectively include a first SD trace portion 310 and a first gate trace portion 210; the first SD trace portion 310 and the first gate trace portion 210 are routed in the non-frame glue area 121 of the fan-shaped area (Fan out) 120; the first SD trace portion 310 and the first gate trace portion 210 are vertically staggered from each other in the up and down direction. By staggering the routing of the gate metal traces and the SD metal traces in the non-frame glue area 121 of the fan-shaped area (Fan out) 120, the RC Loading of the routing in the fan-shaped area (Fan out) 120 is reduced.

[0043] Such as Figure 1 , Figure 1Schematic diagram of a display panel in the prior art; Generally, a display panel usually includes an AA display area 110 and a fan-out area 120. When wiring the array substrate, data line wiring, gate line wiring, driving circuit wiring, and via connection wiring are carried out.

[0044] Data signal transmission lines are used to transmit image data signals from a driving chip. These data lines are usually connected to the same data signal terminal, and there may be multiple lines in a group of data lines to transmit different data signals to each sub-pixel. For example, in some display panels, a group of data lines may include 6 or more data lines. As the columns of the array circuit, they transmit data signals from the data signal terminal to the corresponding sub-pixel area.

[0045] Gate lines, as the rows of the array circuit, are mainly used to transmit scan signals to control the switching of sub-pixels. Multiple gate lines and data lines are arranged in a cross pattern on different layers, defining multiple sub-pixel areas arranged in multiple rows and columns. Each sub-pixel in a sub-pixel area is connected to the data line and gate line of the corresponding row and column.

[0046] Driving circuit wiring. The pixel driving circuit contains multiple thin-film transistors, which are used to control the light emission of sub-pixels. The source, drain, and gate of the thin-film transistor need to be connected to the corresponding lines. For example, the source or drain may be connected to the data line to receive data signals, and the gate may be connected to the gate line or other control signal lines to receive scan signals or other control signals.

[0047] Via connection wiring: In some array substrates, vias are provided to achieve circuit connection between different layers. For example, when the gate driving circuit (GOA circuit) and the pixel driving circuit are respectively arranged on opposite sides of the substrate, vias are needed to connect the GOA circuit and the pixel driving circuit.

[0048] For the wiring of the fan-out area 120 of the display panel, since the wiring in the fan-out area 120 of the display panel is relatively dense and there are two layers of metal wiring, that is, there is also an SD metal line above the gate metal line, which will increase the wiring load. If the SD metal line above the gate metal line is staggered in wiring, the light transmittance of the frame adhesive curing light is relatively low, affecting the frame adhesive curing effect.

[0049] In this embodiment, as Figure 2 , Figure 2 is the wiring schematic diagram of the fan-out area 120 of the array substrate in the present invention. The fan-out area 120 includes a frame adhesive area 122 and a non-frame adhesive area 121. In the non-frame adhesive area 121, the SD metal trace and the gate metal trace are vertically staggered up and down in wiring. As Figure 3 ,Figure 3 Schematic diagram of the film layer structure of the non-frame glue area 121 of the array substrate in the present utility model.

[0050] Specifically, in an application scenario of this embodiment, the SD metal line is stagger-wired in the first SD wiring portion 310 of the non-frame glue area 121, and the gate metal line is stagger-wired in the first gate wiring portion 210 of the non-frame glue area 121.

[0051] In a preferred embodiment, the SD metal line and the gate metal line further respectively include: a second SD wiring portion 320 and a second gate wiring portion 220; the second SD wiring portion 320 and the second gate wiring portion 220 are wired in the frame glue area 122 of the fan-out area 120; the second SD wiring portion 320 and the second gate wiring portion 220 are vertically overlapped and wired up and down.

[0052] Specifically, in an application scenario of this embodiment, the second SD wiring portion 320 of the SD metal line in the frame glue area 122 and the second gate wiring portion 220 of the gate metal line in the frame glue area 122 are vertically overlapped and wired up and down. As Figure 4 , Figure 4 Schematic diagram of the film layer structure of the frame glue area 122 of the array substrate in the present utility model. Vertically overlapping the gate metal wiring and the SD metal wiring in the frame glue area 122 solves the problem of the decline in the frame gluing effect caused by all stagger-wiring.

[0053] In the array substrate, it generally includes various film layers such as substrate glass, buffer layer, isolation layer (ILD), insulating layer (SiNx), gate layer, Island layer, planarization layer (PLN), SD layer, transparent common electrode layer (VITO), pixel electrode layer (PITO), etc.

[0054] In Figure 4 , the second SD wiring portion 320 of the SD metal line in the frame glue area 122 and the second gate wiring portion 220 of the gate metal line in the frame glue area 122 are vertically overlapped and wired up and down.

[0055] Furthermore, the first SD wiring portion 310 is an upper-sector-segment SD wiring, and the second SD wiring portion 320 is a straight-segment SD wiring; the first SD wiring portion 310 is formed on the upper end of the second SD wiring portion 320.

[0056] Furthermore, as Figure 2 , the first SD wiring portion 310 is a lower-sector-segment SD wiring, and the second SD wiring portion 320 is a straight-segment SD wiring; the first SD wiring portion 310 is formed on the lower end of the second SD wiring portion 320.

[0057] The fan-out 120 of the first SD trace portion 310 includes upper and lower portions located in the non-underfill region 121, and the second SD trace portion 320 is located between the upper and lower portions in the underfill region 122.

[0058] Furthermore, as Figure 2 , the first gate trace portion 210 is a fan-out upper segment gate trace, and the second gate trace portion 220 is a straight segment gate trace; the first gate trace portion 210 is formed on the upper end of the second gate trace portion 220.

[0059] Furthermore, as Figure 2 , the first gate trace portion 210 is a fan-out lower segment gate trace, and the second gate trace portion 220 is a straight segment gate trace; the first gate trace portion 210 is formed on the lower end of the second gate trace portion 220.

[0060] The fan-out 120 of the first gate trace portion 210 includes upper and lower portions located in the non-underfill region 121, and the second gate trace portion 220 is located between the upper and lower portions in the underfill region 122.

[0061] In a second aspect, a display panel includes the array substrate of the first aspect.

[0062] By stagger-wiring the gate metal trace and the SD metal trace in the non-underfill region 121 of the fan-out region 120 in the array substrate and the display panel implementing the present utility model, the RC Loading of the wiring in the fan-out region 120 is reduced, and the gate metal trace and the SD metal trace are overlapped vertically and horizontally in the underfill region 122, thereby solving the problem of the decline in the underfill effect caused by all stagger-wiring.

[0063] The above are only the preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An array substrate, characterized in that, include: Gate metal line; SD metal wire; Driver IC; The SD metal line is formed on the gate metal line; The SD metal line and the gate metal line pass through the sector area of the display panel and are electrically connected to the driving IC; The SD metal line and the gate metal line respectively include a first SD routing portion and a first gate routing portion; The first SD wiring portion and the first gate wiring portion are wired in the non-frame glue area of the fan-shaped area; The first SD wiring portion and the first gate wiring portion are vertically staggered in wiring.

2. The array substrate according to claim 1, wherein The SD metal line and the gate metal line further include: A second SD wiring portion and a second gate wiring portion; The second SD wiring portion and the second gate wiring portion are wired in the frame glue area of the fan-shaped area; The second SD wiring portion and the second gate wiring portion are vertically overlapped and wired.

3. The array substrate according to claim 2, wherein The first SD routing portion is an upper fan-shaped segment SD routing portion, and the second SD routing portion is a straight segment SD routing portion; The first SD wiring portion is formed on an upper end of the second SD wiring portion.

4. The array substrate according to claim 2, wherein The first SD routing portion is a lower fan-shaped segment SD routing, and the second SD routing portion is a straight segment SD routing; The first SD wiring portion is formed at a lower end of the second SD wiring portion.

5. The array substrate according to claim 2, characterized in that, The first gate wiring portion is an upper fan-shaped gate wiring portion, and the second gate wiring portion is a straight-segment gate wiring portion; The first gate wiring portion is formed on an upper end of the second gate wiring portion.

6. The array substrate according to claim 2, wherein, The first gate wiring portion is a lower fan-shaped gate wiring portion, and the second gate wiring portion is a straight-segment gate wiring portion; The first gate wiring portion is formed at a lower end of the second gate wiring portion.

7. A display panel, characterized in that, The invention comprises the array substrate according to any one of claims 1 to 6.

Images