Connection structure of 5G terminal antenna

Abstract

The utility model discloses a connection structure of a 5G terminal antenna, relates to the technical field of antennas, and aims to solve the problem that the performance of a 5G terminal cannot be optimal due to the fact that LTE and NR work at the same time when the 5G terminal is in NSA and a plurality of antennas work at the same time and are easily influenced by the environment, and comprises an antenna mainboard, a mounting seat, a composite antenna and an antenna shell, a pin A3 of a radio frequency chip U1 on an antenna mainboard is sequentially connected with a resistor R1, an antenna high-frequency suppression inductor L5 and an antenna feed blocking capacitor C2, a node between the antenna feed blocking capacitor C2 and the antenna high-frequency suppression inductor L5 is connected with an antenna feed port E1, and the other end of the antenna feed blocking capacitor C2 is connected with a switch array U2. A sixth pin, a fifth pin, a thirteenth pin and a first pin of the switch array U2 are respectively connected with the ground matching inductor and are grounded, an adjustable capacitor C1 is arranged in the switch array U2, antenna capacitive reactance is detected through the radio frequency chip U1, and the switch array U2 realizes impedance control by using the adjustable capacitor C1 and the ground matching inductor, so that the antenna performance reaches an optimal state.

Description

Technical Field

[0001] The utility model relates to the technical field of antennas, and specifically relates to a connection structure of a 5G terminal antenna. Background Technique

[0002] A 5G terminal is a device that can access and use the 5G network for communication and data processing. It has high-speed connection capabilities, enabling data transmission rates of several gigabits per second, allowing users to quickly download large files, watch high-definition videos, and play online games smoothly; it has low-latency characteristics, which can be as low as the millisecond level, and is crucial for applications with extremely high real-time requirements such as autonomous driving, industrial automation, and remote medical treatment; it usually has strong multi-device connection capabilities, allowing multiple devices to be connected simultaneously for interconnection and interoperability, creating an intelligent living and working environment for users.

[0003] For example, the patent with the publication number CN115296064A discloses a dual-channel antenna connection structure. In the dual-channel antenna connection structure of the embodiment of the present invention, by arranging the plug end of the composite antenna inside a plug housing including a housing, an opening, and a spring piece, and arranging the connection port inside an interface housing with a groove on its outer surface, the protrusion on the spring piece near the opening on the inner side of the housing can cooperate with the groove on the interface housing, so that the plug housing and the interface housing can be snap-fitted and positioned. However, there are multiple antennas inside the 5G terminal. Currently, in NSA mode of the 5G terminal, LTE and NR work simultaneously, and multiple antennas work simultaneously. The antennas are easily affected by the environment, resulting in the antenna performance not being able to reach the optimal level.

[0004] In view of the above problems, a connection structure of a 5G terminal antenna is proposed. Content of the Utility Model

[0005] The purpose of the utility model is to provide a connection structure of a 5G terminal antenna. By using this device for operation, the problem that in NSA mode of the 5G terminal, LTE and NR work simultaneously, and multiple antennas work simultaneously and are easily affected by the environment, resulting in their performance not being able to reach the optimal level in the above background is solved.

[0006] To achieve the above object, the present utility model provides the following technical solution: A connection structure of a 5G terminal antenna, including an antenna main board and a mounting base fixedly welded to one end of the top of the antenna main board. A composite antenna is fixedly connected to the outer wall of one side of the mounting base, and an antenna housing is sleeved outside the composite antenna. The antenna main board includes a radio frequency chip U1. The A3 pin of the radio frequency chip U1 is connected to a resistor R1, the other end of the resistor R1 is connected to an antenna high-frequency suppression inductor L5, the other end of the antenna high-frequency suppression inductor L5 is connected to an antenna feed DC-blocking capacitor C2, and a line node between the antenna feed DC-blocking capacitor C2 and the antenna high-frequency suppression inductor L5 is connected to an antenna feed port E1 through a wire. The other end of the antenna feed DC-blocking capacitor C2 is connected to a switch array U2. Ground matching inductors L1, L2, L3, and L4 are respectively connected to the 6th, 5th, 13th, and 1st pins of the switch array U2, and the other ends of the ground matching inductors L1, L2, L3, and L4 are respectively connected to ground wires. The 3rd pin of the switch array U2 is connected to the antenna feed DC-blocking capacitor C2. The 2nd and 14th pins of the switch array U2 are connected in series and then connected to the RF_IN port. An adjustable capacitor C1 is provided inside the switch array U2, and both ends of the adjustable capacitor C1 are respectively connected to the 2nd and 3rd pins of the switch array U2.

[0007] Further, the A2 pin of the radio frequency chip U1 is connected to a VCC voltage input port, and its A7 pin is connected to a ground wire.

[0008] Further, the A1, B1, and B2 pins of the radio frequency chip U1 are all connected to the control port of the radio frequency chip U1.

[0009] Further, the 3rd and 4th pins of the switch array U2 are connected in series and then connected to the node at the end of the antenna feed DC-blocking capacitor C2 far from the antenna high-frequency suppression inductor L5.

[0010] Further, the 7th, 12th, and 15th pins of the switch array U2 are all respectively connected to ground wires, and its 8th pin is connected to a VCC voltage input port.

[0011] Further, a control switch is respectively connected to both ends of the adjustable capacitor C1. After the control switches at both ends of the adjustable capacitor C1 are connected in series, they are respectively connected to the 2nd and 3rd pins of the switch array U2.

[0012] Compared with the prior art, the beneficial effects of the present utility model are as follows:

[0013] A connection structure of a 5G terminal antenna proposed by the present utility model. The radio frequency chip U1 on the antenna main board is connected to the switch array U2 through the resistor R1, the antenna high-frequency suppression inductor L5, and the antenna feed DC-blocking capacitor C2. The adjustable capacitor C1 and the ground matching inductor L1 on the switch array U2 can form a PI matching array to control the antenna impedance. The radio frequency chip U1 detects the antenna capacitive reactance to achieve the optimal antenna performance. By controlling the adjustable capacitor C1 inside the switch array U2 and selecting a suitable ground inductor connection, the matching value of the antenna is set. The switch array U2 changes the size of the internally connected capacitor and the size of the ground inductor to improve the antenna usage efficiency, and improves the antenna signal stability, impedance matching, and circuit safety and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the overall structure of the present utility model;

[0015] Figure 2 It is a block diagram of the antenna main board architecture of the present utility model;

[0016] Figure 3 It is a schematic diagram of the working principle circuit of the antenna main board of the present utility model;

[0017] Figure 4 It is a working flow chart of the antenna main board of the present utility model.

[0018] In the figure: 1. Antenna main board; 2. Mounting seat; 3. Composite antenna; 4. Antenna housing. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without making creative efforts shall fall within the protection scope of the present utility model.

[0020] To further understand the content of the present utility model, the present utility model will be described in detail in conjunction with the accompanying drawings.

[0021] To solve the problem that when the 5G terminal works with LTE and NR simultaneously in NSA, multiple antennas working simultaneously are easily affected by the environment and their performance cannot reach the optimal level, please refer to Figures 1 - 4 , and the following preferred technical solutions are provided:

[0022] A connection structure of a 5G terminal antenna of the present utility model mainly consists of an antenna main board 1 and a mounting seat 2 installed at one end of the top of the antenna main board 1. A composite antenna 3 is fixed on one outer wall of the mounting seat 2. An antenna housing 4 is sleeved outside the composite antenna 3. The antenna housing 4 is of a two-piece type, and the two sections of the antenna housing 4 can be rotated and deflected by 90 degrees.

[0023] The present utility model will be further described below in conjunction with embodiments.

[0024] A radio frequency chip U1 (chip model: AW96103) is provided on the antenna main board 1. The A3 pin of the radio frequency chip U1 is connected to a resistor R1. The other end of R1 is connected to an antenna high-frequency suppression inductor L5. The antenna high-frequency suppression inductor L5 is then connected to an antenna feed DC-blocking capacitor C2. The line node between C2 and L5 is connected to an antenna feed port E1 through a wire. The other end of the antenna feed DC-blocking capacitor C2 is connected to a switch array U2 (model of the switch array U2: QAT3350). The 6th, 5th, 13th, and 1st pins of the switch array U2 are respectively connected to ground matching inductors L1, L2, L3, and L4. The other ends of these ground matching inductors are all connected to a ground wire. The 3rd pin of the switch array U2 is connected to the antenna feed DC-blocking capacitor C2. The 2nd and 14th pins of the switch array U2 are connected in series and then connected to an RF_IN port, which is specifically used for receiving radio frequency signals. An adjustable capacitor C1 is provided inside the switch array U2. After both ends of C1 are respectively connected to a control switch and then respectively connected to the 2nd and 3rd pins of the switch array U2. The A2 pin of the radio frequency chip U1 is connected to a VCC voltage input port, and the input voltage is 1.8V. Its A7 pin is connected to a ground wire. The A1, B1, and B2 pins of the radio frequency chip U1 are all connected to the control port of the radio frequency chip U1. The 3rd and 4th pins of the switch array U2 are connected in series and then connected to the node at the end of the antenna feed DC-blocking capacitor C2 far from the antenna high-frequency suppression inductor L5. The 7th, 12th, and 15th pins of the switch array U2 are all connected to a ground wire, and its 8th pin is connected to a VCC voltage input port.

[0025] The A2 pin of the RF chip U1 is connected to the VCC voltage input port to provide the operating voltage for the RF chip U1. The A7 pin is connected to the ground wire to ensure stable grounding of the circuit. The A1, B1, and B2 pins are connected to the control port of the RF chip U1 to receive external control signals for operation control of the chip. Starting from the A3 pin of the RF chip U1, the signal passes through the resistor R1 to limit the current or adjust the signal strength, and then is connected to the antenna high-frequency suppression inductor L5. This inductor can effectively suppress high-frequency interference signals and ensure the purity of the signals received and transmitted by the antenna. Then it is connected to the antenna feed DC-blocking capacitor C2. This capacitor functions to block DC signals and prevent them from entering the subsequent circuit, allowing only AC RF signals to pass through. The node on the line between the antenna feed DC-blocking capacitor C2 and the antenna high-frequency suppression inductor L5 is connected to the antenna feed port E1 through a wire to achieve the feed input of the antenna. The other end of the antenna feed DC-blocking capacitor C2 is connected to the switch array U2. The 3rd and 4th pins of the switch array U2 are connected in series and then connected to the node at the end of the antenna feed DC-blocking capacitor C2 far from the antenna high-frequency suppression inductor L5. The 2nd and 14th pins of the switch array U2 are connected in series and then connected to the RF_IN port to receive the RF input signal. The two ends of the adjustable capacitor C1 inside the switch array U2 are respectively connected to a control switch. After being connected in series with the control switch, it is then connected to the 2nd and 3rd pins of the switch array U2. The capacitance value of the adjustable capacitor C1 can be adjusted by controlling the switch. At the same time, the 6th, 5th, 13th, and 1st pins of the switch array U2 are respectively connected to the ground matching inductors L1, L2, L3, and L4. The other ends of these inductors are all connected to the ground wire. Through the variable capacitor inside the switch array U2 and the inductors connected to the ground, a PI matching array can be realized to control the impedance of the antenna.

[0026] Specifically, first, test the impedance value of the antenna under the condition of changing the capacitance value and record the corresponding impedance matching values in a list. During actual use, the RF chip U1 detects the change in the antenna capacitive reactance, then finds the corresponding matching value through the list, and sets the matching value of the antenna by controlling the adjustable capacitor C1 inside the switch array U2 and selecting appropriate ground inductors. The switch array U2 changes the size of the internally connected series capacitor and the size of the ground inductor to improve the efficiency of the antenna and make the antenna performance reach the optimal state.

[0027] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device.

[0028] Although the embodiments of the present utility model have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle and spirit of the present utility model. The scope of the present utility model is defined by the appended claims and their equivalents.

Claims

1. A connection structure of a 5G terminal antenna, comprising an antenna main board (1) and a mounting base (2) fixedly welded to one end of the top of the antenna main board (1). A composite antenna (3) is fixedly connected to an outer wall of one side of the mounting base (2). An antenna housing (4) is sleeved outside the composite antenna (3), and is characterized in that: The antenna main board (1) includes a radio frequency chip U1. The A3 pin of the radio frequency chip U1 is connected to a resistor R1. The other end of the resistor R1 is connected to an antenna high-frequency suppression inductor L5. The other end of the antenna high-frequency suppression inductor L5 is connected to an antenna feed DC-blocking capacitor C2. The line node between the antenna feed DC-blocking capacitor C2 and the antenna high-frequency suppression inductor L5 is connected to an antenna feed port E1 through a wire. The other end of the antenna feed DC-blocking capacitor C2 is connected to a switch array U2. The 6th, 5th, 13th, and 1st pins of the switch array U2 are respectively connected to ground matching inductors L1, L2, L3, and L4, and the other ends of the ground matching inductors L1, L2, L3, and L4 are respectively connected to ground wires. The 3rd pin of the switch array U2 is connected to the antenna feed DC-blocking capacitor C2. The 2nd and 14th pins of the switch array U2 are connected in series and then connected to the RF_IN port. An adjustable capacitor C1 is provided inside the switch array U2, and the two ends of the adjustable capacitor C1 are respectively connected to the 2nd and 3rd pins of the switch array U2.

2. The connection structure of a 5G terminal antenna according to claim 1, characterized in that: The A2 pin of the radio frequency chip U1 is connected to the VCC voltage input port, and its A7 pin is connected to a ground wire.

3. The connection structure of a 5G terminal antenna according to claim 2, wherein: The A1, B1, and B2 pins of the radio frequency chip U1 are all connected to the control port of the radio frequency chip U1.

4. The connection structure of a 5G terminal antenna according to claim 1, characterized in that: The 3rd and 4th pins of the switch array U2 are connected in series and then connected to the node at the end of the antenna feed DC-blocking capacitor C2 away from the antenna high-frequency suppression inductor L5.

5. The connection structure of a 5G terminal antenna according to claim 1, characterized in that: The 7th, 12th, and 15th pins of the switch array U2 are all respectively connected to ground wires, and its 8th pin is connected to the VCC voltage input port.

6. The connection structure of a 5G terminal antenna according to claim 1, characterized in that: Each end of the adjustable capacitor C1 is respectively connected to a control switch. After the two ends of the adjustable capacitor C1 are connected in series with the control switches, they are respectively connected to the 2nd and 3rd pins of the switch array U2.

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