Clock detection circuit and image sensor
Through the simplified clock detection circuit structure, the combination of AND gate, switch parts and capacitors is used to solve the problems of complexity and high power consumption of existing clock frequency detection circuits, and realize low complexity and low power consumption clock frequency detection, improving user experience.
Patent Information
- Application Number
- CN202422009659.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-08-19
AI Technical Summary
The existing clock frequency detection circuit is complex, consumes a lot of hardware resources and has high power consumption, and has circuit stability problems.
A clock detection circuit including a first AND gate, a first switch element, a second switch element, a first capacitor, a second capacitor, a comparator and a flip-flop is used to determine the clock frequency through logic operations and capacitance charging and discharge, thereby reducing circuit complexity and power consumption.
It realizes accurate detection of input system clock frequency under smaller layout area and low power consumption, improving user experience.
Smart Images
Figure CN223155105U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of image sensors, and particularly relates to a clock detection circuit and an image sensor. Background Art
[0002] Image sensors have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and household appliances. The clock circuit in an image sensor is an important part of its analog-to-digital circuit. Under the accurate drive of the clock circuit, the image sensor transmits the sampled signal to the digital processing module for processing. The system clock input to the chip is often provided by a crystal oscillator. As the input reference clock of the entire chip, its frequency determines the normality of each clock inside the chip. Detecting whether the system clock frequency is within the designed value is crucial for monitoring the normal operation of the chip.
[0003] During the process of conceiving and forming the present application, the applicant found that since the commonly used clock frequency detection circuit is often relatively complex, requiring a counter, an operational amplifier, etc., this will consume more hardware resources and power consumption, and there are problems with circuit stability. Therefore, how to use a stable clock frequency detection circuit with a smaller layout area and lower power consumption to complete the frequency detection of the input clock is an urgent problem to be solved. Summary of the Invention
[0004] To alleviate the above problems, the present application provides a clock detection circuit, including a first AND gate, a first switch element, a second switch element, a first capacitor, a second capacitor, a comparator, and a trigger;
[0005] The first input terminal of the first AND gate is connected to an enable signal, the second input terminal of the first AND gate is connected to a first clock signal, and the output terminal of the first AND gate is connected to the control terminal of the first switch element;
[0006] The first terminal of the first capacitor is connected to the first terminal of the first switch element, the second terminal of the first capacitor is grounded, the second capacitor is connected between the second terminal of the first switch element and the ground, and the third terminal of the first switch element is grounded;
[0007] The first terminal of the second switch element is connected to a first preset voltage, and the second terminal of the second switch element is connected to the second terminal of the first switch element;
[0008] The positive input terminal of the comparator is connected to the second terminal of the second switch element, the negative input terminal of the comparator is connected to a second preset voltage, and the output terminal of the comparator is connected to the input terminal of the trigger;
[0009] The trigger terminal of the trigger is connected to the second input terminal of the first AND gate, the reset terminal of the trigger is connected to the first input terminal of the first AND gate, and the output terminal of the trigger outputs a clock detection result signal.
[0010] Optionally, the clock detection circuit further includes a frequency up-conversion circuit. The input end of the frequency up-conversion circuit is connected to the second input end of the first AND gate, and the output end of the frequency up-conversion circuit is connected to the trigger end of the flip-flop. The frequency up-conversion circuit is used to increase the trigger frequency of the trigger end to avoid the clock detection result signal output from the output end of the flip-flop from being delayed and flipped.
[0011] Optionally, the first switching element includes a first transmission gate and a second transmission gate;
[0012] The first control end of the first transmission gate is connected to the first control signal output from the output end of the first AND gate, the second control end of the first transmission gate is connected to the second control signal, the input end of the first transmission gate serves as the first end of the first switching element, and the output end of the first transmission gate is grounded;
[0013] The first control end of the second transmission gate is connected to the second control signal, the second control end of the second transmission gate is connected to the first control signal output from the output end of the first AND gate, the output end of the second transmission gate is connected to the output end of the second switching element, and the input end of the second transmission gate is connected to the input end of the first transmission gate;
[0014] Wherein, the first control signal and the second control signal are complementary control signals.
[0015] Optionally, the second switching element is a field effect transistor.
[0016] Optionally, the clock detection circuit further includes a signal stabilization unit, and the signal stabilization unit is connected to the output end of the flip-flop.
[0017] Optionally, the signal stabilization unit includes a first NOT gate and a second NOT gate. The input end of the first NOT gate is connected to the output end of the flip-flop, the output end of the first NOT gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate outputs the clock detection result signal.
[0018] Optionally, the first preset voltage is greater than the second preset voltage.
[0019] Optionally, the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.
[0020] The present application further provides an image sensor, including the clock detection circuit as described above.
[0021] The clock detection circuit and image sensor provided by this application have an enable signal connected to the first input terminal of the first AND gate, a first clock signal connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate connected to the control terminal of the first switching element; one end of the first capacitor is connected to one end of the first switching element, the other end of the first capacitor is grounded, the second capacitor is connected between the other end of the first switching element and the ground, and the third end of the first switching element is grounded; one end of the second switching element is connected to a first preset voltage, and the second end of the second switching element is connected to the second end of the first switching element; the positive input terminal of the comparator is connected to the second end of the second switching element, the negative input terminal of the comparator is connected to a second preset voltage, and the output terminal of the comparator is connected to the input terminal of the flip-flop; the trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal. This application adopts an input system clock detection circuit, which can determine whether the input system clock frequency meets the design requirements and improves the user experience. Brief Description of the Drawings
[0022] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0023] Figure 1 It is a schematic diagram of the clock detection circuit according to an embodiment of this application.
[0024] Figure 2 It is a schematic diagram of the connection architecture of the first switching element S1 and the second switching element S2 according to an embodiment of this application.
[0025] Figure 3 It is a flowchart of the clock detection method according to an embodiment of this application.
[0026] Figure 4 It is a timing diagram of key nodes of the clock detection according to an embodiment of this application.
[0027] The realization of the purpose of this application, its functional features and advantages will be further described in combination with the embodiments with reference to the drawings. Through the above drawings, the clear embodiments of this application have been shown, and there will be more detailed descriptions later. These drawings and text descriptions are not intended to limit the scope of the concept of this application in any way, but to explain the concept of this application to those skilled in the art by referring to specific embodiments. Detailed Description of the Embodiments
[0028] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0029] It should be noted that in this document, the terms "including", "comprising", or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements includes not only those elements but also other elements not expressly listed, or elements that are inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article, or device that includes the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.
[0030] It should be understood that the specific embodiments described herein are merely used to explain the present application and are not used to limit the present application.
[0031] First Embodiment
[0032] The present application provides a clock detection circuit. Figure 1 It is a schematic diagram of the clock detection circuit according to an embodiment of the present application.
[0033] As Figure 1 shown, in one embodiment, the clock detection circuit includes a first AND gate AND, a first switch S1, a second switch S2, a first capacitor C1, a second capacitor C2, a comparator CMP, and a flip-flop DFF.
[0034] Exemplarily, a clock circuit is an electronic circuit for generating and distributing clock signals. The clock signal plays a role in synchronizing and coordinating the operations of various components in a digital system. It provides a unified time reference, enabling data transmission and processing in the system to occur in the correct order and at the correct time.
[0035] A first input terminal of the first AND gate AND is connected to an enable signal, a second input terminal of the first AND gate AND is connected to a first clock signal, and an output terminal of the first AND gate AND is connected to a control terminal of the first switch S1.
[0036] Exemplarily, an AND gate is a circuit that implements a logical "multiplication" operation. It has more than two input terminals and one output terminal (generally, a circuit has only one output terminal, while an ECL circuit has two output terminals). Only when all input terminals are at a high level (logical "1"), the output of this circuit is at a high level (logical "1"); otherwise, the output is at a low level (logical "0").
[0037] The first end of the first capacitor C1 is connected to the first end of the first switch S1. The second end of the first capacitor C1 is grounded. The second capacitor C2 is connected between the second end of the first switch S1 and the ground. The third end of the first switch S1 is grounded.
[0038] The first end of the second switch S2 is connected to a first preset voltage. The second end of the second switch S2 is connected to the second end of the first switch S1.
[0039] The positive input terminal of the comparator CMP is connected to the second end of the second switch S2. The negative input terminal of the comparator CMP is connected to a second preset voltage. The output terminal of the comparator CMP is connected to the input terminal of the flip-flop DFF.
[0040] Exemplarily, a comparator is a circuit or device that can implement a comparison function. A comparator is a circuit that compares an analog voltage signal with a reference voltage. The two inputs of the comparator are analog signals, and the output is a binary signal 0 or 1. When the difference between the input voltages increases or decreases and the positive and negative signs remain unchanged, its output remains constant.
[0041] The trigger terminal of the flip-flop DFF is connected to the second input terminal of the first AND gate AND. The reset terminal of the flip-flop DFF is connected to the first input terminal of the first AND gate AND. The output terminal of the flip-flop DFF outputs a clock detection result signal.
[0042] Exemplarily, a flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit that constitutes various sequential circuits and is also an important unit circuit in digital logic circuits. Therefore, flip-flops have a wide range of applications in digital systems and computers. Exemplarily, a D flip-flop has two stable states, namely 0 and 1, and can flip from one stable state to another under the action of certain external signals.
[0043] In this embodiment, an enable signal is input to the first input terminal of the first AND gate, a first clock signal is input to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the control terminal of the first switch element; the first end of the first capacitor is connected to the first end of the first switch element, the second end of the first capacitor is grounded, the second capacitor is connected between the second end of the first switch element and the ground, and the third end of the first switch element is grounded; the first end of the second switch element is connected to a first preset voltage, and the second end of the second switch element is connected to the second end of the first switch element; the positive input terminal of the comparator is connected to the second end of the second switch element, the negative input terminal of the comparator is connected to a second preset voltage, and the output terminal of the comparator is connected to the input terminal of the flip-flop; the trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal. By adopting the input system clock detection circuit, it is possible to determine whether the input system clock frequency meets the design requirements, improving the user experience.
[0044] Optionally, the clock detection circuit further includes a frequency-up conversion circuit. The input terminal of the frequency-up conversion circuit is connected to the second input terminal of the first AND gate, and the output terminal of the frequency-up conversion circuit is connected to the trigger terminal of the flip-flop. The frequency-up conversion circuit is used to increase the trigger frequency of the trigger terminal to avoid the clock detection result signal output from the output terminal of the flip-flop from being delayed and inverted.
[0045] Exemplarily, the first clock signal is converted into a second clock signal with a higher frequency through the frequency-up conversion circuit and output to the enable terminal of the flip-flop, which can increase the enable signal frequency of the enable trigger terminal of the flip-flop. When the comparator flips, the flip-flop can avoid being delayed and inverted, thus avoiding clock frequency errors.
[0046] Figure 2 It is a schematic diagram of the connection architecture of the first switch element S1 and the second switch element S2 according to an embodiment of the present application.
[0047] As Figure 2 shown, optionally, the first switch element S1 includes a first transmission gate A1 and a second transmission gate B1.
[0048] The first control terminal of the first transmission gate A1 is connected to the first control signal Vs1 output from the output terminal of the first AND gate AND, the second control terminal of the first transmission gate A1 is connected to the second control signal Vs1b, the input terminal of the first transmission gate A1 serves as the first end of the first switch element S1, and the output terminal of the first transmission gate A1 is grounded.
[0049] The first control terminal of the second transmission gate B1 is connected to the second control signal Vs1b, the second control terminal of the second transmission gate B1 is connected to the first control signal Vs1 output from the output terminal of the first AND gate AND, the output terminal of the second transmission gate B1 is connected to the output terminal of the second switch element S2, and the input terminal of the second transmission gate B1 is connected to the input terminal of the first transmission gate A1;
[0050] Among them, the first control signal Vs1 and the second control signal Vs1b are complementary control signals.
[0051] Optionally, a clock differential output circuit is connected to the output end of the first AND gate for generating two mutually inverted control signals. The clock differential output circuit includes, but is not limited to, any of the following structures: direct differential amplifier structure, transformer-coupled differential output, logic gate generating differential signal, differential signal buffer structure, etc.
[0052] Exemplarily, a transmission gate (TG gate) is an electronic component, mainly an analog switch for transmitting analog signals. It is composed of a P-channel and an N-channel enhancement-mode MOSFET connected in parallel and can transmit signals in a digital circuit. The main function of the TG gate is to allow or block the current under specific conditions, thereby achieving signal transmission or blocking. In digital circuit logic design, the TG gate (CMOS transmission gate) functions similarly to an OC gate. When the control signal is at a high level, both the P-channel and N-channel MOSFETs are turned on, allowing the signal to pass to the output end; when the control signal is at a low level, both are turned off, and the output end presents a high impedance state (Z). This characteristic enables the TG gate to play a role in level conversion, similar to an OC gate. Using multiple transmission gates in cooperation with appropriate control voltages can achieve the effect of a single-pole multi-throw switch.
[0053] Optionally, the second switching element is a field effect transistor.
[0054] Exemplarily, a field effect transistor (abbreviated as FET) is simply called a field effect tube. A field effect transistor (FET) is a semiconductor device that uses the electric field effect of the input circuit to control the current in the output circuit. There are mainly two types: junction field effect transistor (junction FET—JFET) and metal-oxide semiconductor field effect transistor (metal-oxide semiconductor FET, abbreviated as MOS-FET). It is a unipolar transistor in which majority carriers participate in conduction. It belongs to a voltage-controlled semiconductor device. It has the advantages of high input resistance (107~1015Ω), low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, and wide safe operating area.
[0055] Optionally, the clock detection circuit further includes a signal stabilization unit, and the signal stabilization unit is connected to the output end of the flip-flop.
[0056] Exemplarily, the signal output by the flip-flop may have limited power and limited load-carrying capacity. Therefore, the signal output by the flip-flop can be stabilized through the signal stabilization unit to enhance the load-carrying capacity of the flip-flop.
[0057] Optionally, the signal stabilization unit includes a first NOT gate and a second NOT gate. The input terminal of the first NOT gate is connected to the output terminal of the flip-flop. The output terminal of the first NOT gate is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate outputs a clock detection result signal.
[0058] Exemplarily, by performing two NOT operations on the signal output by the first flip-flop, the load-carrying capacity of the data output signal output by the first flip-flop can be effectively improved, data errors during data transmission can be avoided, and the data transmission accuracy rate can be effectively improved.
[0059] Optionally, the first preset voltage is greater than the second preset voltage.
[0060] Exemplarily, after the first preset voltage charges the second capacitor, the voltage across the second capacitor is equal to the first preset voltage. When the first switching element is alternately turned on, the voltage across the second capacitor gradually decreases. When the voltage across the second capacitor drops below the second preset voltage, the output signal of the comparator will flip.
[0061] Optionally, the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.
[0062] Exemplarily, when the first switching element is alternately turned on, the first end of the first capacitor switches between being grounded and connecting to the first end of the second capacitor. When the capacitance value of the first capacitor is much smaller than that of the second capacitor, in each alternating cycle, the node voltage at the positive input terminal of the comparator will slightly decrease, causing the voltage across the second capacitor to gradually decrease.
[0063] Second Embodiment
[0064] The present application also provides a clock detection method, which is applied to the clock detection circuit as described above. Figure 3 This is a flowchart of the clock detection method according to an embodiment of the present application.
[0065] As Figure 3 shown, in one embodiment, the clock detection method includes:
[0066] S10: By invalidating the enable signal, controlling the first switching element to ground both ends of the first capacitor, and controlling the second switching element to conduct to charge the second capacitor to the first preset voltage, where the first preset voltage is greater than the second preset voltage.
[0067] S20: Controlling the second switching element to turn off, flipping the enable signal to be valid, alternately turning on the first switching element based on the first clock signal, and controlling the first end of the first capacitor to alternately switch between being grounded and connecting to the second capacitor, so that the input voltage at the positive input terminal of the comparator conforms to the first preset function expression, where the capacitance value of the first capacitor is less than the capacitance value of the second capacitor.
[0068] S30: When the voltage value of the second capacitor drops below the second preset voltage, the output voltage of the comparator flips. Based on the Taylor expansion of the first preset function expression, the pulse width of the detection clock detection signal is detected as the frequency detection result of the first clock signal.
[0069] Optionally, the first preset function expression is:
[0070]
[0071] The expression of the Taylor expansion of the first preset function expression is:
[0072]
[0073] Where Vin is the input voltage of the positive input terminal of the comparator, C1 is the capacitance value of the first capacitor, C2 is the capacitance value of the second capacitor, V1 is the voltage value of the first preset voltage, and n is the number of cycles.
[0074] Figure 4 It is the timing diagram of the key nodes for clock detection in an embodiment of the present application.
[0075] Please continue to refer to Figure 2 、 Figure 3 and Figure 4 , Exemplarily, in the preparation stage, at this time the enable signal is invalid, that is, dec_en = 0 is a low-level signal, the second switch S2 is turned on, and at this time both ends of the first capacitor C1 are grounded; the upper plate of the second capacitor C2 is charged to the first preset voltage V1, the value of the second preset voltage Vref is lower than V1 (for example, Vref = 0.8 * V1), and the output voltage Vo1 of the comparator = 1 is a high-level signal; the flip-flop DFF is in the reset state, and the flip-flop outputs a clock detection result signal Vo = 0 as a low-level signal; before the end of the preparation stage, the second switch S2 is turned off, and the charge of the second capacitor C2 is completely stored.
[0076] Exemplarily, in the detection stage, when the enable signal dec_en changes from 0 to 1, the reset state of the flip-flop DFF ends. The output voltage Vo1 = 1 of the comparator, which is a high-level signal, is transmitted to the output of the flip-flop DFF, and the output clock detection result signal Vo of the flip-flop changes from the low level 0 to the high level 1. Since the enable signal dec_en = 1 is a high-level signal, the AND logic gate of the AND gate is effective, and the input system clock signal clk_in is transmitted to the output end of the AND gate to generate the control terminal signals Vs1 and Vs1b of the first switch S1. The first switch S1 conducts alternately, and the positive terminal of the first capacitor C1 switches between grounding and connecting to the positive electrode of the second capacitor C2. It is set that the capacitance value of the first capacitor C1 is much smaller than that of the second capacitor C2 (for example, the capacitance ratio of the first capacitor to the second capacitor is c1 = 0.01 * c2). In each cycle, the voltage of the Vin node at the positive input terminal of the comparator will decrease slightly, and its voltage expression is as follows:
[0077]
[0078] Where n represents the number of cycles experienced, and its Taylor expansion is as follows:
[0079]
[0080] Optionally, the second preset voltage is greater than the predetermined voltage value, and the predetermined voltage value is positively correlated with the accuracy of the frequency detection result of the first clock signal. It should be explained that the accuracy of the frequency detection result of the first clock signal indicates whether only the range of the clock detection signal needs to be obtained or the specific value of the clock detection signal needs to be obtained. If only the range of the clock detection signal needs to be obtained, the accuracy is low; if the specific value of the clock detection signal needs to be obtained, the accuracy is high. Therefore, the higher the accuracy requirement, the larger the corresponding predetermined voltage value, and the larger the second preset voltage Vref.
[0081] For the given first preset voltage V1, second preset voltage Vref, capacitance values of the first capacitor C1 and the second capacitor C2, determine the number of cycles required for the output of the comparator to flip, so that the input system clock frequency and the detection pulse width are linearly related. By calibrating the upper and lower limits of the pulse width, it can be detected whether the system clock frequency meets the requirements.
[0082] Optionally, based on the Taylor expansion of the first preset function expression, the process of detecting the pulse width of the clock detection signal as the frequency detection result of the first clock signal includes: fixing the number of cycles for the output of the comparator to flip, so that the frequency of the first clock signal is linearly related to the pulse width of the clock detection signal.
[0083] Optionally, based on the Taylor expansion of the first preset function expression, the process of detecting the pulse width of the clock detection signal as the frequency detection result of the first clock signal includes:
[0084] The clock frequency of the first clock signal is directly proportional to the pulse width of the clock detection signal, and the detection result of the first clock signal is determined by the pulse width of the clock detection signal.
[0085] Exemplarily, the number of cycles required for the comparator output to flip is fixed. Therefore, the input system clock frequency and the detected pulse width are linearly related. By calibrating the upper and lower limits of the pulse width, it can be detected whether the system clock frequency meets the requirements.
[0086] Exemplarily, please continue to refer to Figure 2 、 Figure 3 and Figure 4 , since the capacitance value of the first capacitor C1 is much smaller than the capacitance value of the second capacitor C2, the above Taylor expansion can be approximately retained for the first two terms, that is:
[0087]
[0088] Thus, it can be obtained that the voltage drop at the positive input terminal Vin of the comparator is linearly related to n. At this time, the value of the second preset voltage Vref is still lower than V1, Vo1 = 1, and Vo = 1.
[0089] Third Embodiment
[0090] The present application also provides an image sensor, including the clock detection circuit as described above.
[0091] The present application also provides an image sensor. The image sensor includes a memory and a processor. Among them, a computer program is stored on the memory, and when the computer program is executed by the processor, the steps of the clock detection method as described above are implemented.
[0092] For the clock detection method, clock detection circuit, and image sensor provided by the present application, an enable signal is connected to the first input terminal of the first AND gate, the first clock signal is connected to the second input terminal of the first AND gate, and the output terminal of the first AND gate is connected to the control terminal of the first switching element; the first end of the first capacitor is connected to the first end of the first switching element, the second end of the first capacitor is grounded, the second capacitor is connected between the second end of the first switching element and the ground, and the third end of the first switching element is grounded; the first end of the second switching element is connected to the first preset voltage, and the second end of the second switching element is connected to the second end of the first switching element; the positive input terminal of the comparator is connected to the second end of the second switching element, the negative input terminal of the comparator is connected to the second preset voltage, and the output terminal of the comparator is connected to the input terminal of the flip-flop; the trigger terminal of the flip-flop is connected to the second input terminal of the first AND gate, the reset terminal of the flip-flop is connected to the first input terminal of the first AND gate, and the output terminal of the flip-flop outputs a clock detection result signal. The input system clock detection circuit adopted by the present application can determine whether the input system clock frequency meets the design requirements, improving the user experience.
[0093] It should be noted that in this application, step codes such as S10 and S20 are adopted. The purpose is to more clearly and briefly express the corresponding content, and it does not constitute a substantial limitation in sequence. Those skilled in the art may execute S20 first and then S10 during specific implementation, etc., but all of these should be within the protection scope of this application.
[0094] In the embodiments of the image sensor and the clock detection circuit provided in this application, all the technical features of any of the above method embodiments may be included. The content of the specification expansion and explanation is basically the same as that of the above method embodiments, and will not be elaborated here.
[0095] This application embodiment also provides a computer program product. The computer program product includes computer program code. When the computer program code runs on a computer, it causes the computer to execute the methods in the above various possible implementation manners.
[0096] This application embodiment also provides a chip, including a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the device equipped with the chip executes the methods in the above various possible implementation manners.
[0097] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in this application embodiment. The technical solutions of this application can also be applied to other scenarios. For example, as known to those of ordinary skill in the art, with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in this application embodiment are equally applicable to similar technical problems.
[0098] The serial numbers of the above application embodiments are only for description and do not represent the advantages or disadvantages of the embodiments.
[0099] The steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs.
[0100] The units in the device of this application embodiment can be combined, divided, and deleted according to actual needs.
[0101] In this application, for the description of the same or similar term concepts, technical solutions, and / or application scenarios, generally only the first occurrence is described in detail. When it appears repeatedly later, for the sake of brevity, it is generally not elaborated again. When understanding the technical solutions and other contents of this application, for the same or similar term concepts, technical solutions, and / or application scenarios that are not described in detail later, reference can be made to the relevant detailed descriptions before.
[0102] In this application, the descriptions of each embodiment have their own emphases. For the parts not described or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0103] The technical features of the technical solution of the present application can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in the present application.
[0104] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be included in the patent protection scope of the present application by the same token.
Claims
1. A clock detection circuit, characterized in that, It includes a first AND gate, a first switch, a second switch, a first capacitor, a second capacitor, a comparator, and a trigger; The first input terminal of the first AND gate is connected to an enable signal, the second input terminal of the first AND gate is connected to a first clock signal, and the output terminal of the first AND gate is connected to the control terminal of the first switch; The first terminal of the first capacitor is connected to the first terminal of the first switch, the second terminal of the first capacitor is grounded, the second capacitor is connected between the second terminal of the first switch and the ground, and the third terminal of the first switch is grounded; The first terminal of the second switch is connected to a first preset voltage, and the second terminal of the second switch is connected to the second terminal of the first switch; The positive input terminal of the comparator is connected to the second terminal of the second switch, the negative input terminal of the comparator is connected to a second preset voltage, and the output terminal of the comparator is connected to the input terminal of the trigger; The trigger terminal of the trigger is connected to the second input terminal of the first AND gate, the reset terminal of the trigger is connected to the first input terminal of the first AND gate, and the output terminal of the trigger outputs a clock detection result signal.
2. The clock detection circuit according to claim 1, characterized in that The clock detection circuit further includes a frequency-up conversion circuit. The input terminal of the frequency-up conversion circuit is connected to the second input terminal of the first AND gate, and the output terminal of the frequency-up conversion circuit is connected to the trigger terminal of the trigger. The frequency-up conversion circuit is used to increase the trigger frequency of the trigger terminal to avoid the clock detection result signal output by the output terminal of the trigger from being delayed and flipped.
3. The clock detection circuit according to claim 2, wherein The first switch includes a first transmission gate and a second transmission gate; The first control terminal of the first transmission gate is connected to a first control signal output by the output terminal of the first AND gate, the second control terminal of the first transmission gate is connected to a second control signal, the input terminal of the first transmission gate is used as the first terminal of the first switch, and the output terminal of the first transmission gate is grounded; The first control terminal of the second transmission gate is connected to the second control signal, the second control terminal of the second transmission gate is connected to the first control signal output by the output terminal of the first AND gate, the output terminal of the second transmission gate is connected to the output terminal of the second switch, and the input terminal of the second transmission gate is connected to the input terminal of the first transmission gate; Wherein, the first control signal and the second control signal are complementary control signals.
4. A clock detection circuit according to claim 3, characterized in that, The second switch is a field effect transistor.
5. The clock detection circuit according to claim 1, characterized in that The clock detection circuit further includes a signal stabilization unit, and the signal stabilization unit is connected to the output terminal of the trigger.
6. The clock detection circuit according to claim 5, wherein The signal stabilization unit includes a first NOT gate and a second NOT gate. The input terminal of the first NOT gate is connected to the output terminal of the trigger, the output terminal of the first NOT gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate outputs the clock detection result signal.
7. A clock detection circuit according to any one of claims 1-6, characterized in that, The first preset voltage is greater than the second preset voltage.
8. The clock detection circuit according to claim 7, wherein The capacitance value of the first capacitor is less than the capacitance value of the second capacitor.
9. An image sensor, characterized in that, It includes the clock detection circuit according to any one of claims 1-8.