Power semiconductor device test circuit

Abstract

The utility model discloses a power semiconductor device test circuit, relates to the technical field of semiconductor device test, and solves the technical problems of high cost and low test efficiency when a semiconductor device is tested in the prior art. The circuit comprises a driving module and a tested module, wherein the tested module is connected with the driving module; the tested module comprises a tested element Q22, a tested element Q21, an inductor L2 and a switch SW2; a grid electrode of the tested element Q22 is connected with the driving module, a source electrode of the tested element Q22 is grounded, and a drain electrode of the tested element Q22 is connected with the inductor L2; the inductor L2 is connected with the VCC; the grid electrode and the source electrode of the tested element Q21 are in short circuit, the drain electrode of the tested element Q21 is connected with the switch SW2 in series, and the tested element Q21 and the switch SW2 are connected to the two ends of the inductor L2 in parallel after series connection. According to the utility model, double-pulse testing and EAS testing can be carried out on the semiconductor device at the same time, the testing cost is saved, the testing efficiency is improved, and the testing accuracy can be ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor device testing, in particular to a power semiconductor device testing circuit. Background Art

[0002] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which utilizes the special electrical properties of semiconductor materials to perform specific functions and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. After a semiconductor device (such as an IGBT or a single MOSFET) is manufactured, corresponding parameters of the semiconductor device are tested, and the test results are important reference bases for whether the device structure and process need to be improved.

[0003] When testing a semiconductor device, there are two relatively important test items. One is the double-pulse test, and the other is the EAS (single-pulse avalanche breakdown energy) test. When performing a double-pulse test on a semiconductor device, as Figure 1a shown, the upper transistor is continuously turned off, and two pulses are given to the driving signal of the lower transistor to test the switching characteristics of the lower transistor; an inductor is connected in parallel at both ends of the upper transistor to test the reverse diode characteristics of the upper transistor. When performing an EAS test on a semiconductor device, as Figure 1b shown, the single-pulse avalanche breakdown energy is tested through the freewheeling after the inductor is turned off. Currently, when performing the above two tests on a semiconductor device, they need to be carried out in two different test circuits, which will increase the test cost and at the same time affect the test efficiency of the semiconductor device.

[0004] In the process of implementing the present utility model, the inventors found that there are at least the following problems in the prior art:

[0005] When testing a semiconductor device in the prior art, the cost is relatively high and the test efficiency is low. Summary of the Utility Model

[0006] The purpose of the present utility model is to provide a power semiconductor device testing circuit to solve the technical problems of high cost and low test efficiency when testing a semiconductor device in the prior art. The many technical effects that can be produced by the preferred technical solutions provided by the present utility model are described in detail below.

[0007] To achieve the above purpose, the present utility model provides the following technical solutions:

[0008] A power semiconductor device testing circuit provided by the present utility model includes: a driving module and a device under test module, and the device under test module is connected to the driving module;

[0009] The module under test includes a device under test Q22, a device under test Q21, an inductor L2, and a switch SW2; the gate of the device under test Q22 is connected to the driving module, the source is grounded, and the drain is connected to the inductor L2; the inductor L2 is connected to VCC; the gate and source of the device under test Q21 are shorted, and the drain is connected in series with the switch SW2. After the series connection, the device under test Q21 and the switch SW2 are connected in parallel across both ends of the inductor L2.

[0010] Optionally, the driving module includes a driving chip U2;

[0011] The gate of the device under test Q22 in the module under test is connected to the driving chip U2.

[0012] Optionally, the test circuit further includes a voltage regulation module; the voltage regulation module includes a voltage regulation chip U3; the voltage regulation chip U3 includes a VIN interface, an ADJ interface, a TAB interface, and a VOUT interface;

[0013] The VIN interface is connected to a regulated power supply, the ADJ interface is grounded, the VOUT interface outputs a voltage and is connected to the TAB interface, and the VOUT interface is also connected to the driving chip U2.

[0014] Optionally, the test circuit further includes a signal input module, the signal input module includes a connector RF1, and the connector RF1 includes a first interface, a second interface, a third interface, and a fourth interface;

[0015] The second interface, the third interface, and the fourth interface are all grounded, and the first interface is connected to the driving chip U2.

[0016] Optionally, the driving module further includes a transistor Q19 and a transistor Q20;

[0017] The base of the transistor Q19 is connected to the CLAMP interface of the driving chip U2, the collector is connected to a 10V power supply, and the emitter is connected to the gate of the device under test Q22 after a resistor R9 is connected in series;

[0018] The base of the transistor Q20 is connected to the CLAMP interface of the driving chip U2, the emitter is grounded, and the collector is connected to the gate of the device under test Q22 after a resistor R10 is connected in series.

[0019] Optionally, the driving module further includes a resistor R8, a capacitor C12, and a capacitor C13;

[0020] One end of the resistor R8 is connected to the OUT interface on the driving chip U2, and the other end is connected to the CLAMP interface on the driving chip U2;

[0021] One end of the capacitor C12 is grounded and the other end is connected to a 10V power supply;

[0022] One end of the capacitor C13 is grounded and the other end is connected to a 15V power supply.

[0023] Optionally, the driving module further includes a resistor R6 and a resistor R7;

[0024] One end of the resistor R6 is connected to the RDY interface of the driving chip U2, and the other end is connected to the VOUT interface of the voltage stabilizing chip U3;

[0025] One end of the resistor R7 is connected to the #FLT interface of the driving chip U2, and the other end is connected to the VOUT interface of the voltage stabilizing chip U3.

[0026] Optionally, the driving module further includes a capacitor C11; one end of the capacitor C11 is connected to the VOUT interface of the voltage stabilizing chip U3, and the other end is grounded.

[0027] Optionally, the test circuit further includes a filtering module, the filtering module includes a switch SW1 and a plurality of capacitors connected in parallel with the switch SW1, and one end of the parallel-connected switch SW1 and the plurality of capacitors is grounded and the other end is connected to the VCC.

[0028] Optionally, the inductor L2 is an adjustable inductor; the model of the driving chip U2 is 1ED020112FA2.

[0029] Implementing one of the technical solutions in the above technical solutions of the present invention has the following advantages or beneficial effects:

[0030] The present invention can simultaneously perform double-pulse testing and EAS testing on semiconductor devices, saving testing costs, improving testing efficiency, and ensuring testing accuracy at the same time. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for description in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts. In the drawings:

[0032] Figure 1a is a schematic circuit diagram of double-pulse testing of semiconductor devices in the prior art;

[0033] Figure 1b is a schematic circuit diagram of EAS testing of semiconductor devices in the prior art;

[0034] Figure 2 It is a schematic circuit diagram for testing semiconductor devices in a utility model. Detailed implementation manners

[0035] In order to make the objectives, technical solutions and advantages of the present utility model clearer and more understandable, various exemplary embodiments to be described below will refer to the corresponding drawings, which form a part of the exemplary embodiments and describe various exemplary embodiments that may be adopted to implement the present utility model. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. It should be understood that they are only examples of processes, methods, devices, etc. that are consistent with some aspects of the present utility model disclosed in detail in the appended claims. Other embodiments may also be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and essence of the present utility model.

[0036] In the description of the present utility model, it should be understood that terms such as "center", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the drawings shown, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. Terms such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. The meaning of the term "plurality" is two or more. The terms "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and may be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0037] In order to illustrate the technical solutions described in the present utility model, the following will be described by means of specific embodiments, and only the parts related to the embodiments of the present utility model are shown.

[0038] Embodiment:

[0039] As Figure 2As shown in the figure, the present utility model provides a power semiconductor device test circuit, including: a driving module and a device under test module, and the device under test module is connected to the driving module; the device under test module includes a device under test element Q22, a device under test element Q21, an inductor L2, and a switch SW2; the gate of the device under test element Q22 is connected to the driving module, the source is grounded, and the drain is connected to the inductor L2; the inductor L2 is connected to VCC; the gate and the source of the device under test element Q21 are short-circuited, and the drain is connected in series with the switch SW2, and after being connected in series, the device under test element Q21 and the switch SW2 are connected in parallel across both ends of the inductor L2.

[0040] Specifically, the device under test module is connected to the driving module. The driving module is used to drive the entire test circuit, and the device under test module can be tested under the action of the driving module. When the driving module is working, the electrical components in the device under test module will perform corresponding actions. When the switch SW2 is closed, that is, a double-pulse test is performed on the device under test element. At this time, the driving module will control the gate of the device under test element Q22 to turn on and off to observe the dynamic characteristics of the device under test element. The reverse recovery current of the device under test element Q21 can be tested through the freewheeling action of the inductor L2. When SW2 is turned off, it is an EAS (single-pulse avalanche breakdown energy) test, and the avalanche withstand capacity of the device under test element Q22 can be obtained through the inductor.

[0041] It should be noted that the inductor L2 in this embodiment is an adjustable inductor. The reason for setting it as an adjustable inductor is to be able to test the double pulses and avalanches of different semiconductor devices, which can expand the test objects. The model of the adjustable inductor is preferably 1606-10GLC. Using other different models of adjustable inductors is also within the protection scope of this embodiment. In this embodiment, the device under test element Q22 and the device under test element Q21 are selected as N-type MOS transistors for illustration. In actual tests, the device under test elements are not limited to N-type MOS transistors, and other types of device under test elements can also be tested.

[0042] The present utility model can simultaneously perform double-pulse tests and EAS tests on semiconductor devices, saving test costs, improving test efficiency, and ensuring test accuracy at the same time.

[0043] As an optional implementation manner, such as Figure 2As shown in the figure, the test circuit further includes a voltage stabilizing module; the voltage stabilizing module includes a voltage stabilizing chip U3; the voltage stabilizing chip U3 includes a VIN interface, an ADJ interface, a TAB interface, and a VOUT interface; the VIN interface is connected to a regulated power supply, the ADJ interface is grounded, the VOUT interface outputs a voltage and is connected to the TAB interface, and the VOUT interface is also connected to the drive module. The voltage range of the VIN interface in the voltage stabilizing chip U3 is 6.5V - 18V. In this embodiment, the regulated power supply connected to the VIN interface is 10V. The voltage output by VOUT is 5V. The function of the voltage stabilizing module is to stabilize the overall test circuit and ensure the stability of the circuit during the test. It should be noted that the model of the voltage stabilizing chip U3 in this embodiment is preferably AMS1117 - 5.0, and the use of other different models of voltage stabilizing chips is also within the protection scope of this embodiment.

[0044] In addition, as Figure 2 shown in the figure, the test circuit further includes a signal input module. The signal input module includes a connector RF1. The connector RF1 includes a first interface, a second interface, a third interface, and a fourth interface; the second interface, the third interface, and the fourth interface are all grounded, and the first interface is connected to the drive module. The function of the signal input module is to be able to input signals. In this embodiment, the model of the connector RF1 is selected as a radio frequency coaxial connector, and the model is preferably DOSIN - 801 - 0072. The use of other different models of radio frequency coaxial connectors is also within the protection scope of this embodiment.

[0045] As an alternative embodiment, as Figure 2 shown in the figure, the drive module includes a drive chip U2. The DUT module, the voltage stabilizing module, and the signal input module are all connected to the drive chip U2; the gate of the DUT element Q22 in the DUT module is connected to the drive chip U2; the VOUT interface in the voltage stabilizing module is connected to the drive chip U2; the first interface in the signal input module is connected to the drive chip U2.

[0046] Specifically, the drive chip U2 plays a relatively important role in the drive module. The signal input module, the voltage stabilizing module, and the DUT module are all connected to the drive chip U2. It should be noted that the model of the drive chip U2 in this embodiment is 1ED020112FA2.

[0047] As Figure 2 shown in the figure, the drive module further includes a transistor Q19 and a transistor Q20; the base of the transistor Q19 is connected to the CLAMP interface of the drive chip U2, the collector is connected to a 10V power supply, and the emitter is connected to the gate of the DUT element Q22 after a resistor R9 is connected in series; the base of the transistor Q20 is connected to the CLAMP interface of the drive chip U2, the emitter is grounded, and the collector is connected to the gate of the DUT element Q22 after a resistor R10 is connected in series.

[0048] Specifically, the settings of transistor Q19 and transistor Q20 can form a push-pull circuit for controlling the device under test Q22, amplifying the control effect on the gate of the device under test Q22, and ensuring the stability of the test. Moreover, the voltages input to transistor Q19 and transistor Q20 are both 10V, and the voltage received by the gate of the device under test Q22 will be closer to the application scenario in reality, enabling the test results to be more accurate and ensuring the accuracy of the test results.

[0049] A resistor R9 is connected in series between the emitter of transistor Q19 and the gate of the device under test Q22, and a resistor R10 is connected in series between the collector of transistor Q20 and the gate of the device under test Q22. Resistors R9 and R10 can adjust the switching resistance of the gate of the device under test Q22 to observe the influence of the switching resistance on the dynamic characteristics of the device under test. It should be noted that transistor Q19 and transistor Q20 are preferably NPN-type transistors.

[0050] As Figure 2 shown, the drive module further includes a resistor R8, a capacitor C12, and a capacitor C13; one end of the resistor R8 is connected to the OUT interface on the drive chip U2, and the other end is connected to the CLAMP interface on the drive chip U2; one end of the capacitor C12 is grounded, and the other end is connected to a 10V power supply; one end of the capacitor C13 is grounded, and the other end is connected to a 15V power supply.

[0051] The drive module further includes a resistor R6 and a resistor R7; one end of the resistor R6 is connected to the RDY interface of the drive chip U2, and the other end is connected to the VOUT interface of the voltage regulator chip U3; one end of the resistor R7 is connected to the #FLT interface of the drive chip U2, and the other end is connected to the VOUT interface of the voltage regulator chip U3.

[0052] The drive module further includes a capacitor C11; one end of the capacitor C11 is connected to the VOUT interface of the voltage regulator chip U3, and the other end is grounded.

[0053] In addition to the interfaces connected to the signal input module, the voltage regulator module, and the device under test module, the drive chip U2 further includes a #RST interface, a VCC1 interface, a GND1 interface, an IN- interface, a VEE2 interface, a DESAT interface, a GND2 interface, and a VCC2 interface. The #RST interface and the VCC1 interface are connected to the VOUT interface of the voltage regulator chip U3, and the voltage range of the VCC1 interface is 4.5V - 5.5V; the GND1 interface and the IN- interface are grounded together; the VEE2 interface, the DESAT interface, and the GND2 interface are all grounded; the VCC2 interface is connected to a 15V power supply, and the voltage range of the VCC2 interface is 13V - 20V.

[0054] As an alternative embodiment, the test circuit further includes a filtering module. The filtering module includes a switch SW1 and a plurality of capacitors connected in parallel with the switch SW1. One end of the parallel-connected switch SW1 and the plurality of capacitors is grounded, and the other end is connected to VCC. Specifically, the plurality of capacitors in the switch module are respectively capacitor C18, capacitor C17, capacitor C16, and capacitor C15. Capacitor C18, capacitor C17, capacitor C16, capacitor C15, and the switch SW1 are connected in parallel. After being connected in parallel, one end is grounded and the other end is connected to VCC. Connecting a plurality of capacitors in parallel to VCC can not only protect the circuit but also reduce voltage oscillation by means of energy storage. During the test, the switch SW1 disconnects the charging of capacitor C18, capacitor C17, capacitor C16, and capacitor C15, playing a role in filtering and making the bus voltage smoother.

[0055] The test principle of this test circuit is as follows: The voltage regulator chip U3 serves as a voltage regulator. When a 10V voltage is input, a 5V voltage output at its VOUT interface indicates normal operation. At this time, when the RDY interface and the #FLT interface of the driver chip U2 are at a high level, it means there is no open circuit inside the driver chip U2. The VCC1 interface and the VCC2 interface of the driver chip U2 are respectively connected to 5V and 15V to supply power to the driver chip U2 to make it work, and the #RST interface is at a high level to prevent the chip from resetting. When 5V is input at the IN+ interface on the signal input module, the driver chip U2 operates normally, and the OUT interface outputs 15V, turning on the transistors Q19 and Q20. The gate of the device under test Q22 is connected to the 10V power supply through the transistor Q19, and the transistors Q19 and the device under test Q22 conduct. At this time, the device under test Q22 is in the on state. When a low level is input at the IN+ interface of the signal input module, there is no output at OUT, the transistors Q19 and Q20 are in the off state, and the gate of the device under test Q22 is at a low level, and it is in the off state at this time. During the test, the switch SW1 in the filtering module is disconnected, and the capacitors C18, C17, C16, and C15 are charged, playing a role in filtering and making the bus voltage smoother. When SW1 is closed, the capacitors discharge. During the test, closing SW2 is a double-pulse test. At this time, the gate can be controlled to turn on and off through the control module to observe the dynamic characteristics of the device under test, and the reverse recovery current of the device under test Q21 can also be tested through the freewheeling effect of the inductor L2. When the switch SW2 is turned off, it is an EAS (single-pulse avalanche breakdown energy) test, and the avalanche tolerance of the device under test Q22 can be obtained through the inductor L2.

[0056] The embodiment is only a special case and does not indicate that the present utility model has only such an implementation manner.

[0057] The above are only the preferred embodiments of the present utility model. Those skilled in the art will know that without departing from the spirit and scope of the present utility model, various changes or equivalent substitutions can be made to these features and embodiments. Additionally, under the teaching of the present utility model, these features and embodiments can be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present utility model.

Claims

1. A power semiconductor device test circuit, characterized in that, Including: A driving module and a module under test, where the module under test is connected to the driving module; The module under test includes a device under test Q22, a device under test Q21, an inductor L2, and a switch SW2; the gate of the device under test Q22 is connected to the driving module, the source is grounded, and the drain is connected to the inductor L2; the inductor L2 is connected to VCC; the gate and source of the device under test Q21 are short-circuited, and the drain is connected in series with the switch SW2, and after the series connection, the device under test Q21 and the switch SW2 are connected in parallel across both ends of the inductor L2.

2. The test circuit for a power semiconductor device according to claim 1, wherein The driving module includes a driving chip U2; The gate of the device under test Q22 in the module under test is connected to the driving chip U2.

3. The test circuit of a power semiconductor device according to claim 2, characterized in that, The test circuit further includes a voltage regulation module; the voltage regulation module includes a voltage regulation chip U3; the voltage regulation chip U3 includes a VIN interface, an ADJ interface, a TAB interface, and a VOUT interface; The VIN interface is connected to a regulated power supply, the ADJ interface is grounded, the VOUT interface outputs a voltage and is connected to the TAB interface, and the VOUT interface is also connected to the driving chip U2.

4. A power semiconductor device test circuit according to claim 2, characterized in that, The test circuit further includes a signal input module, the signal input module includes a connector RF1, and the connector RF1 includes a first interface, a second interface, a third interface, and a fourth interface; The second interface, the third interface, and the fourth interface are all grounded, and the first interface is connected to the driving chip U2.

5. A power semiconductor device test circuit according to claim 2, characterized in that, The driving module further includes a transistor Q19 and a transistor Q20; The base of the transistor Q19 is connected to the CLAMP interface of the driving chip U2, the collector is connected to a 10V power supply, and the emitter is connected to the gate of the device under test Q22 after a series resistor R9; The base of the transistor Q20 is connected to the CLAMP interface of the driving chip U2, the emitter is grounded, and the collector is connected to the gate of the device under test Q22 after a series resistor R10.

6. The test circuit for a power semiconductor device according to claim 2, characterized in that, The driving module further includes a resistor R8, a capacitor C12, and a capacitor C13; One end of the resistor R8 is connected to the OUT interface on the driving chip U2, and the other end is connected to the CLAMP interface on the driving chip U2; One end of the capacitor C12 is grounded, and the other end is connected to a 10V power supply; One end of the capacitor C13 is grounded, and the other end is connected to a 15V power supply.

7. A power semiconductor device test circuit according to claim 3, characterized in that, The driving module further includes a resistor R6 and a resistor R7; One end of the resistor R6 is connected to the RDY interface of the driving chip U2, and the other end is connected to the VOUT interface of the voltage regulation chip U3; One end of the resistor R7 is connected to the #FLT interface of the driving chip U2, and the other end is connected to the VOUT interface of the voltage regulation chip U3.

8. The test circuit of a power semiconductor device according to claim 3, characterized in that, The driving module further includes a capacitor C11; one end of the capacitor C11 is connected to the VOUT interface of the voltage regulation chip U3, and the other end is grounded.

9. The test circuit for a power semiconductor device according to claim 1, wherein The test circuit further includes a filtering module, the filtering module includes a switch SW1 and a plurality of capacitors connected in parallel with the switch SW1, and after the parallel connection, one end of the switch SW1 and the plurality of capacitors is grounded, and the other end is connected to VCC.

10. A power semiconductor device test circuit according to any one of claims 2 to 9, characterized in that The inductor L2 is an adjustable inductor; the model of the drive chip U2 is 1ED020112FA2.

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