Chip packaging structure and memory

Abstract

The utility model provides a chip packaging structure and a memory, and relates to the field of chips. The chip packaging structure comprises a substrate and a chip stacking module, wherein the chip stacking module comprises N chip stacking layers; the first chip stacking layer comprises a pair of chips, and the pair of chips are arranged on the substrate in parallel; the Nth chip stacking layer comprises chips, and the chips of the Nth chip stacking layer and the chips of the (N-1) th chip stacking layer are in lap joint and fixed; the offset distance of the chip of the Nth chip stacking layer relative to the chip of the (N-1) th chip stacking layer in the first direction is larger than the offset distance of the chip of the (N + 1) th chip stacking layer relative to the chip of the Nth chip stacking layer in the second direction. According to the invention, the width size of the substrate and the thickness of the chip packaging structure can be reduced.

Description

Technical Field

[0001] This application relates to the field of chips, and particularly to a chip packaging structure and a memory. Background Art

[0002] With the progress and development of technology, memory chips show a development trend of gradually decreasing size and gradually increasing capacity. Most of the mass-produced memory chips on the market adopt a single-stack or double-stack method to stack multiple Dies. However, the single-stack method has the problem of a relatively large thickness of the chip packaging structure, and the double-stack method has the problem of a relatively large substrate size. Based on this, how to reduce the thickness of the chip packaging structure and the substrate size simultaneously is a technical problem that urgently needs to be solved in this field. Content of the Utility Model

[0003] In view of this, the purpose of this application is to overcome the deficiencies in the prior art and provide a chip packaging structure and a memory, which can ensure the reduction of the width size of the substrate and the thickness of the chip packaging structure while stacking the same number of chips.

[0004] This application provides the following technical solutions:

[0005] In the first aspect, this application provides a chip packaging structure, which includes a substrate and a chip stacking module. The chip stacking module includes N chip stacking layers. The N chip stacking layers are sequentially stacked on the substrate, satisfying: N is a positive integer and N≥2; the chip stacking layer closest to the substrate is the first chip stacking layer, and the first chip stacking layer includes a pair of chips, and the pair of chips are arranged side by side on the substrate;

[0006] The Nth chip stacking layer includes the chip, and the chip of the Nth chip stacking layer and the chip of the N-1th chip stacking layer are overlapped and fixed;

[0007] Wherein, the chip of the Nth chip stacking layer is offset relative to the chip of the N-1th chip stacking layer in a first direction, and the chip of the N+1th chip stacking layer is offset relative to the chip of the Nth chip stacking layer in a second direction. The first direction and the second direction are opposite, and the offset distance of the chip of the Nth chip stacking layer relative to the chip of the N-1th chip stacking layer in the first direction is greater than the offset distance of the chip of the N+1th chip stacking layer relative to the chip of the Nth chip stacking layer in the second direction.

[0008] In one embodiment of the first aspect, the Nth layer of the chip stack layer further includes a support member, and the support member is clamped between the chip of the (N - 1)th layer of the chip stack layer and the chip of the (N + 1)th layer of the chip stack layer.

[0009] In one embodiment of the first aspect, the chips of adjacent chip stack layers are arranged in parallel.

[0010] In one embodiment of the first aspect, the support member is provided with a gasket, and the gasket is clamped between the chip of the (N - 1)th layer of the chip stack layer and the chip of the (N + 1)th layer of the chip stack layer.

[0011] In one embodiment of the first aspect, the chip of the (N - 1)th layer of the chip stack layer has a solder joint on the side facing away from the substrate, and the solder joint of the chip of the (N - 1)th layer of the chip stack layer is located outside the projection area of the gasket of the Nth layer of the chip stack layer on the chip of the (N - 1)th layer of the chip stack layer.

[0012] In one embodiment of the first aspect, the gasket is formed by a fow layer filled between adjacent chips.

[0013] In one embodiment of the first aspect, the support member is provided as a heat-conducting structure with heat-conducting ability.

[0014] In one embodiment of the first aspect, there is a gap between the support member and the chip of the Nth layer of the chip stack layer;

[0015] There is a gap between a pair of chips of the first layer of the chip stack layer.

[0016] In one embodiment of the first aspect, the chips and the substrate on the same side of the chip stack module are connected in series.

[0017] In a second aspect, the present application further provides a memory, and the memory includes a main board and the chip packaging structure as described in any one of the above embodiments, and the chip packaging structure is disposed on the main board.

[0018] The embodiments of the present application have the following advantages:

[0019] With the chip packaging structure provided by the present application, the chip stacking module starts from the substrate. The first layer contains a pair of chips arranged side by side, and each subsequent layer of chips (i.e., from the second layer to the Nth layer) is connected to the chips of the next layer by means of lapping and fixing. The key lies in that the chips of each layer are offset in the first direction and the second direction parallel to the substrate compared with the next layer, and this offset is staggered, that is, the first direction and the second direction are opposite. More importantly, for each upward layer, the offset distance gradually decreases, forming a gradient offset layout. This makes the chip stacking more compact in the height direction and realizes reduction in the width direction at the same time.

[0020] Therefore, through the staggered offset stacking in the direction away from the substrate, the adjacent chips can be arranged more closely, effectively reducing the total thickness of the chip packaging. Compared with the traditional single-layer direct stacking, the space utilization rate is significantly improved. The offset setting in the horizontal direction enables the width dimension of the substrate to be reduced to a certain extent even in the case of stacking multiple layers of chips, which is particularly important for electronic products pursuing miniaturization and high integration. In addition, the staggered offset layout helps to improve the air flow channels between the stacked chips, which is beneficial to heat dissipation, and this is particularly important for high-power and high-performance chips.

[0021] In addition, the present application also relates to a memory. Since the above chip packaging structure has the above technical effects, the memory including this chip packaging structure should have the same technical effects, which will not be elaborated here.

[0022] In order to make the above objects, features and advantages of the present utility model more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present utility model and should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0024] Figure 1 Shows a schematic structural diagram of the chip packaging structure provided by the embodiments of the present application.

[0025] Main element symbol description:

[0026] 100 - Substrate; 200 - Chip stacking module; 210 - Chip stacking layer; 211 - Chip; 212 - Support; 300 - Bonding wire. Detailed Embodiments

[0027] Embodiments of the present utility model will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation of the present utility model.

[0028] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. On the contrary, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0029] In the present utility model, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. It can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0030] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality of" means two or more unless otherwise clearly and specifically defined.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this template herein are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0032] In the related art, with the progress and development of technology, storage chips show a development trend of gradually decreasing size and gradually increasing capacity. Currently, the most mass-produced storage chips on the market can stack up to 16 layers of Dies. When making 16-layer Dies with large capacity, minimizing the product thickness and the substrate size has become the primary problem to be solved.

[0033] Among them, most of the mass-produced memory chips on the market adopt a single-stack method or a double-stack method to stack multiple Dies. However, the single-stack method has the problem of a relatively large thickness of the chip packaging structure, and the double-stack method has the problem of a relatively large substrate size. That is to say, how to reduce the thickness of the chip packaging structure and the substrate size simultaneously is a technical problem that urgently needs to be solved in this field.

[0034] As Figure 1 shown, to solve the above technical problems, according to the present application, a chip packaging structure is provided. The chip packaging structure includes a substrate 100 and a chip stacking module 200. The chip stacking module 200 includes N chip stacking layers 210. The N chip stacking layers 210 are sequentially stacked on the substrate 100, satisfying: N is a positive integer, and N≥2; the chip stacking layer 210 closest to the substrate 100 is the first chip stacking layer 210, and the first chip stacking layer 210 includes a pair of chips 211, and the pair of chips 211 are arranged side by side on the substrate 100; the Nth chip stacking layer 210 includes a chip 211, and the chip 211 of the Nth chip stacking layer 210 and the chip 211 of the (N - 1)th chip stacking layer 210 are overlapped and fixed;

[0035] Among them, the chip 211 of the Nth chip stacking layer 210 is offset relative to the chip 211 of the (N - 1)th chip stacking layer 210 in a first direction, and the chip 211 of the (N + 1)th chip stacking layer 210 is offset relative to the chip 211 of the Nth chip stacking layer 210 in a second direction. The first direction and the second direction are opposite, and the offset distance of the chip 211 of the Nth chip stacking layer 210 relative to the chip 211 of the (N - 1)th chip stacking layer 210 in the first direction is greater than the offset distance of the chip 211 of the (N + 1)th chip stacking layer 210 relative to the chip 211 of the Nth chip stacking layer 210 in the second direction.

[0036] In this embodiment, starting from the substrate 100, the chip stacking module 200 has a first layer containing a pair of chips 211 arranged side by side, and each subsequent layer of chips 211 (i.e., from the second layer to the Nth layer) is connected to the next layer of chips 211 by an overlapping and fixing method. The key is that each layer of chips 211 is offset relative to the next layer in a first direction and a second direction parallel to the substrate 100, and this offset is staggered, that is, the first direction and the second direction are opposite. More importantly, with each upward layer, the offset distance gradually decreases, forming a gradient offset layout. This makes the chips 211 stacked more compact in the height direction and reduces the size in the width direction at the same time.

[0037] In addition, the key lies in that the chips 211 of each layer are offset in the first direction and the second direction parallel to the substrate 100 compared to the lower layer, and this offset is staggered, that is, the first direction and the second direction are opposite. More importantly, for each upper layer, the offset distance gradually decreases, forming a gradient offset layout. This makes the chips 211 more compact in the height direction during stacking and achieves a reduction in the width direction at the same time.

[0038] Although the specific heat dissipation design is not directly mentioned, the staggered offset stacking method provides more channels for heat dissipation, which helps to dissipate heat, thereby potentially improving the overall performance and reliability. Generally speaking, this chip packaging structure successfully solves the limitations regarding thickness and the size of the substrate 100 in traditional stacking technologies through the ingenious arrangement and offset strategy of the chips 211, providing a new solution for high-performance and high-density memory and other integrated circuit packages.

[0039] Exemplarily, the chip packaging structure provided in this application takes 16 dies as an example; of course, in other embodiments, it can also be 4 dies, 8 dies, and so on.

[0040] Compared with the conventional 16-die stacking, the 16-die stacking completed by using the packaging structure provided in this application stacks the chips 211 with each other, and as much as possible satisfies the reduction of the product thickness and the thickness size of the packaging structure at the same time. That is, on the premise of ensuring the reduction of the size of the substrate 100, it is thinner than the conventional 16-layer stacking thickness, achieving the concept of ultra-thin and small-size design.

[0041] Therefore, through the staggered offset stacking in the direction away from the substrate 100, the adjacent chips 211 can be arranged more closely, effectively reducing the total thickness of the chip 211 packaging. Compared with the traditional single-layer direct stacking, the space utilization rate is significantly improved. The offset setting in the horizontal direction enables the width size of the substrate 100 to be reduced to a certain extent even when multiple layers of chips 211 are stacked, which is particularly important for electronic products pursuing miniaturization and high integration. In addition, the staggered offset layout also helps to improve the air flow channels between the stacked chips 211, which is beneficial for heat dissipation, and this is particularly important for high-power and high-performance chips 211.

[0042] As Figure 1 shown, in some embodiments, the Nth layer chip stacking layer 210 further includes a support member 212, and the support member 212 is clamped between the chips 211 of the (N - 1)th layer chip stacking layer 210 and the chips 211 of the (N + 1)th layer chip stacking layer 210.

[0043] In these embodiments, the support member 212 is located between the (N - 1)-th layer and the (N + 1)-th layer of chips 211, connecting and supporting the chips 211 in the upper and lower layers like the bridge columns of a bridge, effectively preventing the stacked structure from deforming due to external forces or temperature changes, improving the stability of the overall structure, and reducing the risk of interlayer misalignment or fracture.

[0044] It should be noted that in the stacking of multiple chips 211, uneven distribution of pressure and thermal stress on each chip 211 may cause local damage. The support member 212 can serve as a stress buffer to help evenly distribute these forces, protect the chips 211 from damage, and extend their service life. Moreover, since the chips 211 in adjacent layers overlap, the two ends of the chip 211 are respectively a lap joint end and a cantilever end. By arranging the support member 212 at the lower end of the cantilever end to support the cantilever end, the stability of the chip 211 can be ensured.

[0045] If necessary, the support member 212 can be designed to have electrical isolation, which helps to achieve electrical isolation between different chip 211 layers, optimize signal transmission, reduce interference, and improve signal integrity.

[0046] Exemplarily, the two ends of the support member 212 in the direction away from the substrate 100 are in surface contact with the adjacent chips 211 respectively, increasing the contact surface, further improving stability, and reducing damage to the chips 211 by the support member 212. In other words, directly contacting the surfaces of the adjacent chips 211 at the two ends in the direction away from the substrate 100 is intended to provide a more stable support effect by increasing the contact area between the support member 212 and the chips 211. The increased contact surface can more evenly distribute the forces applied to the support member 212, reduce the pressure on any single contact point, and thus reduce the risk of chip 211 damage caused by pressure concentration, ensuring the long-term stability and reliability of the stacked structure.

[0047] Exemplarily, the support member 212 is set as a column; of course, in other embodiments, according to different design requirements and application scenarios, the support member 212 can also be designed into other shapes, such as: plate-shaped, sheet-shaped, grid, frame structure, etc. Or, the support member 212 is made of elastic or flexible materials. The support member 212 made of materials with a certain elasticity can absorb part of the mechanical stress while maintaining support, protecting the chips 211 from external impacts such as vibrations or drops.

[0048] As Figure 1 shown, in some embodiments, the chips 211 in adjacent chip stacking layers 210 are arranged in parallel.

[0049] In these embodiments, the chips 211 of adjacent chip stacking layers 210 are arranged in a parallel manner. Such a design aims to optimize space utilization and ensure structural stability. The parallel arrangement means that the chips 211 in each layer are aligned in the vertical direction, which can maximize the utilization of vertical space, enabling more chips 211 to be stacked without increasing the overall package size, thereby increasing the storage capacity or logic units to meet the requirements of high-performance and high-density integration. Moreover, the parallel stacking structure is relatively simple and intuitive, facilitating precise alignment and fixation during the manufacturing process, reducing complexity and potential alignment errors, and being conducive to improving production efficiency and the yield rate.

[0050] Exemplarily, the chips 211 are stacked on the substrate 100, and the upper surfaces of the chips 211 and the substrate 100 are arranged in parallel.

[0051] As Figure 1 shown, in some embodiments, the support member 212 is provided as a spacer, and the spacer is clamped between the chips 211 of the (N - 1)-th chip stacking layer 210 and the chips 211 of the (N + 1)-th chip stacking layer 210.

[0052] In these embodiments, by designing the support member 212 in the form of a spacer and clamping it between adjacent chip stacking layers 210. The spacer, as an intermediate layer, can effectively prevent direct contact between the chips 211 of the (N - 1)-th layer and the (N + 1)-th layer, reducing the wear or damage that may occur at the edges of the chips 211 due to physical contact and protecting the surface integrity of the chips 211.

[0053] The presence of the spacer can evenly distribute the pressure of the upper chips 211 on the lower chips 211, avoiding damage or deformation of the chips 211 caused by excessive local pressure and improving the overall mechanical stability of the stacking structure. Moreover, according to the selection of the spacer material, the function of heat conduction can be achieved. For example, using a material with high thermal conductivity can promote the effective dissipation of heat and help manage the thermal energy distribution in the chip 211 stack.

[0054] In scenarios where electrical isolation is required, the spacer can act as an insulating layer to prevent electrical signals between different chip 211 layers from interfering with each other and ensure the pure transmission of signals.

[0055] Among them, the thickness and length of the spacer can be flexibly adjusted to adapt to the height requirements of different chip 211 designs or to compensate for tolerances in the manufacturing process, ensuring precise alignment of the stack and appropriate spacing between layers.

[0056] As Figure 1As shown, in some embodiments, the chip 211 of the (N - 1)th layer chip stacking layer 210 has solder joints on the side facing away from the substrate 100, and the solder joints of the chip 211 of the (N - 1)th layer chip stacking layer 210 are located outside the projection area of the spacer of the Nth layer chip stacking layer 210 on the chip 211 of the (N - 1)th layer chip stacking layer 210.

[0057] In these embodiments, the chip 211 stacking structure further optimizes the stacking stability and the reliability of electrical connection by carefully designing the positions of the solder joints of the chip 211. Specifically, the chip 211 of the (N - 1)th layer chip stacking layer 210 is provided with solder joints on the side away from the substrate 100, and these solder joints are specifically arranged within a specific area, that is, to ensure that they are not within the area where the spacer of the Nth layer chip stacking layer 210 projects onto the (N - 1)th layer chip 211.

[0058] By setting the solder joints outside the spacer projection area, such a layout effectively utilizes the edge space of the chip 211, enabling sufficient positions for soldering while maintaining the compactness of the stack, and avoiding wiring or soldering problems caused by space constraints in a highly integrated stacking structure.

[0059] Avoiding the direct area under the spacer can prevent solder overflow or splashing that may occur during the soldering process, which may contaminate or damage the surface of the spacer or the chip 211, maintaining the cleanliness of the interlayer interface and good electrical isolation. Moreover, the spacer can more directly support the upper - layer chip 211 without being restricted by the solder - joint position, enhancing the mechanical strength and stability of the overall stacking structure, especially the ability to resist external force impacts and thermal expansion stresses.

[0060] In some embodiments, the spacer is formed by a FOW layer filled between adjacent chips 211.

[0061] In these embodiments, the innovative design of the spacer is formed by curing a FOW (Film On Wire) layer filled between adjacent chips 211, aiming to further optimize the structure and performance of the chip 211 stack. The introduction of the FOW layer not only serves as an alternative or supplement to the support 212 but may also integrate other functions. For example, the FOW layer not only plays a physical - support role but also integrates insulating, conductive, or thermal - management materials, and is designed as a thin film with specific electrical or thermal - conduction properties according to specific requirements. This design enables the spacer to not only maintain the correct spacing between chips 211 but also play an important role in electrical isolation, signal transmission, or heat - energy distribution.

[0062] Precise filling between chips 211 through FOW technology can ensure that each gap is evenly and tightly sealed, thereby improving the overall uniformity and stability of the stacked structure. This method is particularly suitable for cases where there are slight differences between chips 211 or precise alignment is required, increasing the adaptability and precision of the stacked structure.

[0063] The formation process of the FOW layer involves steps such as fluid curing. Compared with traditional support members 212 that require precise alignment and fixation, the injection filling process of this liquid or semi - liquid material may be more flexible and simple, which is beneficial to improving production efficiency and reducing costs.

[0064] In addition, the FOW layer can bond the chips 211 located at its upper and lower ends, thereby achieving both support and fixation of the chips 211. Thus, subsequent assembly process flows are reduced.

[0065] In some embodiments, the support member 212 is arranged as a heat - conducting structure with heat - conducting ability.

[0066] In these embodiments, the support member 212 has good heat - conduction performance and, as a medium for heat transfer, helps to quickly conduct the heat generated by the upper - layer chips 211, assisting in the thermal management of the entire packaging structure, maintaining good heat - dissipation performance, which is crucial for maintaining the normal operating temperature of the chips 211.

[0067] Exemplarily, the support member 212 is a ceramic part; of course, in other embodiments, the support member 212 can also be made of polymer materials, etc.

[0068] As Figure 1 shown, in some embodiments, there is a gap between the support member 212 and the chip 211 of the N - th layer chip stacking layer 210; there is a gap between a pair of the chips 211 of the first - layer chip stacking layer 210.

[0069] In these embodiments, by providing gaps between the support member 212 and the chip 211 of the N - th layer chip stacking layer 210 and between a pair of chips 211 of the first - layer chip stacking layer 210, the existence of the gaps can promote air circulation or filling with heat - conducting materials, helping heat to conduct from the chips 211 to the support member 212 and then further to the external heat - dissipation system, thereby improving the overall heat - dissipation efficiency, ensuring that the chips 211 maintain an appropriate temperature during operation, and preventing performance degradation or damage caused by overheating.

[0070] Reserving a gap between the chip 211 and the support member 212 or between the chips 211 can serve as a stress buffer zone, reducing stress concentration caused by differences in thermal expansion or mechanical stress, protecting the chips 211 from physical damage, and improving the long - term stability and reliability of the packaging structure.

[0071] In addition, the existence of the gap provides room for adjustment during the assembly process. Due to the errors in the switching of the chip 211, the assembly difficulty and time cost caused by the extremely high requirement for alignment accuracy can be reduced.

[0072] As Figure 1 shown, in some embodiments, the chips 211 and the substrate 100 located on the same side of the chip stack module 200 are in series.

[0073] In these embodiments, a direct electrical connection or signal path is established between the chip 211 and the substrate 100 located on the same side of the stack module through the bonding wire 300. Through direct series connection, the signal path between the chip 211 and the substrate 100 can be simplified, the delay and loss of signal transmission can be reduced, and the data transmission rate and efficiency of the overall system can be improved. By reducing intermediate connectors or wiring layers, the series design can simplify the packaging structure, reduce the assembly complexity, and thus may reduce the material cost and manufacturing cost.

[0074] In some embodiments, the present application also provides a memory, which includes a main board and the chip packaging structure described in any one of the above embodiments, and the chip packaging structure is arranged on the main board.

[0075] In these embodiments, the memory integrates the above innovative chip packaging structure and arranges it on the main board, making full use of the advantages of the packaging structure in reducing the packaging thickness, shrinking the substrate size, improving the thermal management efficiency, and enhancing the structural stability. Since the above chip packaging structure has the above technical effects, the memory including this chip packaging structure should have the same technical effects, which will not be elaborated here.

[0076] When this memory is specifically a flash memory, it is directly related to high-density data storage applications, such as solid-state drives (SSDs), embedded storage modules, etc., and can provide faster read and write speeds, higher storage density, and better energy consumption performance. Of course, in addition to flash memory, the memory can also adopt other forms, including but not limited to:

[0077] Dynamic random access memory (DRAM): Suitable for scenarios that require high-speed, temporary data storage, such as computer memory modules, providing fast data access speeds.

[0078] Static random access memory (SRAM): Compared with DRAM, SRAM is faster but more expensive, and is often used for cache memories, such as L1 and L2 caches in CPUs.

[0079] Hard disk drive (HDD): Traditional rotating disk storage technology, suitable for large-capacity, low-cost storage requirements.

[0080] Solid State Hybrid Drives (SSHDS): Combines the high speed of SSDs and the large capacity of HDDs, and optimizes the data storage location through intelligent algorithms to balance performance and cost.

[0081] Phase Change Memory (PCM): A non-volatile storage technology that uses the phase change of materials to store data, characterized by high speed and a large number of erase / write cycles, and may become part of high-speed storage solutions in the future.

[0082] Magnetoresistive Random-Access Memory (MRAM): Stores information using the resistance change of magnetic tunnel junctions and is suitable for low-power and instant-start applications.

[0083] In all the examples shown and described here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values.

[0084] It should be noted that like reference numerals and letters denote like items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0085] The above-described embodiments merely represent several implementation manners of the present utility model, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation on the scope of the present utility model. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present utility model, several modifications and improvements can still be made, and these all belong to the protection scope of the present utility model.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes a substrate and a chip stacking module. The chip stacking module includes N chip stacking layers. The N chip stacking layers are sequentially stacked on the substrate, satisfying: N is a positive integer and N≥2; the chip stacking layer closest to the substrate is the first chip stacking layer, and the first chip stacking layer includes a pair of chips, and the pair of chips are arranged side by side on the substrate; The Nth chip stacking layer includes the chip, and the chip of the Nth chip stacking layer and the chip of the (N - 1)th chip stacking layer are overlapped and fixed; Wherein, the chip of the Nth chip stacking layer is offset relative to the chip of the (N - 1)th chip stacking layer in the first direction, and the chip of the (N + 1)th chip stacking layer is offset relative to the chip of the Nth chip stacking layer in the second direction. The first direction and the second direction are opposite, and the offset distance of the chip of the Nth chip stacking layer relative to the chip of the (N - 1)th chip stacking layer in the first direction is greater than the offset distance of the chip of the (N + 1)th chip stacking layer relative to the chip of the Nth chip stacking layer in the second direction.

2. The chip packaging structure according to claim 1, wherein The Nth chip stacking layer further includes a support member, and the support member is clamped between the chip of the (N - 1)th chip stacking layer and the chip of the (N + 1)th chip stacking layer.

3. The chip packaging structure according to claim 2, characterized in that, The chips of adjacent chip stacking layers are arranged in parallel.

4. The chip packaging structure according to claim 2, wherein The support member is provided with a gasket, and the gasket is clamped between the chip of the (N - 1)th chip stacking layer and the chip of the (N + 1)th chip stacking layer.

5. The chip packaging structure according to claim 4, characterized in that, The chip of the (N - 1)th chip stacking layer has a solder joint on the side facing away from the substrate, and the solder joint of the chip of the (N - 1)th chip stacking layer is located outside the projection area of the gasket of the Nth chip stacking layer on the chip of the (N - 1)th chip stacking layer.

6. The chip packaging structure according to claim 4, wherein The gasket is formed by fow layers filled between adjacent chips.

7. The chip packaging structure according to claim 2, wherein The support member is set as a heat-conducting structure with heat-conducting ability.

8. The chip packaging structure according to claim 4, wherein There is a gap between the support member of the Nth chip stacking layer and the chip; There is a gap between the pair of chips of the first chip stacking layer.

9. The chip packaging structure according to claim 1, wherein The chips and the substrate on the same side of the chip stacking module are connected in series.

10. A memory, characterized in that, The memory includes a main board and the chip packaging structure according to any one of claims 1 to 9, and the chip packaging structure is arranged on the main board.

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