MOS tube and pin structure thereof

Abstract

The utility model provides an MOS transistor and a pin structure thereof, the pin structure is connected with a PCB substrate and is used for controlling a circuit state, the pin structure further comprises a base body, a plurality of pins are arranged in the base body and partially extend out of the base body, and the plurality of pins are arranged around the base body by a circle; wherein each pin comprises a fixed end and a connecting end, the fixed ends are arranged on the peripheral surface of the base body, and the connecting ends are arranged on one side, close to the PCB substrate, of the base body, so that the height of the pins is reduced. According to the MOS tube and the pin structure thereof provided by the invention, the pin structure is designed to be arranged around the base body by one circle, and the fixing piece and the connecting end of the pin are respectively arranged on the peripheral surface of the base body and one side close to the PCB substrate, so that the height of the pin can be obviously reduced, and the overall height of packaging is reduced. Therefore, the space can be effectively saved in a compact design, the plurality of pins are arranged around the base body, the peripheral space of the base body can be utilized more efficiently, the occupied area of packaging is reduced, and the space utilization rate is improved.

Description

Technical Field

[0001] This application relates to the technical field of electronic components, and particularly to a MOS transistor and its pin structure. Background Art

[0002] MOS transistor packaging is a common semiconductor device packaging technology used to protect and connect the MOS transistor chip to the circuit board. A MOS transistor typically consists of a gate, a drain, and a source. Through packaging technology, these functional regions are wrapped together, and an appropriate pin structure is provided to achieve circuit connection and mechanical support. MOS transistor packaging aims to optimize the physical protection, thermal management capabilities, and electrical performance of the device to meet the requirements of various electronic device designs.

[0003] In the semiconductor industry, traditional MOS transistor packaging solutions include common forms such as TO-220, TO-92, and SOI C. These packaging forms achieve the connection between the device and the circuit board through exposed pins and provide mechanical support and heat dissipation functions. However, traditional packaging has more pins and a larger volume, with certain limitations in space utilization. Especially for high-power applications or compactly designed electronic devices, these packaging forms may not effectively meet the requirements of modern products. Summary of the Utility Model

[0004] In view of this, it is necessary to provide a pin structure that can reduce the packaging volume of the MOS transistor to solve the above problems.

[0005] An embodiment of this application provides a pin structure of a MOS transistor, which is connected to a PCB substrate and used to control the circuit state. The pin structure further includes:

[0006] A substrate;

[0007] Pins, a plurality of the pins are arranged in the substrate and partially extend out of the substrate. The plurality of pins are arranged around the substrate in a circle.

[0008] Among them, each pin includes a fixed end and a connection end. The fixed end is arranged on the peripheral surface of the substrate, and the connection end is arranged on the side of the substrate close to the PCB substrate to reduce the pin height.

[0009] In at least one embodiment of this application, when observing along a plane perpendicular to the side of the substrate close to the PCB substrate, the pins include a first source electrode, a drain electrode, a gate electrode, and a second source electrode that are arranged on the substrate in a clockwise order.

[0010] In at least one embodiment of this application, the first source electrode and the gate electrode are respectively arranged on opposite side surfaces of the substrate to prevent hot spot aggregation.

[0011] In at least one embodiment of the present application, each of the fixed ends is completely embedded in the substrate. Along the vertical direction, the height from the side of the substrate close to the PCB board to the connection end is defined as a, where 0.01 mm ≤ a ≤ 0.05 mm.

[0012] In at least one embodiment of the present application, the width of the connection end is defined as b, where 0.2 mm ≤ b ≤ 0.3 mm.

[0013] In at least one embodiment of the present application, the gap between two adjacent pins is defined as c, where 0.4 mm ≤ c ≤ 0.5 mm.

[0014] In at least one embodiment of the present application, the pin further includes a fixing portion, a connecting portion, and an arc portion. The fixing portion is embedded in the side of the substrate close to the PCB substrate and partially protrudes from the substrate;

[0015] The connecting portion is parallel to the surface of the substrate close to the pin and is fixedly connected to the PCB substrate. The arc portion is disposed between the connecting portion and the fixing portion.

[0016] In at least one embodiment of the present application, the pin further includes a thickening layer, and the thickening layer is disposed on the side of the fixing portion and the arc portion away from the substrate.

[0017] In at least one embodiment of the present application, the pin further includes an insulating layer, and the insulating layer is attached to the side of the thickening layer facing away from the substrate for improving electrical isolation.

[0018] A MOS transistor includes the pin structure of a MOS transistor as described above.

[0019] By designing the pin structure to be arranged around the substrate in a circle and disposing the fixing member and the connection end of the pin on the circumferential surface of the substrate and the side close to the PCB substrate respectively, the MOS transistor and its pin structure provided above can significantly reduce the pin height, thereby reducing the overall height of the package. This can effectively save space in a compact design and increase the integration degree of electronic devices. The multiple pins are arranged around the substrate in a circle, which can more efficiently utilize the peripheral space of the substrate, reduce the occupied area of the package, and improve the space utilization rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a perspective view of the pin structure of a MOS transistor in an embodiment of the present application.

[0021] Figure 2 is Figure 1 another perspective view of the pin structure of the MOS transistor as described above.

[0022] Figure 3 isFigure 1 The front view of the pin structure of a MOS transistor as described above.

[0023] Figure 4 is Figure 1 The enlarged side view of the pin structure of a MOS transistor as described above.

[0024] Figure 5 is Figure 1 The schematic diagram of the pins of the pin structure of a MOS transistor as described above.

[0025] Description of main component symbols

[0026] 100. The pin structure of a MOS transistor; 10. Substrate; 20. Pins; 21. Fixed end; 22. Connection end; 23. First source; 24. Drain; 25. Gate; 26. Second source; 27. Fixed part; 28. Connection part; 29. Arc surface part; 30. Thickened layer; 40. Insulating layer. Specific embodiments

[0027] Next, the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0028] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be an intermediate component at the same time. When a component is considered to be "provided on" another component, it can be directly provided on the other component or there may be an intermediate component at the same time. The terms "top", "bottom", "upper", "lower", "left", "right", "front", "rear", and similar expressions used herein are only for the purpose of illustration.

[0029] The embodiments of the present application provide a pin structure of a MOS transistor, which is connected to a PCB substrate and is used to control the circuit state. The pin structure further includes:

[0030] Substrate;

[0031] Pins, a plurality of the pins are provided in the substrate and partially extend out of the substrate, and the plurality of pins are arranged around the substrate for one week;

[0032] Among them, the pin includes a fixed end and a connection end. The fixed end is provided on the peripheral surface of the substrate, and the connection end is provided on one side of the substrate close to the PCB substrate to reduce the pin height.

[0033] A MOS transistor and its pin structure provided above can significantly reduce the pin height and thus the overall height of the package by designing the pin structure to surround the substrate in a circle and arranging the fixing parts and connection ends of the pins on the circumferential surface of the substrate and on the side close to the PCB substrate, respectively. This can effectively save space in a compact design and increase the integration of electronic devices. Multiple pins are arranged around the substrate in a circle, which can make more efficient use of the peripheral space of the substrate, reduce the occupied area of the package, and improve the space utilization rate.

[0034] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0035] Please refer to Figures 1-5 , an embodiment of the present application provides a pin structure 100 of a MOS transistor, which is connected to a PCB substrate and is used to control the circuit state. The pin 20 structure further includes:

[0036] A substrate 10;

[0037] Pins 20, a plurality of the pins 20 are arranged in the substrate 10 and partially protrude from the substrate 10, and the plurality of pins 20 are arranged around the substrate 10 in a circle;

[0038] Wherein, the pin 20 includes a fixed end 21 and a connection end 22. The fixed end 21 is arranged on the circumferential surface of the substrate 10, and the connection end 22 is arranged on the side of the substrate 10 close to the PCB substrate to reduce the height of the pin 20.

[0039] Specifically, the substrate 10 serves as a support and fixing structure for the pins 20 to ensure the stable position of the pins 20. Through the fixing function of the substrate 10, the pins 20 can be maintained in a specific position and arrangement, preventing the pins 20 from moving or deforming during assembly or use. The pins 20 are the electrical connection parts between the MOS transistor and the PCB substrate, responsible for transmitting electrical signals to the PCB substrate. The existence of the pins 20 enables the MOS transistor to achieve electrical connection with the circuit board, transmit control signals or power signals, and ensure the normal operation of the circuit.

[0040] Furthermore, part of the pin 20 is embedded in the substrate 10, and the other part protrudes from the substrate 10, which is convenient for connection with the PCB substrate. This structural design enhances the mechanical strength of the pin 20, prevents the pin 20 from bending or breaking during the welding process, and at the same time ensures good contact between the pin 20 and the PCB board. And the pins 20 are arranged around the substrate 10 in a circle, providing a symmetric and compact connection method. The circumferential layout increases the number and layout density of the pins 20, improves the reliability and stability of the electrical connection, and at the same time reduces the occupied space of the package.

[0041] Furthermore, the fixed end 21 is used to fix the position of the pin 20, and the connection end 22 is used to connect to the PCB substrate. The design of separating the fixed end 21 and the connection end 22 makes the pin 20 more stable during soldering and assembly, avoiding loosening or breaking of the pin 20 caused by uneven stress. The fixed end 21 is embedded in the circumferential surface of the base body 10 to ensure that the position of the pin 20 remains fixed. The mechanical strength and stability of the pin 20 are improved, preventing the pin 20 from falling off or loosening during use.

[0042] Furthermore, the connection end 22 is located on the side of the base body 10 close to the PCB substrate, facilitating electrical connection with the PCB substrate. The height of the pin 20 is reduced, improving the overall compactness of the package and the low-profile design, which is suitable for electronic products that require a thin and light design. The reduction in the height of the pin 20 reduces the overall thickness of the package. The adaptability of the package is improved, especially in electronic products that require an ultra-thin design, such as smart watches and mobile phones.

[0043] In a specific embodiment, the size of the base body 10 is 2mm × 2mm, which helps to miniaturize the overall design and is suitable for compact electronic products. Due to the advantages of miniaturization and ultra-thin design of the pin 20 and the base body 10 structure, it is very suitable for use in mobile devices such as mobile phones and tablet computers, saving internal space and improving the thinness and lightness of the whole machine. In wearable devices such as smart watches and fitness trackers, the pin 20 structure can provide a compact and reliable electrical connection, meeting the design requirements of miniaturization and high integration.

[0044] In a specific embodiment, when observing along a plane perpendicular to the side of the base body 10 close to the PCB substrate, the pin 20 includes a first source electrode 23, a drain electrode 24, a gate electrode 25, and a second source electrode 26 that are sequentially arranged on the base body 10 in a clockwise direction.

[0045] Specifically, the first source electrode 23 is a source electrode of a MOS transistor, which leads out current and is connected to an external circuit through a pad on the PCB. The drain electrode 24 is the main current outlet of the MOS transistor and is connected to a load. It leads out the current flowing from the source electrode and is connected to a pad on the PCB. The gate electrode 25 is a control terminal for controlling the on / off state of the MOS transistor, and controls the conduction or cutoff state between the source electrode and the drain electrode 24 through a voltage signal. The second source electrode 26 is a pin 20 with the same function as the first source electrode 23, further providing a current path.

[0046] Furthermore, the drain 24 usually needs to handle a relatively large current, so it is very important to ensure effective heat dissipation and reliable connection of the drain 24 in the layout. Designing the drain 24 in the middle of the pin 20 structure helps to balance the current and heat dissipation requirements. The control signal of the gate 25 requires low capacitance and low resistance to ensure fast switching speed and high efficiency. The position of the gate 25 is designed between the source and the drain 24, which can reduce the parasitic capacitance and improve the switching performance. Acting together with the first source 23, it can evenly distribute the current, reduce the resistance and heat accumulation, and improve the overall performance. The two-source design can provide a better current dispersion effect and improve the reliability and lifespan of the MOS transistor.

[0047] In a specific embodiment, the first source 23 and the gate 25 are respectively arranged on opposite side surfaces of the substrate 10 to prevent hot spot aggregation.

[0048] Specifically, the first source 23 is designed on one side surface of the substrate 10 so that the source current can be evenly distributed when passing through the substrate 10.

[0049] Beneficial effects: This design helps to dissipate heat evenly and prevent local overheating. By dispersing the path of the source current, the local current density is reduced, and the formation of hot spots is avoided. The gate 25 is designed on the side surface opposite to the first source 23, and the control signal of the gate 25 is input into the MOS transistor through this side surface. Separating the gate 25 from the source not only helps to reduce the parasitic capacitance and improve the switching speed, but also avoids direct heat conduction between the gate 25 and the source, further preventing hot spot aggregation.

[0050] In a specific embodiment, each fixed end 21 is completely embedded in the substrate 10, and the height from the side of the substrate 10 close to the PCB board to the connection end 22 is defined as a in the vertical direction, where 0.01 mm ≤ a ≤ 0.05 mm.

[0051] Specifically, the height from the side of the substrate 10 close to the PCB board to the connection end 22 is a, that is, the height of the pin 20 protruding from the substrate 10 is a. The semiconductor chip is in direct contact with the PCB board, reducing the thermal stress at the solder joint interface. Improving the welding strength and reliability, ensuring the stability of long-term use. The bottom pins 20 of the package are in direct contact with the PCB board. Improving the heat conduction efficiency, better dissipating heat, and facilitating electromagnetic shielding treatment on the PCB board. Effectively isolating external electromagnetic interference and enhancing the anti-interference ability of the circuit.

[0052] Furthermore, this design helps to reduce the overall height of pin 20, making the entire device more thin - type and suitable for electronic products that require high integration and ultra - thin design. The lower height of pin 20 can also reduce warping during soldering, improving the accuracy and reliability of soldering. At the same time, reducing the height of pin 20 can reduce parasitic inductance and parasitic capacitance, improving the high - frequency performance and signal integrity of the circuit.

[0053] In a specific embodiment, the width of the connection end 22 is defined as b, where 0.2 mm ≤ b ≤ 0.3 mm.

[0054] Specifically, while maintaining the miniaturization of the overall component, the connection end 22 of pin 20 with an appropriate width can provide sufficient conductive area to ensure stable current transmission and reduce resistance. The connection end 22 of pin 20 with a width between 0.2 mm and 0.3 mm can provide sufficient mechanical strength, reducing the risk of deformation or fracture of pin 20 during soldering and use. The wider connection end 22 of pin 20 provides a larger soldering area, helping to evenly distribute the solder paste during the soldering process and improving the strength and reliability of the solder joint. This width range ensures that pin 20 has both sufficient conductive performance and good mechanical strength while maintaining the miniaturization of the overall component.

[0055] In a specific embodiment, the gap between two adjacent pins 20 is defined as c, where 0.4 mm ≤ c ≤ 0.5 mm.

[0056] Specifically, an appropriate gap can effectively prevent short - circuit between adjacent pins 20, ensuring the safe operation of the circuit. The gap can reduce parasitic capacitance and parasitic inductance, improving the high - frequency characteristics and signal integrity of the circuit. It also helps to disperse and dissipate heat, preventing local overheating. And a sufficient gap can reduce the mechanical stress between pins 20, preventing deformation or fracture of pins 20 during soldering and use. While ensuring performance, reducing the gap allows pins 20 to be arranged in a smaller space, suitable for compact package designs and ensuring the miniaturization of the overall component.

[0057] In a specific embodiment, pin 20 further includes a fixing portion 27, a connecting portion 28, and an arc - shaped portion 29. The fixing portion 27 is embedded in the side of the base 10 close to the PCB substrate and partially protrudes from the base 10;

[0058] The connecting portion 28 is parallel to the surface of the base 10 close to pin 20 and is fixedly connected to the PCB substrate. The arc - shaped portion 29 is disposed between the connecting portion 28 and the fixing portion 27.

[0059] Specifically, the design of the fixing portion 27 ensures that the pin 20 maintains a stable position during installation and use, preventing displacement or loosening of the pin 20 due to mechanical vibration or external forces. The fixing portion 27 is embedded in the base body 10, which helps to ensure the accurate alignment of the pin 20 with the PCB board during welding, improving the reliability and precision of welding. The design of the fixing portion 27 can disperse the mechanical stress between the pin 20 and the base body 10, reducing the risk of damage to the pin 20 in the stress concentration area, thereby extending the service life of the component.

[0060] Furthermore, the connecting portion 28 is parallel to the surface of the base body 10 close to the pin 20 and is fixedly connected to the PCB substrate. The parallel design of the connecting portion 28 and its fixed connection to the PCB board ensure a stable electrical connection between the pin 20 and the circuit board, reducing the connection impedance and signal transmission loss. The connecting portion 28 is distributed on one side of the pin 20 close to the base body 10, providing additional mechanical support and enhancing the stability of the pin 20 under vibration or mechanical shock.

[0061] Still further, the arc-shaped surface portion 29 is located between the connecting portion 28 and the fixing portion 27 and is mainly designed as a transition area for the pin 20 to smooth the transition between the connecting surface of the pin 20 and the base body 10, removing sharp edges and angles. Sharp edges are likely to cause stress concentration, increasing the risk of damage to the pin 20 under external forces. The design of the arc-shaped surface portion 29 effectively reduces this stress concentration phenomenon, improving the durability and reliability of the pin 20. Removing sharp edges can reduce defects such as solder bridging and solder joint cracking during the welding process, improving the reliability and consistency of welding. The smooth surface of the pin 20 can reduce the parasitic inductance and parasitic capacitance when the current flows through, improving the electrical performance, especially in high-frequency applications. Removing sharp edges and surface defects can improve the electrical contact reliability between the pin 20 and the pad, reducing the contact resistance.

[0062] In a specific embodiment, the pin 20 further includes a thickening layer 30, and the thickening layer 30 is provided on the sides of the fixing portion 27 and the arc-shaped surface portion 29 away from the base body 10.

[0063] Specifically, local thickening can increase the conductive cross-sectional area of the pin 20, reduce the resistance, thereby reducing the power loss and voltage drop, and improving the overall electrical performance. Increasing the metal thickness of the pin 20 can enhance its current-carrying capacity, adapt to high-power applications, and ensure the stable operation of the circuit. Local thickening can enhance the mechanical strength of the pin 20, reduce the risk of bending or breaking, and improve the durability of the device. The thickening treatment can smooth sharp edges and irregular surfaces, reducing stress concentration points, thereby improving the anti-mechanical stress ability of the pin 20.

[0064] Furthermore, increasing the metal thickness can improve the soldering performance of the pin 20, ensure the formation of a firm solder joint during the soldering process, and reduce soldering defects such as cold soldering or dry soldering. The thickened pin 20 provides a larger soldering contact area, improving the wettability of the solder and the reliability of the solder joint. The locally thickened metal layer can provide better anti-corrosion protection and extend the service life of the pin 20 in a harsh environment.

[0065] Further increasing the metal thickness can effectively reduce the risk of surface oxidation of the pin 20, ensuring long-term stable electrical performance. It can also conduct and dissipate heat more effectively, improving the heat dissipation performance of the pin 20 and ensuring the stability of the device in a high-temperature environment. For high-frequency applications, local thickening can reduce the parasitic inductance and parasitic capacitance of the pin 20, optimize the signal transmission path, and improve signal integrity and transmission speed.

[0066] In a specific embodiment, the pin 20 further includes an insulating layer 40, which is attached to the side of the thickened layer 30 facing away from the substrate 10 for improving electrical isolation.

[0067] Specifically, the insulating layer is located on the side of the thickened layer 30 of the pin 20 facing away from the substrate 10. Its main function is to provide effective electrical isolation between the pin 20 and other components (such as a PCB board or other pins 20). This is a key factor in preventing short circuits or electrical interference between different signal lines or voltages in the circuit.

[0068] Furthermore, the insulating layer 40 can effectively prevent possible short-circuit phenomena in the circuit, especially in high-voltage or high-frequency circuits, ensuring the safety of the device and users. By providing good electrical isolation, the insulating layer 40 helps maintain the purity and stability of the signal, reduces signal distortion or attenuation, and improves the performance and reliability of the circuit. The insulating layer 40 can effectively isolate the contact between the pin 20 and the external environment, preventing the performance degradation or damage of the pin 20 caused by moisture, chemical substances, or other environmental factors.

[0069] A MOS transistor includes all the features of the pin structure 100 of a MOS transistor described above. Therefore, the above-mentioned embodiment includes all the beneficial effects of the above-mentioned embodiments.

[0070] This compact layout of the pin 20, combined with the design of leading out the bottom pins 20, provides good heat dissipation performance and reliability. The design of leading out the bottom pins 20 enables the semiconductor chip to be in direct contact with the PCB board, which can improve the soldering strength and reliability. Compared with the traditional pin 20 structure, the design of leading out the bottom pins 20 can reduce the thermal stress at the solder joint interface, thereby improving the long-term reliability of soldering.

[0071] Since the semiconductor chip has its pins led out from pin 20 at the bottom, the lead length can be greatly reduced during wiring and connection, thereby reducing the parasitic inductance and parasitic capacitance. This helps to improve the high-frequency characteristics and signal integrity of the circuit. Moreover, with the design of leading out the pins at the bottom from pin 20, electromagnetic shielding treatment can be conveniently carried out on the PCB board. This can effectively isolate external electromagnetic interference and enhance the anti-interference ability of the circuit. Since it is in direct contact with the PCB board, the heat of the MOS transistor can be better conducted and dissipated through the PCB board. This heat conduction mode is more efficient than traditional packaging. Because the lead length is short, the on-resistance of the MOS transistor is relatively lower. This can improve the conduction efficiency of the circuit and reduce power consumption.

[0072] The design of leading out the bottom pins from pin 20 has many advantages such as facilitating heat dissipation, improving welding reliability, reducing parasitic parameters, enhancing electromagnetic shielding, improving heat conduction performance, and reducing on-resistance. These characteristics give this application unique advantages in the design of small electronic products.

[0073] The above are only the implementation manners of this application. It should be noted here that for those of ordinary skill in the art, improvements can be made without departing from the creative concept of this application, but these all fall within the protection scope of this application.

Claims

1. A pin structure of a MOS transistor, connected to a PCB substrate and used to control the circuit state, is characterized in that The pin structure further includes: a substrate; pins, a plurality of the pins are disposed in the substrate and partially protrude from the substrate, and the plurality of pins are arranged around the substrate in a circle; wherein, each of the pins includes a fixed end and a connection end, the fixed end is disposed on the circumferential surface of the substrate, and the connection end is disposed on a side of the substrate close to the PCB substrate to reduce the height of the pin.

2. The pin structure of a MOS transistor according to claim 1, wherein When observing along a direction perpendicular to the surface of the substrate close to the PCB substrate, the pins include a first source electrode, a drain electrode, a gate electrode, and a second source electrode that are sequentially disposed on the substrate in a clockwise direction.

3. The pin structure of a MOS transistor according to claim 2, characterized in that, The first source electrode and the gate electrode are respectively disposed on opposite side surfaces of the substrate to prevent hot spot aggregation.

4. The pin structure of a MOS transistor according to claim 1, characterized in that Each of the fixed ends is completely embedded in the substrate, and the height from the side of the substrate close to the PCB board to the connection end is defined as a in the vertical direction, and 0.01 mm ≤ a ≤ 0.05 mm.

5. The pin structure of a MOS transistor according to claim 1, characterized in that, The width of the connection end is defined as b, and 0.2 mm ≤ b ≤ 0.3 mm.

6. The pin structure of a MOS transistor according to claim 1, characterized in that, The gap between two adjacent pins is defined as c, and 0.4 mm ≤ c ≤ 0.5 mm.

7. The pin structure of a MOS transistor according to claim 1, characterized in that, The pin further includes a fixing portion, a connecting portion, and an arc surface portion. The fixing portion is embedded in the side of the substrate close to the PCB substrate and partially protrudes from the substrate; the connecting portion is parallel to the surface of the substrate close to the pin and is fixedly connected to the PCB substrate, and the arc surface portion is disposed between the connecting portion and the fixing portion.

8. The pin structure of a MOS transistor according to claim 7, characterized in that, The pin further includes a thickening layer, and the thickening layer is disposed on a side of the fixing portion and the arc surface portion away from the substrate.

9. The pin structure of a MOS transistor according to claim 8, wherein The pin further includes an insulating layer, and the insulating layer is attached to a side of the thickening layer away from the substrate to improve electrical isolation.

10. A MOS transistor, characterized in that, It includes a pin structure of a MOS transistor as described in any one of the above claims 1-9.

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