Power amplifier

Abstract

The utility model provides a power amplifier. The power amplifier comprises an adaptive bias circuit, an input matching balun, a primary driving amplifier, a power divider, a first secondary driving amplifier, a second secondary driving amplifier, a first inter-stage matching network, a second inter-stage matching network, a first power stage amplifier, a second power stage amplifier and a power combiner. The high output power of the power amplifier is realized by synthesizing the two paths of amplified differential signals through the power combiner, and the variable capacitance tube is added in the driving amplifier to compensate the non-linear change of the input capacitance of the transistor, so that the linearity of the circuit is improved; furthermore, a direct-current bias signal corresponding to the radio-frequency signal is output through the self-adaptive bias circuit to dynamically adjust the power-stage amplifier, so that the power amplifier has a gain complementary effect, the linearity of the power amplifier circuit is improved, and the power amplifier has high-power and high-linearity radio-frequency signal output.

Description

Technical Field

[0001] The present disclosure relates to the technical field of millimeter-wave integrated circuits, and particularly to a power amplifier. Background Art

[0002] The 5G millimeter-wave band has significant advantages of large bandwidth, high capacity, and low latency, and can achieve extremely high data transmission rates and stronger stability. Among them, the power amplifier, as one of the core components in the transceiver system, plays a decisive role in the performance of the transmitter. The magnitude of the transmitted power directly determines the communication distance, and its linearity is related to whether the information can be accurately transmitted. Therefore, it is crucial to implement a high-power and high-linearity power amplifier that meets the requirements. Summary of the Utility Model

[0003] The purpose of the embodiments of the present disclosure is to provide a power amplifier to solve the problems of insufficient power and low linearity existing in the existing power amplifiers.

[0004] The embodiments of the present disclosure adopt the following technical solutions: A power amplifier includes:

[0005] An adaptive bias circuit, an input matching balun, a primary driver amplifier, a power divider, a first secondary driver amplifier, a second secondary driver amplifier, a first inter-stage matching network, a second inter-stage matching network, a first power stage amplifier, a second power stage amplifier, and a power combiner; wherein,

[0006] The input end of the adaptive bias circuit inputs a radio frequency signal to be amplified, and converts the radio frequency signal into a DC bias signal for output;

[0007] The single-ended input end of the input matching balun inputs a radio frequency signal to be amplified, and converts the radio frequency signal into a differential signal for output from the differential output end;

[0008] The differential input end of the primary driver amplifier is connected to the differential output end of the input matching balun to receive the differential signal, and amplifies the differential signal to form a primary amplified differential signal, which is then output from the differential output end of the primary driver amplifier;

[0009] The differential input end of the power divider is connected to the differential output end of the primary driver amplifier to receive the primary amplified differential signal, and evenly divides the primary amplified differential signal into a first amplified differential signal and a second amplified differential signal. The first amplified differential signal is output from the first differential output end of the power divider, and the second amplified differential signal is output from the second differential output end of the power divider;

[0010] The differential input terminal of the first secondary driver amplifier is connected to the first differential output terminal of the power divider to receive the first amplified differential signal, and after amplifying the first amplified differential signal to form a first secondary amplified differential signal, it is output from the differential output terminal of the first secondary driver amplifier;

[0011] The differential input terminal of the second secondary driver amplifier is connected to the second differential output terminal of the power divider to receive the second amplified differential signal, and after amplifying the second amplified differential signal to form a second secondary amplified differential signal, it is output from the differential output terminal of the second secondary driver amplifier;

[0012] The differential input terminal of the first inter-stage matching network is connected to the differential output terminal of the first secondary driver amplifier, and the first secondary amplified differential signal passes through the first inter-stage matching network and is output from the differential output terminal of the first inter-stage matching network;

[0013] The differential input terminal of the second inter-stage matching network is connected to the differential output terminal of the second secondary driver amplifier, and the second secondary amplified differential signal passes through the second inter-stage matching network and is output from the differential output terminal of the second inter-stage matching network;

[0014] The differential input terminal of the first power stage amplifier is connected to the differential output terminal of the first inter-stage matching network to receive the first secondary amplified differential signal, the bias signal input terminal of the first power stage amplifier is connected to the output terminal of the adaptive bias circuit to receive the DC bias signal, and after amplifying the first secondary amplified differential signal under the action of the DC bias signal to form a first power amplified differential signal, it is output from the differential output terminal of the first power stage amplifier;

[0015] The differential input terminal of the second power stage amplifier is connected to the differential output terminal of the second inter-stage matching network to receive the second secondary amplified differential signal, the bias signal input terminal of the second power stage amplifier is connected to the output terminal of the adaptive bias circuit to receive the DC bias signal, and after amplifying the second secondary amplified differential signal under the action of the DC bias signal to form a second power amplified differential signal, it is output from the differential output terminal of the second power stage amplifier;

[0016] The first differential input terminal of the power combiner is connected to the differential output terminal of the first power stage amplifier to receive the first power amplified differential signal, and the second differential input terminal of the power combiner is connected to the differential output terminal of the second power stage amplifier to receive the second power amplified differential signal. The power combiner combines the first power amplified differential signal and the second power amplified differential signal to form a radio frequency amplified signal, and outputs the signal from the single-ended output terminal of the power combiner.

[0017] The beneficial effects of the embodiments of the present disclosure are as follows: The power combiner is used to combine two amplified differential signals to achieve a high output power of the power amplifier, and a variable capacitor tube is added to the drive amplifier to compensate for the non-linear change of the input capacitance of the transistor, thereby improving the circuit linearity. Further, the adaptive bias circuit outputs a DC bias signal corresponding to the radio frequency signal to dynamically adjust the power stage amplifier, so that the power amplifier has a gain complementary effect, completing the improvement of the linearity of the power amplifier circuit, and enabling the power amplifier to output a radio frequency signal with high power and high linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in one or more embodiments of the present specification or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 is a circuit schematic diagram of the power amplifier in this embodiment;

[0020] Figure 2 is a circuit structure schematic diagram of the adaptive bias circuit in this embodiment;

[0021] Figure 3 is a circuit structure schematic diagram of the input matching balun in this embodiment;

[0022] Figure 4 is a circuit structure schematic diagram of the primary drive amplifier in this embodiment;

[0023] Figure 5 is a simulation schematic diagram of the influence of adding a variable capacitor tube to the circuit in the primary drive amplifier in this embodiment;

[0024] Figure 6 is a circuit structure schematic diagram of the power splitter in this embodiment;

[0025] Figure 7 is a circuit structure schematic diagram of the first secondary drive amplifier in this embodiment;

[0026] Figure 8 This is a schematic diagram of the circuit structure of the second-stage driver amplifier in this embodiment;

[0027] Figure 9 (a) This is a schematic diagram of the circuit structure of the first inter-stage matching network in this embodiment;

[0028] Figure 9 (b) This is a schematic diagram of the circuit structure of the second inter-stage matching network in this embodiment;

[0029] Figure 10 This is a schematic diagram of the circuit structure of the first power stage amplifier in this embodiment;

[0030] Figure 11 This is a schematic diagram of the circuit structure of the second power stage amplifier in this embodiment;

[0031] Figure 12 This is a schematic diagram of the relationship between the input power and the gain of the main transistor and the auxiliary transistor in this embodiment;

[0032] Figure 13 This is a schematic diagram of the circuit structure of the power combiner in this embodiment;

[0033] Figure 14 This is a schematic diagram of the overall circuit structure of the power amplifier in this embodiment. Detailed implementation manners

[0034] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will clearly and completely describe the technical solutions in one or more embodiments of this specification with reference to the accompanying drawings in one or more embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this document.

[0035] The 5G millimeter-wave frequency band has significant advantages of large bandwidth, high capacity, and low latency, and can achieve extremely high data transmission rates and stronger stability. Among them, the power amplifier, as one of the core components in the transceiver system, plays a decisive role in the performance of the transmitter. The magnitude of the transmitted power directly determines the communication distance, and its linearity is related to whether the information can be accurately transmitted. Therefore, it is crucial to implement a high-power and high-linearity power amplifier that meets the requirements.

[0036] To solve the above problems, the embodiments of the present disclosure provide a power amplifier with high output power and high linearity, and its circuit schematic diagram is as shown in Figure 1As shown, it is a three-stage amplification and two-way synthesis structure, mainly including: an adaptive bias circuit 10, an input matching balun 20, a primary drive amplifier 30, a power divider 40, a first secondary drive amplifier 51, a second secondary drive amplifier 52, a first inter-stage matching network 61, a second inter-stage matching network 62, a first power stage amplifier 71, a second power stage amplifier 72, and a power combiner 80. The radio frequency signal RF to be amplified is respectively input to the adaptive bias circuit 10 and the input matching balun 20, and after being amplified by the subsequent circuits and combined by the power combiner 80, a radio frequency amplified signal RF' is output. The following combines Figures 1 to 14 to describe the power amplifier of this embodiment in detail.

[0037] The input end of the adaptive bias circuit 10 inputs the radio frequency signal RF to be amplified, and converts the radio frequency signal RF into a DC bias signal V b output. This DC bias signal V b is mainly used for the gain complementarity of the first power stage amplifier 71 and the second power stage amplifier 72, and its specific complementarity principle will be described in the parts of the first power stage amplifier 71 and the second power stage amplifier 72. Figure 2 shows the circuit structure schematic diagram of the adaptive bias circuit 10 in this embodiment. It mainly includes an envelope detection circuit centered on the transistor M B1 and a voltage amplification circuit centered on the transistor M B2 . And the output end of the voltage amplification circuit (i.e., the drain of the transistor M B2 ) is used as the output end of the adaptive bias circuit 10 to realize the change of the voltage value of the DC bias signal V b with the change of the input radio frequency signal RF. It should be noted that Figure 2 the circuit structure of the adaptive bias circuit 10 shown is only a preferred implementation manner. In fact, other circuits that can play the same role can also be selected for implementation, and this embodiment does not make specific restrictions.

[0038] The input matching balun (balun, balanced to unbalanced, converter) 20 is mainly used to convert the single-ended radio frequency signal RF into a differential signal. Its single-ended input end accesses the radio frequency signal RF to be amplified, and the converted differential signal is output through the differential output end of the input matching balun 20. Specifically, the input matching balun 20 at least includes a first transformer T1. As Figure 3 shown, one side of the primary end of the first transformer T1 accesses the radio frequency signal, and the other side is grounded. The two sides of the secondary end of the first transformer T1 are used as the differential output ends of the input matching balun 20. At the same time, the center tap of the secondary end of the first transformer T1 accesses a first bias voltage V bias1, which is used to provide a bias voltage for the primary drive amplifier 30 of the subsequent stage and complete impedance matching.

[0039] The primary drive amplifier 30 is used to amplify the differential signal for the first time to drive the subsequent stage. Its differential input terminal is connected to the differential output terminal of the input matching balun to receive the differential signal, and the differential signal is amplified to form a primary amplified differential signal and then output from the differential output terminal of the primary drive amplifier. Figure 4 The circuit structure schematic diagram of the primary drive amplifier 30 in this embodiment is shown. It mainly includes a first PMOS variable capacitor tube P1, a second PMOS variable capacitor tube P2, a first transistor M1, a second transistor M2, a first neutralization capacitor CN1, and a second neutralization capacitor CN2. Among them, the sources of the first transistor M1 and the second transistor M2 are grounded. The gates of the first transistor M1 and the second transistor M2 are used as the differential input terminals of the primary drive amplifier 30 and are connected to both sides of the secondary terminal of the first transformer T1. The gate of the first PMOS variable capacitor tube P1 is connected to the gate of the first transistor M1, and the gate of the second PMOS variable capacitor tube P2 is connected to the gate of the second transistor M2. The substrates of the first PMOS variable capacitor tube P1 and the second PMOS variable capacitor tube P2 are connected and connected to the first regulation signal V tune1 , the drain of the first transistor M1 is connected to the gate of the second transistor M2 after being connected in series with the first neutralization capacitor CN1, the drain of the second transistor M2 is connected to the gate of the first transistor M1 after being connected in series with the second neutralization capacitor CN2, and the drains of the first transistor M1 and the second transistor M2 are used as the differential output terminals of the primary drive amplifier 30.

[0040] Figure 5 The simulation schematic diagram showing the influence of adding variable capacitor tubes on the circuit in the primary drive amplifier is shown. From Figure 5 it can be seen that in the case of setting the PMOS variable capacitor tube (with P-varactor), the capacitance change curve is smoother compared to the case of not setting the PMOS variable capacitor tube (without P-varactor). Therefore, in this embodiment, adding a variable capacitor tube to the gate of the drive stage amplifier can effectively compensate for the non-linear change of the transistor input capacitance, thereby improving the circuit linearity; in addition, due to PVT (Pressure, Volume, Temperature) changes or inaccurate models resulting in inconsistent input capacitance with the simulation, adjusting the voltage magnitude of V tnne1 can also be used for compensation.

[0041] The power splitter 40 has a differential input terminal and two differential output terminals. Its differential input terminal is connected to the differential output terminal of the primary drive amplifier 30 to receive the primary amplified differential signal output by the primary drive amplifier 30. Subsequently, the power splitter 40 evenly divides the primary amplified differential signal into the same first amplified differential signal and second amplified differential signal. The first amplified differential signal is output from the first differential output terminal of the power splitter 40, and the second amplified differential signal is output from the second differential output terminal of the power splitter 40.

[0042] Specifically, Figure 6 The schematic circuit structure diagram of the power splitter 40 is shown. It mainly includes a first coil L1, a second coil L2, a third coil L3, and a fourth coil L4. One end of the first coil L1 is connected to the drain of the first transistor M1 of the primary drive amplifier 30. The other end of the first coil L1 is connected to one end of the second coil L2. The other end of the second coil L2 is then connected to the drain of the second transistor M2 of the primary drive amplifier 30 to complete the reception of the primary amplified differential signal. At the same time, the other end of the first coil L1 (i.e., one end of the second coil L2) is also connected to the operating voltage VDD for providing VDD to the primary drive amplifier 30. The third coil L3 is coupled to the first coil L1. Both sides of the third coil L3 serve as the first differential output terminal of the power splitter 40. The fourth coil L4 is coupled to the second coil L2. Both sides of the fourth coil L4 serve as the second differential output terminal of the power splitter 40. The center taps of the third coil L3 and the fourth coil L4 are both connected to the second bias voltage V bias2 , providing a bias voltage for the subsequent-stage amplifier and achieving impedance matching.

[0043] The first secondary drive amplifier 51 and the second secondary drive amplifier 52 are secondary drive amplifiers with the same structural functions, respectively used to amplify the two amplified differential signals output by the power splitter 40 to drive the subsequent stage. Among them, the differential input terminal of the first secondary drive amplifier 51 is connected to the first differential output terminal of the power splitter 40 to receive the first amplified differential signal, and after amplifying the first amplified differential signal to form a first secondary amplified differential signal, it is output from the differential output terminal of the first secondary drive amplifier 51. The differential input terminal of the second secondary drive amplifier 52 is connected to the second differential output terminal of the power splitter 40 to receive the second amplified differential signal, and after amplifying the second amplified differential signal to form a second secondary amplified differential signal, it is output from the differential output terminal of the second secondary drive amplifier 52.

[0044] Figure 7 and Figure 8 respectively show the schematic circuit structure diagrams of the first secondary drive amplifier 51 and the second secondary drive amplifier 52. As Figure 7 and Figure 8As can be seen from the content shown, its actual circuit structure is the same as that of the primary drive amplifier 30, and both improve the linearity of the circuit through PMOS variable capacitance tubes.

[0045] As Figure 7 shown, the first secondary drive amplifier 51 includes at least: a third PMOS variable capacitance tube P3, a fourth PMOS variable capacitance tube P4, a third transistor M3, a fourth transistor M4, a third neutralization capacitor CN3, and a fourth neutralization capacitor CN4; wherein, the sources of the third transistor M3 and the fourth transistor M4 are grounded, the gates of the third transistor M3 and the fourth transistor M4 serve as the differential input terminals of the first secondary drive amplifier 51 and are connected to both sides of the third coil L3, the gate of the third PMOS variable capacitance tube P3 is connected to the gate of the third transistor M3, the gate of the fourth PMOS variable capacitance tube P4 is connected to the gate of the fourth transistor M4, the substrates of the third PMOS variable capacitance tube P3 and the fourth PMOS variable capacitance tube P4 are connected and connected to the second control signal V tune2 , the drain of the third transistor M3 is connected to the gate of the fourth transistor M4 after being connected in series with the third neutralization capacitor CN3, the drain of the fourth transistor M4 is connected to the gate of the third transistor M3 after being connected in series with the fourth neutralization capacitor CN4, and the drains of the third transistor M3 and the fourth transistor M4 serve as the differential output terminals of the first secondary drive amplifier 51.

[0046] As Figure 8 shown, the second secondary drive amplifier 52 includes at least: a fifth PMOS variable capacitance tube P5, a sixth PMOS variable capacitance tube P6, a fifth transistor M5, a sixth transistor M6, a fifth neutralization capacitor CN5, and a sixth neutralization capacitor CN6; wherein, the sources of the fifth transistor M5 and the sixth transistor M6 are grounded, the gates of the fifth transistor M5 and the sixth transistor M6 serve as the differential input terminals of the second secondary drive amplifier 52 and are connected to both sides of the fourth coil L4, the gate of the fifth PMOS variable capacitance tube P5 is connected to the gate of the fifth transistor M5, the gate of the sixth PMOS variable capacitance tube P6 is connected to the gate of the sixth transistor M6, the substrates of the fifth PMOS variable capacitance tube P5 and the sixth PMOS variable capacitance tube P6 are connected and connected to the second control signal V tune2 , the drain of the fifth transistor M5 is connected to the gate of the sixth transistor M6 after being connected in series with the fifth neutralization capacitor CN5, the drain of the sixth transistor M6 is connected to the gate of the fifth transistor M5 after being connected in series with the sixth neutralization capacitor CN6, and the drains of the fifth transistor M5 and the sixth transistor M6 serve as the differential output terminals of the second secondary drive amplifier 52.

[0047] The first inter-stage matching network 61 and the second inter-stage matching network 62 are also two matching networks with the same structural function, which are used for broadband impedance matching between the secondary drive amplifier of the previous stage and the power stage amplifier of the subsequent stage. In this embodiment, both the first inter-stage matching network 61 and the second inter-stage matching network 62 have a differential input terminal and a differential output terminal. Specifically, the differential input terminal of the first inter-stage matching network 61 is connected to the differential output terminal of the first secondary drive amplifier 51, and the first secondary amplified differential signal passes through the first inter-stage matching network 51 and is output from the differential output terminal of the first inter-stage matching network 51; the differential input terminal of the second inter-stage matching network 62 is connected to the differential output terminal of the second secondary drive amplifier 52, and the second secondary amplified differential signal passes through the second inter-stage matching network 52 and is output from the differential output terminal of the second inter-stage matching network 52. Figure 9 (a) and Figure 9 (b) respectively show the circuit structure diagrams of the first inter-stage matching network 61 and the second inter-stage matching network 62.

[0048] As Figure 9 (a) shows, the first inter-stage matching network 61 at least includes: a second transformer T2, wherein one side of the primary terminal of the second transformer T2 is connected to the drain of the third transistor M3, the other side of the primary terminal of the second transformer T2 is connected to the drain of the fourth transistor M4, the center tap of the primary terminal of the second transformer T2 is connected to the operating voltage VDD, both sides of the secondary terminal of the second transformer T2 are used as the differential output terminals of the first inter-stage matching network 61, and the center tap of the secondary terminal of the second transformer T2 is connected to the third bias voltage V bias3 . As Figure 9 (b) shows, the second inter-stage matching network 62 at least includes: a third transformer T3; wherein one side of the primary terminal of the third transformer T3 is connected to the drain of the fifth transistor M5, the other side of the primary terminal of the third transformer T3 is connected to the drain of the sixth transistor M6, the center tap of the primary terminal of the third transformer T3 is connected to the operating voltage VDD, both sides of the secondary terminal of the third transformer T3 are used as the differential output terminals of the second inter-stage matching network 62, and the center tap of the secondary terminal of the third transformer T3 is connected to the third bias voltage V bias3 . The third bias voltage V connected to the center taps of the secondary terminals of the above two matching networks bias3 is used to provide a bias voltage for the power stage drive amplifier of the subsequent stage.

[0049] The power stage amplifier is used to amplify the differential signal output from the previous stage again. The structures and functions of the first power stage amplifier 71 and the second power stage amplifier 72 in this embodiment are exactly the same. The differential input terminal of the first power stage amplifier 71 is connected to the differential output terminal of the first inter-stage matching network 61 to receive the first secondary amplified differential signal. The bias signal input terminal of the first power stage amplifier 71 is connected to the output terminal of the adaptive bias circuit 10 to receive the DC bias signal, and the first secondary amplified differential signal is amplified under the action of the DC bias signal to form the first power amplified differential signal and then output from the differential output terminal of the first power stage amplifier 71; the differential input terminal of the second power stage amplifier 72 is connected to the differential output terminal of the second inter-stage matching network 62 to receive the second secondary amplified differential signal. The bias signal input terminal of the second power stage amplifier 72 is connected to the output terminal of the adaptive bias circuit 10 to receive the DC bias signal, and the second secondary amplified differential signal is amplified under the action of the DC bias signal to form the second power amplified differential signal and then output from the differential output terminal of the second power stage amplifier 72.

[0050] Specifically, as Figure 10 shown, the first power stage amplifier 71 at least includes: the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the seventh neutralization capacitor CN7, the eighth neutralization capacitor CN8, the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2; among them, the gate of the seventh transistor M7 is connected to one side of the secondary terminal of the second transformer T2. The source of the seventh transistor M7 and the source of the tenth transistor M10 are grounded. The drain of the seventh transistor M7 is connected to the gate of the tenth transistor M10 after being connected in series with the seventh neutralization capacitor CN7. The gate of the eighth transistor M8 is connected to the gate of the seventh transistor M7 after being connected in series with the first capacitor C1. The source of the eighth transistor M8 is grounded. The drain of the eighth transistor M8 is connected to the drain of the seventh transistor M7. The source of the ninth transistor M9 is grounded. The drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10. The gate of the ninth transistor M9 is connected to the gate of the tenth transistor M10 after being connected in series with the second capacitor C2. The gate of the tenth transistor M10 is connected to the other side of the secondary terminal of the second transformer T2. The drain of the tenth transistor M10 is connected to the gate of the seventh transistor M7 after being connected in series with the eighth neutralization capacitor CN8. One end of the first resistor R1 is connected to the gate of the eighth transistor M8, and the other end of the first resistor R1 is connected to the DC bias signal V b , one end of the second resistor R2 is connected to the DC bias signal V b , the other end of the second resistor R2 is connected to the gate of the ninth transistor M9. The drains of the seventh transistor M7 and the tenth transistor M10 are used as the differential output terminals of the first power stage amplifier 71.

[0051] AsFigure 11 As shown, the second power stage amplifier 72 includes at least: an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a ninth neutralizing capacitor CN9, a tenth neutralizing capacitor CN10, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4; wherein, the gate of the eleventh transistor M11 is connected to one side of the secondary terminal of the third transformer T3, the source of the eleventh transistor M11 and the source of the fourteenth transistor M14 are grounded, the drain of the eleventh transistor M11 is connected to the gate of the fourteenth transistor M14 after being connected in series with the ninth neutralizing capacitor CN9, the gate of the twelfth transistor M12 is connected to the gate of the eleventh transistor M11 after being connected in series with the third capacitor C3, the source of the twelfth transistor M12 is grounded, the drain of the twelfth transistor M12 is connected to the drain of the eleventh transistor M11, the source of the thirteenth transistor M13 is grounded, the drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14, the gate of the thirteenth transistor M13 is connected to the gate of the fourteenth transistor M14 after being connected in series with the fourth capacitor C4, the gate of the fourteenth transistor M14 is connected to the other side of the secondary terminal of the third transformer T3, the drain of the fourteenth transistor M14 is connected to the gate of the eleventh transistor M11 after being connected in series with the tenth neutralizing capacitor CN10, one end of the third resistor R3 is connected to the gate of the twelfth transistor M12, and the other end of the third resistor R3 is connected to the DC bias signal V b , one end of the fourth resistor R4 is connected to the DC bias signal V b , the other end of the fourth resistor R4 is connected to the gate of the thirteenth transistor M13, and the drains of the eleventh transistor M11 and the fourteenth transistor M14 serve as the differential output terminals of the second power stage amplifier 72.

[0052] In this embodiment, taking the first power stage amplifier 71 as an example, M7 and M10 are the main transistors, and M8 and M9 are the auxiliary transistors, forming a dual - gate amplification structure. The sources of the transistors M7, M8, M9, and M10 are grounded. The differential output terminal of the inter - stage matching network is connected to the gates of M7 and M10 of the power stage amplifier. The gate of M8 is divided into two paths. One path is connected to the gate of M7 through C1, and one path is connected to V b , the gate of M7 is connected to the gate of M8 through the capacitor C1 and is also connected to the drain of M10 through CN8; the gate of M9 is divided into two paths. One path is connected to the gate of M10 through C2, and one path is connected to V b , the gate of M10 is connected to the gate of M9 through the capacitor C2 and is also connected to the drain of M7 through CN7. In actual implementation, the main transistors and the auxiliary transistors work in different states, thereby achieving the effect of gain complementarity. As Figure 12As shown, it shows the relationship between the input power Pin and the gain Gain of the main transistor and the auxiliary transistor. The first part in the figure represents the curve of the gain varying with the output power when the main transistor is biased in class AB, the second part represents the curve of the gain varying with the output power when the auxiliary transistor is biased in class C, and the third part represents the overall gain curve presented after the gains of the main transistor and the auxiliary transistor are complementary. Combining Figure 12 It can be seen that the gain compression of the main transistor is compensated by the gain expansion of the auxiliary transistor, thereby improving the linearity of the circuit.

[0053] Finally, the power combiner 80 in this embodiment has two differential input terminals and one single-ended output terminal. The first differential input terminal of the power combiner 80 is connected to the differential output terminal of the first power stage amplifier 71 to receive the first power amplified differential signal, and the second differential input terminal of the power combiner 80 is connected to the differential output terminal of the second power stage amplifier 72 to receive the second power amplified differential signal. The power combiner combines the first power amplified differential signal and the second power amplified differential signal to form a radio frequency amplified signal, and outputs it from the single-ended output terminal of the power combiner 80.

[0054] The circuit structure schematic diagram of the power combiner 80 is as Figure 13 shown, and mainly includes a fifth coil L5, a sixth coil L6, a seventh coil L7, and an eighth coil L8. The two ends of the fifth coil L5 are used as the first differential input terminal of the power amplifier 80 and are connected to the drains of the seventh transistor M7 and the tenth transistor M10. The center tap of the fifth coil L5 is connected to the operating voltage VDD. The two ends of the sixth coil L6 are used as the second differential input terminal of the power amplifier 80 and are connected to the drains of the eleventh transistor M11 and the fourteenth transistor M14. The center tap of the sixth coil L6 is connected to the operating voltage VDD. The seventh coil L7 is coupled to the fifth coil L5, and the eighth coil L8 is coupled to the sixth coil L6. One end of the seventh coil L7 is used as the single-ended output terminal of the power combiner 80. The second end of the seventh coil L7 is connected to the first end of the eighth coil L8, and the second end of the eighth coil L8 is grounded.

[0055] Figure 14 shows the overall circuit structure schematic diagram of the power amplifier in this embodiment, which is used to specifically describe the connection relationship between the above-mentioned various structures. In this embodiment, the first transistor M1 to the fourteenth transistor M14 are all N-type transistors.

[0056] In this embodiment, a power combiner is used to combine two amplified differential signals to achieve high output power of the power amplifier, and a variable capacitor tube is added to the drive amplifier to compensate for the non-linear change of the transistor input capacitance, thereby improving the circuit linearity. Further, an adaptive bias circuit outputs a DC bias signal corresponding to the RF signal to dynamically adjust the power stage amplifier, so that the power amplifier has a gain complementary effect, completing the improvement of the linearity of the power amplifier circuit and enabling the power amplifier to output an RF signal with high power and high linearity.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A power amplifier, characterized in that, Comprising: An adaptive bias circuit, an input matching balun, a primary drive amplifier, a power divider, a first secondary drive amplifier, a second secondary drive amplifier, a first inter-stage matching network, a second inter-stage matching network, a first power stage amplifier, a second power stage amplifier, and a power combiner; wherein, The input end of the adaptive bias circuit inputs a radio frequency signal to be amplified, and converts the radio frequency signal into a DC bias signal for output; The single-ended input end of the input matching balun inputs a radio frequency signal to be amplified, and converts the radio frequency signal into a differential signal for output from the differential output end; The differential input end of the primary drive amplifier is connected to the differential output end of the input matching balun to receive the differential signal, and amplifies the differential signal to form a primary amplified differential signal, which is then output from the differential output end of the primary drive amplifier; The differential input end of the power divider is connected to the differential output end of the primary drive amplifier to receive the primary amplified differential signal, and evenly divides the primary amplified differential signal into a first amplified differential signal and a second amplified differential signal. The first amplified differential signal is output from the first differential output end of the power divider, and the second amplified differential signal is output from the second differential output end of the power divider; The differential input end of the first secondary drive amplifier is connected to the first differential output end of the power divider to receive the first amplified differential signal, and amplifies the first amplified differential signal to form a first secondary amplified differential signal, which is then output from the differential output end of the first secondary drive amplifier; The differential input end of the second secondary drive amplifier is connected to the second differential output end of the power divider to receive the second amplified differential signal, and amplifies the second amplified differential signal to form a second secondary amplified differential signal, which is then output from the differential output end of the second secondary drive amplifier; The differential input end of the first inter-stage matching network is connected to the differential output end of the first secondary drive amplifier, and the first secondary amplified differential signal passes through the first inter-stage matching network and is output from the differential output end of the first inter-stage matching network; The differential input end of the second inter-stage matching network is connected to the differential output end of the second secondary drive amplifier, and the second secondary amplified differential signal passes through the second inter-stage matching network and is output from the differential output end of the second inter-stage matching network; The differential input end of the first power stage amplifier is connected to the differential output end of the first inter-stage matching network to receive the first secondary amplified differential signal, and the bias signal input end of the first power stage amplifier is connected to the output end of the adaptive bias circuit to receive the DC bias signal. The first secondary amplified differential signal is amplified under the action of the DC bias signal to form a first power amplified differential signal, which is then output from the differential output end of the first power stage amplifier; The differential input terminal of the second power stage amplifier is connected to the differential output terminal of the second-stage inter-stage matching network to receive the second-stage amplified differential signal. The bias signal input terminal of the second power stage amplifier is connected to the output terminal of the adaptive bias circuit to receive the DC bias signal, and the second-stage amplified differential signal is amplified under the action of the DC bias signal to form a second power amplified differential signal, which is then output from the differential output terminal of the second power stage amplifier. The first differential input terminal of the power combiner is connected to the differential output terminal of the first power stage amplifier to receive the first power amplified differential signal. The second differential input terminal of the power combiner is connected to the differential output terminal of the second power stage amplifier to receive the second power amplified differential signal. The power combiner combines the first power amplified differential signal and the second power amplified differential signal to form a radio frequency amplified signal, which is then output from the single-ended output terminal of the power combiner.

2. The power amplifier according to claim 1, wherein The adaptive bias circuit at least includes: a cascaded envelope detection circuit and a voltage amplification circuit, and the output terminal of the voltage amplification circuit serves as the output terminal of the adaptive bias circuit.

3. The power amplifier according to claim 1, wherein The input matching balun at least includes: a first transformer; one side of the primary terminal of the first transformer is connected to the radio frequency signal, the other side of the primary terminal of the first transformer is grounded, the center tap of the secondary terminal of the first transformer is connected to a first bias voltage, and both sides of the secondary terminal of the first transformer serve as the differential output terminals of the input matching balun.

4. The power amplifier according to claim 3, characterized in that, The primary driver amplifier at least includes: a first PMOS variable capacitor, a second PMOS variable capacitor, a first transistor, a second transistor, a first neutralizing capacitor, and a second neutralizing capacitor; wherein, the sources of the first transistor and the second transistor are grounded. The gates of the first transistor and the second transistor serve as the differential input terminals of the primary driver amplifier and are connected to both sides of the secondary terminal of the first transformer. The gate of the first PMOS variable capacitor is connected to the gate of the first transistor. The gate of the second PMOS variable capacitor is connected to the gate of the second transistor. The substrates of the first PMOS variable capacitor and the second PMOS variable capacitor are connected and connected to a first control signal. The drain of the first transistor is connected to the gate of the second transistor after being connected in series with the first neutralizing capacitor. The drain of the second transistor is connected to the gate of the first transistor after being connected in series with the second neutralizing capacitor. The drains of the first transistor and the second transistor serve as the differential output terminals of the primary driver amplifier.

5. The power amplifier according to claim 4, characterized in that, The power divider at least includes: a first coil, a second coil, a third coil, and a fourth coil; wherein, one end of the first coil is connected to the drain of the first transistor, the other end of the first coil is connected to one end of the second coil, the other end of the second coil is connected to the drain of the second transistor, and the other end of the first coil is connected to the operating voltage. The third coil is coupled to the first coil. The center tap of the third coil is connected to a second bias voltage, and both sides of the third coil serve as the first differential output terminals of the power divider; the fourth coil is coupled to the second coil. The center tap of the fourth coil is connected to the second bias voltage, and both sides of the fourth coil serve as the second differential output terminals of the power divider.

6. The power amplifier according to claim 5, characterized in that The first secondary driver amplifier at least includes: a third PMOS variable capacitor, a fourth PMOS variable capacitor, a third transistor, a fourth transistor, a third neutralization capacitor, and a fourth neutralization capacitor; wherein, the sources of the third transistor and the fourth transistor are grounded. The gates of the third transistor and the fourth transistor serve as the differential input terminals of the first secondary driver amplifier and are connected to both sides of the third coil. The gate of the third PMOS variable capacitor is connected to the gate of the third transistor. The gate of the fourth PMOS variable capacitor is connected to the gate of the fourth transistor. The substrates of the third PMOS variable capacitor and the fourth PMOS variable capacitor are connected and connected to a second regulation signal. The drain of the third transistor is connected to the gate of the fourth transistor after being connected in series with the third neutralization capacitor. The drain of the fourth transistor is connected to the gate of the third transistor after being connected in series with the fourth neutralization capacitor. The drains of the third transistor and the fourth transistor serve as the differential output terminals of the first secondary driver amplifier; The second secondary driver amplifier at least includes: a fifth PMOS variable capacitor, a sixth PMOS variable capacitor, a fifth transistor, a sixth transistor, a fifth neutralization capacitor, and a sixth neutralization capacitor; wherein, the sources of the fifth transistor and the sixth transistor are grounded. The gates of the fifth transistor and the sixth transistor serve as the differential input terminals of the second secondary driver amplifier and are connected to both sides of the fourth coil. The gate of the fifth PMOS variable capacitor is connected to the gate of the fifth transistor. The gate of the sixth PMOS variable capacitor is connected to the gate of the sixth transistor. The substrates of the fifth PMOS variable capacitor and the sixth PMOS variable capacitor are connected and connected to a second regulation signal. The drain of the fifth transistor is connected to the gate of the sixth transistor after being connected in series with the fifth neutralization capacitor. The drain of the sixth transistor is connected to the gate of the fifth transistor after being connected in series with the sixth neutralization capacitor. The drains of the fifth transistor and the sixth transistor serve as the differential output terminals of the second secondary driver amplifier.

7. The power amplifier according to claim 6, wherein The first inter-stage matching network at least includes: a second transformer; wherein, one side of the primary end of the second transformer is connected to the drain of the third transistor, the other side of the primary end of the second transformer is connected to the drain of the fourth transistor, the center tap of the primary end of the second transformer is connected to the operating voltage, both sides of the secondary end of the second transformer serve as the differential output terminals of the first inter-stage matching network, and the center tap of the secondary end of the second transformer is connected to the third bias voltage; The second inter-stage matching network at least includes: a third transformer; wherein, one side of the primary end of the third transformer is connected to the drain of the fifth transistor, the other side of the primary end of the third transformer is connected to the drain of the sixth transistor, the center tap of the primary end of the third transformer is connected to the operating voltage, both sides of the secondary end of the third transformer serve as the differential output terminals of the second inter-stage matching network, and the center tap of the secondary end of the third transformer is connected to the third bias voltage.

8. The power amplifier according to claim 7, characterized in that, The first power stage amplifier at least includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a seventh neutralizing capacitor, an eighth neutralizing capacitor, a first capacitor, a second capacitor, a first resistor, and a second resistor; wherein, the gate of the seventh transistor is connected to one side of the secondary end of the second transformer, the source of the seventh transistor and the source of the tenth transistor are grounded, the drain of the seventh transistor is connected to the gate of the tenth transistor after being connected in series with the seventh neutralizing capacitor, the gate of the eighth transistor is connected to the gate of the seventh transistor after being connected in series with the first capacitor, the source of the eighth transistor is grounded, the drain of the eighth transistor is connected to the drain of the seventh transistor, the source of the ninth transistor is grounded, the drain of the ninth transistor is connected to the drain of the tenth transistor, the gate of the ninth transistor is connected to the gate of the tenth transistor after being connected in series with the second capacitor, the gate of the tenth transistor is connected to the other side of the secondary end of the second transformer, the drain of the tenth transistor is connected to the gate of the seventh transistor after being connected in series with the eighth neutralizing capacitor, one end of the first resistor is connected to the gate of the eighth transistor, the other end of the first resistor is connected to the DC bias signal, one end of the second resistor is connected to the DC bias signal, the other end of the second resistor is connected to the gate of the ninth transistor, and the drain of the seventh transistor and the drain of the tenth transistor serve as the differential output terminals of the first power stage amplifier; The second power stage amplifier at least includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a ninth neutralizing capacitor, a tenth neutralizing capacitor, a third capacitor, a fourth capacitor, a third resistor, and a fourth resistor; wherein, The gate of the eleventh transistor is connected to one side of the secondary terminal of the third transformer. The sources of the eleventh transistor and the fourteenth transistor are grounded. The drain of the eleventh transistor is connected to the gate of the fourteenth transistor after being connected in series with the ninth neutralizing capacitor. The gate of the twelfth transistor is connected to the gate of the eleventh transistor after being connected in series with the third capacitor. The source of the twelfth transistor is grounded. The drain of the twelfth transistor is connected to the drain of the eleventh transistor. The source of the thirteenth transistor is grounded. The drain of the thirteenth transistor is connected to the drain of the fourteenth transistor. The gate of the thirteenth transistor is connected to the gate of the fourteenth transistor after being connected in series with the fourth capacitor. The gate of the fourteenth transistor is connected to the other side of the secondary terminal of the third transformer. The drain of the fourteenth transistor is connected to the gate of the eleventh transistor after being connected in series with the tenth neutralizing capacitor. One end of the third resistor is connected to the gate of the twelfth transistor, and the other end of the third resistor is connected to the DC bias signal. One end of the fourth resistor is connected to the DC bias signal, and the other end of the fourth resistor is connected to the gate of the thirteenth transistor. The drains of the eleventh transistor and the fourteenth transistor serve as the differential output terminals of the second power stage amplifier.

9. The power amplifier according to claim 8, wherein The power combiner at least includes: a fifth coil, a sixth coil, a seventh coil, and an eighth coil. Both ends of the fifth coil serve as the first differential input terminals of the power amplifier and are connected to the drains of the seventh transistor and the tenth transistor. The center tap of the fifth coil is connected to the operating voltage. Both ends of the sixth coil serve as the second differential input terminals of the power amplifier and are connected to the drains of the eleventh transistor and the fourteenth transistor. The center tap of the sixth coil is connected to the operating voltage. The seventh coil is coupled to the fifth coil, and the eighth coil is coupled to the sixth coil. One end of the seventh coil serves as the single-ended output terminal of the power combiner. The second end of the seventh coil is connected to the first end of the eighth coil, and the second end of the eighth coil is grounded.

10. The power amplifier according to claim 9, wherein The first transistor to the fourteenth transistor are all N-type transistors.

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