Chip stacking structure, memory and electronic equipment

Abstract

The utility model provides a chip stacking structure, a memory and electronic equipment, and relates to the field of chips. The chip stacking structure comprises a substrate and at least two chip sets arranged on the substrate at intervals. In every two adjacent chip sets, one chip, adjacent to the fluid layer on the lead, in the first chip group is manufactured by adopting a rewiring layer technology, and is connected with the chip, located on the uppermost layer, in the third chip group through a first bonding wire penetrating through the fluid layer on the lead; the chip located on the uppermost layer in the fourth chip group is manufactured by adopting a rewiring layer technology and is connected with the chip located on the lowermost layer in the second chip group through a second bonding wire. According to the chip stacking structure, on the basis of chip stacking, the FOW technology and the RDL technology are utilized to enable every two adjacent chip sets to be interconnected, compared with a single-stacking structure and a double-stacking structure, the chip stacking structure has the advantages that the space utilization rate is higher, the space occupied by chip stacking is smaller, and therefore miniaturization design of a memory is better facilitated.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and particularly to a chip stacking structure, a memory, and an electronic device. Background Art

[0002] The information disclosed in this background art section is only intended to enhance the understanding of the overall background art of the present disclosure, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art.

[0003] In order to increase the storage capacity of a memory, usually more chips are stacked in the height direction, for example, a single-stack or double-stack design is adopted. The single-stack structure stacks all chips in the height direction at the same position, and the double-stack structure divides all chips into at least two chip groups, the at least two chip groups are arranged at intervals, and each chip group is stacked in the height direction respectively. However, adopting the single-stack structure will cause the stacking height of the chips to be too high, occupying too much longitudinal space, while adopting the double-stack structure, although the stacking height is reduced, the occupied lateral space is large, and the space utilization rates of both are low, which is not conducive to the miniaturization design of the memory. Summary of the Utility Model

[0004] In view of this, the purpose of the present application is to provide a chip stacking structure, a memory, and an electronic device, aiming to solve the technical problem that the chip stacking structure occupies a large space and is not conducive to the miniaturization design of the memory.

[0005] To achieve the above purpose, the technical solution adopted in the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a chip stacking structure, including:

[0007] A substrate;

[0008] At least two chip groups, which are arranged on the substrate at intervals. Among every two adjacent chip groups: one of the chip groups includes a first chip subgroup, a second chip subgroup, and a fluid layer on the lead. The first chip subgroup is located between the substrate and the second chip subgroup, and the fluid layer on the lead is arranged between two chips in the first chip subgroup or between the first chip subgroup and the second chip subgroup; the other chip group includes a third chip subgroup and a fourth chip subgroup, and the third chip subgroup is arranged between the substrate and the fourth chip subgroup;

[0009] Among them, one chip adjacent to the fluid layer on the lead in the first chip group is made by using the redistribution layer technology, and is connected to the chip located at the top layer in the third chip group through a first bonding wire passing through the fluid layer on the lead. The chip located at the top layer in the fourth chip group is made by using the redistribution layer technology, and is connected to the chip located at the bottom layer in the second chip group through a second bonding wire.

[0010] In one embodiment of the first aspect, the first chip group includes a first chip, a second chip, a third chip, a fourth chip, and a fifth chip stacked in a stepped manner in sequence. The substrate, the first chip, the second chip, the third chip, the fourth chip, and the fifth chip are sequentially connected through a third bonding wire. The fluid layer on the lead is disposed between the third chip and the fourth chip. The third chip is made by using the redistribution layer technology, and is connected to the chip located at the top layer in the third chip group through the first bonding wire passing through the fluid layer on the lead.

[0011] In one embodiment of the first aspect, the second chip group includes a sixth chip, a seventh chip, and an eighth chip stacked in a stepped manner in sequence. The sixth chip, the seventh chip, and the eighth chip are sequentially connected through a fourth bonding wire. The sixth chip is connected to the chip made by using the redistribution layer technology in the fourth chip group through the second bonding wire.

[0012] In one embodiment of the first aspect, the third chip group includes a ninth chip, a tenth chip, and an eleventh chip stacked in a stepped manner in sequence. The ninth chip, the tenth chip, and the eleventh chip are sequentially connected through a fifth bonding wire. The eleventh chip is connected to the chip made by using the redistribution layer technology in the first chip group through the first bonding wire passing through the fluid layer on the lead.

[0013] In one embodiment of the first aspect, the fourth chip group includes a twelfth chip, a thirteenth chip, a fourteenth chip, a fifteenth chip, and a sixteenth chip stacked in a stepped manner in sequence. The substrate, the twelfth chip, the thirteenth chip, the fourteenth chip, the fifteenth chip, and the sixteenth chip are sequentially connected through a sixth bonding wire. The sixteenth chip is made by using the redistribution layer technology, and is connected to the chip located at the bottom layer in the second chip group through the second bonding wire.

[0014] In one embodiment of the first aspect, the first chip group includes a first chip, a second chip, a third chip, and a fourth chip stacked in a stepped manner in sequence. The substrate, the first chip, the second chip, the third chip, and the fourth chip are sequentially connected by third bonding wires; the second chip group includes a fifth chip, a sixth chip, a seventh chip, and an eighth chip stacked in a stepped manner in sequence. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are sequentially connected by fourth bonding wires;

[0015] wherein, the fifth chip is connected to the chip made by using the redistribution layer technology in the fourth chip group through the second bonding wire. The fluid layer on the lead is disposed between the fourth chip and the fifth chip. The fourth chip is made by using the redistribution layer technology and is connected to the chip located at the uppermost layer in the third chip group through the first bonding wire passing through the fluid layer on the lead.

[0016] In one embodiment of the first aspect, the third chip group includes a ninth chip, a tenth chip, an eleventh chip, and a twelfth chip stacked in a stepped manner in sequence. The ninth chip, the tenth chip, the eleventh chip, and the twelfth chip are sequentially connected by fifth bonding wires. The twelfth chip is connected to the chip made by using the redistribution layer technology in the first chip group through the first bonding wire passing through the fluid layer on the lead.

[0017] In one embodiment of the first aspect, the fourth chip group includes a thirteenth chip, a fourteenth chip, a fifteenth chip, and a sixteenth chip stacked in a stepped manner in sequence. The substrate, the thirteenth chip, the fourteenth chip, the fifteenth chip, and the sixteenth chip are sequentially connected by sixth bonding wires. The sixteenth chip is made by using the redistribution layer technology and is connected to the chip located at the lowermost layer in the second chip group through the second bonding wire.

[0018] In one embodiment of the first aspect, the substrate and multiple chips in the first chip group are sequentially connected by third bonding wires, and multiple chips in the second chip group are sequentially connected by fourth bonding wires.

[0019] In one embodiment of the first aspect, the third bonding wires are located on the side of the first chip group away from the third chip group, and the fourth bonding wires are located on the side of the second chip group close to the fourth chip group.

[0020] In one embodiment of the first aspect, multiple chips in the third chip group are sequentially connected through fifth bonding wires, and the substrate and multiple chips in the fourth chip group are sequentially connected through sixth bonding wires.

[0021] In one embodiment of the first aspect, the fifth bonding wires are located on the side of the third chip group close to the first chip group, and the sixth bonding wires are located on the side of the fourth chip group far from the second chip group.

[0022] In a second aspect, an embodiment of the present application provides a memory, including a main board and the chip stacking structure in any of the above embodiments, and the chip stacking structure is disposed on the main board.

[0023] In a third aspect, an embodiment of the present application provides an electronic device, including the memory in the above embodiments.

[0024] The beneficial effects of the present application are as follows:

[0025] In the chip stacking structure provided by the present application, since one chip adjacent to the fluid layer on the lead in the first chip group is made by the redistribution layer technology and is connected to the chip at the top layer in the third chip group through the first bonding wire passing through the fluid layer on the lead. On this basis, the chip at the top layer in the fourth chip group is made by the redistribution layer technology and is connected to the chip at the bottom layer in the second chip group through the second bonding wire. In this way, on the basis of chip stacking, the FOW technology and the RDL technology are utilized to realize the interconnection of every two adjacent chip groups. Compared with the single-stack structure and the double-stack structure, it has a higher space utilization rate, and the space occupied by the chip stacking is smaller, thus being more conducive to the miniaturization design of the memory.

[0026] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0027] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 Shows a schematic structural diagram of a single-stack structure in the related art;

[0029] Figure 2 Shows a schematic structural diagram of a double-stack structure in the related art;

[0030] Figure 3 shows a structural schematic diagram of a double-stack four-row finger structure in the related art;

[0031] Figure 4 shows a brief schematic diagram of a chip stacking structure in an embodiment of the present application;

[0032] Figure 5 shows a structural schematic diagram of a chip stacking structure in some embodiments of the present application;

[0033] Figure 6 shows a structural schematic diagram of a chip stacking structure in other embodiments of the present application.

[0034] Description of main component symbols:

[0035] 100 - chip stacking structure; 110 - substrate; 120 - first chip group; 121 - first chip; 122 - second chip; 123 - third chip; 124 - fourth chip; 125 - fifth chip; 130 - second chip group; 131 - sixth chip; 132 - seventh chip; 133 - eighth chip; 140 - fluid layer on the lead; 150 - third chip group; 151 - ninth chip; 152 - tenth chip; 153 - eleventh chip; 160 - fourth chip group; 161 - twelfth chip; 162 - thirteenth chip; 163 - fourteenth chip; 164 - fifteenth chip; 165 - sixteenth chip; 171 - first bonding wire; 172 - second bonding wire; 173 - third bonding wire; 174 - fourth bonding wire; 175 - fifth bonding wire; 176 - sixth bonding wire. Detailed implementation manners

[0036] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application.

[0037] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.

[0039] In this application, unless otherwise clearly defined and limited, the terms such as "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0040] In this application, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0041] To increase the storage capacity of a memory, more chips are usually stacked in the height direction. For example, a single-stack or dual-stack design is adopted. The single-stack structure stacks all the chips in the height direction at the same position. The dual-stack structure divides all the chips into at least two chip groups, the at least two chip groups are arranged at intervals, and each chip group is stacked in the height direction respectively.

[0042] Here, 16 chips are taken as an example for illustration. As Figure 1 shown is the single-stack structure: the 16 chips are evenly divided into two chip groups, each chip group has 8 chips. Each chip in one chip group is a 1-channel chip, and each chip in the other chip group is a 0-channel chip. First, the 1-channel chip group is stacked, and then the 0-channel chip group is stacked on the basis of the 1-channel chip group. As Figure 2The following is a double-stack structure: 16 chips are evenly divided into two chip groups, each chip group also has 8 chips. Each chip in one chip group is a 1-channel chip, and each chip in the other chip group is a 0-channel chip. The two chip groups are arranged at intervals and are stacked in the height direction respectively.

[0043] However, adopting a single-stack structure will result in too high a stacking height of the chips, occupying too much vertical space. While adopting a double-stack structure, although the stacking height is reduced, the occupied horizontal space is relatively large, and the space utilization rates of both are low, which is not conducive to the miniaturization design of the memory. At the same time, Figure 1 The single-stack structure shown also has a relatively high bonding height of the bonding wires, thus increasing the process risk.

[0044] In addition, there is also Figure 3 the double-stack four-row finger structure shown. This stacking structure has stubs during substrate wiring. The stubs will not only generate antenna radiation effects, but also cause signal reflections, thus affecting the signal transmission quality.

[0045] To solve the above technical problems, on the one hand, an embodiment of the present application provides a chip stacking structure, which relates to the technical field of chips and is mainly applied to the memory of electronic devices.

[0046] As Figure 4 shown, the chip stacking structure 100 provided by this embodiment includes a substrate 110 and at least two chip groups.

[0047] Among them, at least two chip groups are arranged on the substrate 110 at intervals. In every two adjacent chip groups: one chip group includes a first chip subgroup 120, a second chip subgroup 130, and a film-on-wire layer 140 (FOW). The first chip subgroup 120 is arranged between the substrate 110 and the second chip subgroup 130, and the film-on-wire layer 140 is arranged between two chips in the first chip subgroup 120 or between the first chip subgroup 120 and the second chip subgroup 130; the other chip group includes a third chip subgroup 150 and a fourth chip subgroup 160, and the third chip subgroup 150 is arranged between the substrate 110 and the fourth chip subgroup 160. One chip adjacent to the film-on-wire layer 140 in the first chip subgroup 120 is made by using the re-distributed layer (RDL) technology and is connected to the chip at the top layer in the third chip subgroup 150 through a first bonding wire 171 passing through the film-on-wire layer 140. The chip at the top layer in the fourth chip subgroup 160 is made by using the re-distributed layer technology and is connected to the chip at the bottom layer in the second chip subgroup 130 through a second bonding wire 172.

[0048] Exemplarily, the first bonding wire 171 and the second bonding wire 172 can be selected from gold wires, silver alloy wires, copper wires, etc. The same applies to the bonding wires mentioned below, and no specific limitation is made here.

[0049] It should be noted that the re - distributed layer technology (RDL) refers to forming a layer of metal circuit network on the chip, re - arranging and re - wiring the I / O (input / output) ports, so that these contacts extend to the surface of the chip through semiconductor processes, expand the layout to a new and more spacious area, and form a surface array arrangement. The fluid - over - wire layer 140 is also called the FOW layer, which is a support - type adhesive, usually in the form of a thin film. Its main function is to allow the bonding wire to pass through. For example, the first bonding wire 171 can pass through the fluid - over - wire layer 140 from the first chip group 120 and connect to the third chip group 150. At the same time, the fluid - over - wire layer 140 can play a bonding effect before or during the placement of the chips.

[0050] Exemplarily, each chip in the first chip group 120 has 0 channels, each chip in the second chip group 130 has 1 channel, each chip in the third chip group 150 has 0 channels, and each chip in the fourth chip group 160 has 1 channel. Of course, it can also be that each chip in the first chip group 120 has 1 channel, each chip in the second chip group 130 has 0 channels, each chip in the third chip group 150 has 1 channel, and each chip in the fourth chip group 160 has 0 channels. No specific limitation is made here.

[0051] It can be understood that for the chip stacking structure 100 provided in this embodiment, since one chip adjacent to the fluid - over - wire layer 140 in the first chip group 120 is made by the re - distributed layer technology and is connected to the top - most chip in the third chip group 150 through the first bonding wire 171 passing through the fluid - over - wire layer 140. On this basis, the top - most chip in the fourth chip group 160 is made by the re - distributed layer technology and is connected to the bottom - most chip in the second chip group 130 through the second bonding wire 172. In this way, on the basis of chip stacking, the FOW technology and the RDL technology are used to interconnect every two adjacent chip groups. Compared with the single - stack structure and the double - stack structure, it has a higher space utilization rate, the space occupied by chip stacking is smaller, which is more conducive to the miniaturization design of the memory.

[0052] Such as Figure 5As shown, in one embodiment, the first chip group 120 includes a first chip 121, a second chip 122, a third chip 123, a fourth chip 124, and a fifth chip 125 that are stacked in a stepped manner in sequence. The substrate 110, the first chip 121, the second chip 122, the third chip 123, the fourth chip 124, and the fifth chip 125 are sequentially connected by third bonding wires 173. The fluid layer 140 on the lead is disposed between the third chip 123 and the fourth chip 124. The third chip 123 is made by using the redistribution layer technology and is connected to the chip located at the top layer in the third chip group 150 through a first bonding wire 171 passing through the fluid layer 140 on the lead.

[0053] It should be noted that the first chip 121, the second chip 122, the third chip 123, the fourth chip 124, and the fifth chip 125 are all 0-channel.

[0054] In this embodiment, since the fluid layer 140 on the lead is disposed between the third chip 123 and the fourth chip 124, the third chip 123 is made by using the redistribution layer technology and is connected to the chip located at the top layer in the third chip group 150 through a first bonding wire 171 passing through the fluid layer 140 on the lead. In this way, the interconnection between the first chip group 120 and the third chip group 150 is realized.

[0055] As Figure 5 shown, further, the second chip group 130 includes a sixth chip 131, a seventh chip 132, and an eighth chip 133 that are stacked in a stepped manner in sequence. The sixth chip 131, the seventh chip 132, and the eighth chip 133 are sequentially connected by fourth bonding wires 174. The sixth chip 131 is connected to the chip made by using the redistribution layer technology in the fourth chip group 160 through a second bonding wire 172.

[0056] It should be noted that the sixth chip 131, the seventh chip 132, and the eighth chip 133, the sixth chip 131, the seventh chip 132, and the eighth chip 133 are all 1-channel.

[0057] In this embodiment, since the sixth chip 131 is connected to the chip made by using the redistribution layer technology in the fourth chip group 160 through a second bonding wire 172, the interconnection between the second chip group 130 and the fourth chip group 160 is realized in this way.

[0058] As Figure 5As shown, in one embodiment, the third chip group 150 includes a ninth chip 151, a tenth chip 152, and an eleventh chip 153 stacked in a stepped manner in sequence. The ninth chip 151, the tenth chip 152, and the eleventh chip 153 are sequentially connected by a fifth bonding wire 175. The eleventh chip 153 is connected to a chip made by using a redistribution layer technology in the first chip group 120 through a first bonding wire 171 passing through the fluid layer 140 on the lead.

[0059] It should be noted that the ninth chip 151, the tenth chip 152, and the eleventh chip 153 are all 0 channels.

[0060] In this embodiment, since the eleventh chip 153 is connected to a chip made by using a redistribution layer technology in the first chip group 120 through the first bonding wire 171 passing through the fluid layer 140 on the lead, the interconnection between the first chip group 120 and the third chip group 150 is realized.

[0061] As Figure 5 shown, further, the fourth chip group 160 includes a twelfth chip 161, a thirteenth chip 162, a fourteenth chip 163, a fifteenth chip 164, and a sixteenth chip 165 stacked in a stepped manner in sequence. The substrate 110, the twelfth chip 161, the thirteenth chip 162, the fourteenth chip 163, the fifteenth chip 164, and the sixteenth chip 165 are sequentially connected by a sixth bonding wire 176. The sixteenth chip 165 is made by using a redistribution layer technology and is connected to the chip at the lowermost layer in the second chip group 130 through a second bonding wire 172.

[0062] It should be noted that the twelfth chip 161, the thirteenth chip 162, the fourteenth chip 163, the fifteenth chip 164, and the sixteenth chip 165 are all 1 channels.

[0063] In this embodiment, since the sixteenth chip 165 is made by using a redistribution layer technology and is connected to the chip at the lowermost layer in the second chip group 130 through the second bonding wire 172, the interconnection between the second chip group 130 and the fourth chip group 160 is realized.

[0064] As Figure 5As shown, in a specific embodiment, the chip stack structure 100 includes two chip groups. One chip group includes a first chip subgroup 120, a second chip subgroup 130, and a fluid layer on the lead 140. The other chip group includes a third chip subgroup 150 and a fourth chip subgroup 160. The first chip subgroup 120 includes a first chip 121, a second chip 122, a third chip 123, a fourth chip 124, and a fifth chip 125 stacked in a stepped manner in sequence. The substrate 110, the first chip 121, the second chip 122, the third chip 123, the fourth chip 124, and the fifth chip 125 are sequentially connected by a third bonding wire 173. The second chip subgroup 130 includes a sixth chip 131, a seventh chip 132, and an eighth chip 133 stacked in a stepped manner in sequence. The sixth chip 131, the seventh chip 132, and the eighth chip 133 are sequentially connected by a fourth bonding wire 174. The third chip subgroup 150 includes a ninth chip 151, a tenth chip 152, and an eleventh chip 153 stacked in a stepped manner in sequence. The ninth chip 151, the tenth chip 152, and the eleventh chip 153 are sequentially connected by a fifth bonding wire 175. The third chip subgroup 150 includes a twelfth chip 161, a thirteenth chip 162, a fourteenth chip 163, a fifteenth chip 164, and a sixteenth chip 165 stacked in a stepped manner in sequence. The substrate 110, the twelfth chip 161, the thirteenth chip 162, the fourteenth chip 163, the fifteenth chip 164, and the sixteenth chip 165 are sequentially connected by a sixth bonding wire 176.

[0065] Among them, the fluid layer on the lead 140 is disposed between the third chip 123 and the fourth chip 124. The third chip 123 is made by using a redistribution layer technology and is connected to the eleventh chip 153 through a first bonding wire 171 passing through the fluid layer on the lead 140. The sixteenth chip 165 is made by using a redistribution layer technology and is connected to the sixth chip 131 through a second bonding wire 172.

[0066] It should be noted that for the chip stack structure 100 in the above specific embodiment, there are 16 chips. The 16 chips are divided into two chip groups, and each chip group has 8 chips. The 8 chips in one chip group are divided into a first chip subgroup 120 and a second chip subgroup 130. The first chip subgroup 120 has 5 chips with 0 channels, and the second chip subgroup 130 has 3 chips with 1 channels. The 8 chips in the other chip group are divided into a third chip subgroup 150 and a fourth chip subgroup 160. The third chip subgroup 150 has 3 chips with 0 channels, and the fourth chip subgroup 160 has 5 chips with 1 channels. Of course, in addition to Figure 5 the 5 + 3 combination shown, it is also possible to adopt Figure 6The 4+4 combination shown, that is, each chip group has 4 chips, and the fluid layer 140 on the lead is arranged between the first chip group 120 and the second chip group 130. In addition, in other embodiments, the chip stack structure 100 may also have 32 chips, 8 chips, etc., and no specific limitations are made here.

[0067] The following introduces the 4+4 combination, that is, each chip group has 4 chips, and the fluid layer 140 on the lead is arranged between the first chip group 120 and the second chip group 130:

[0068] As Figure 6 shown, in another embodiment, the first chip group 120 includes the first chip 121, the second chip 122, the third chip 123, and the fourth chip 124 stacked in a stepped manner in sequence. The substrate 110, the first chip 121, the second chip 122, the third chip 123, and the fourth chip 124 are sequentially connected by the third bonding wire 173. The second chip group 130 includes the fifth chip 125, the sixth chip 131, the seventh chip 132, and the eighth chip 133 stacked in a stepped manner in sequence. The fifth chip 125, the sixth chip 131, the seventh chip 132, and the eighth chip 133 are sequentially connected by the fourth bonding wire 174. The fifth chip 125 is connected to the chip made by the redistribution layer technology in the fourth chip group 160 through the second bonding wire 172. The fluid layer 140 on the lead is arranged between the fourth chip 124 and the fifth chip 125. The fourth chip 124 is made by the redistribution layer technology and is connected to the chip located at the uppermost layer in the third chip group 150 through the first bonding wire 171 passing through the fluid layer 140 on the lead.

[0069] It should be noted that the first chip 121, the second chip 122, the third chip 123, and the fourth chip 124 are all 0 channels, and the fifth chip 125, the sixth chip 131, the seventh chip 132, and the eighth chip 133 are all 1 channels.

[0070] In this embodiment, since the fifth chip 125 is connected to the chip made by the redistribution layer technology in the fourth chip group 160 through the second bonding wire 172, and on this basis, the fourth chip 124 is made by the redistribution layer technology and is connected to the chip located at the uppermost layer in the third chip group 150 through the first bonding wire 171 passing through the fluid layer 140 on the lead, it is also possible to connect the first chip group 120 and the third chip group 150, and connect the second chip group 130 and the fourth chip group 160 to achieve the interconnection of adjacent two chip groups.

[0071] It should be noted that the fluid layer 140 on the lead allows the third bonding wire 173 to pass through, so that the third bonding wire 173 can pass through the fluid layer 140 on the lead to connect the third chip 123 and the fourth chip 124.

[0072] As Figure 6 shown, in another embodiment, the third chip group 150 includes the ninth chip 151, the tenth chip 152, the eleventh chip 153, and the twelfth chip 161 that are stacked in a stepped manner in sequence. The ninth chip 151, the tenth chip 152, the eleventh chip 153, and the twelfth chip 161 are sequentially connected by the fifth bonding wire 175. The twelfth chip 161 is connected to the chip made by using the redistribution layer technology in the first chip group 120 through the first bonding wire 171 passing through the fluid layer 140 on the lead. The fourth chip group 160 includes the thirteenth chip 162, the fourteenth chip 163, the fifteenth chip 164, and the sixteenth chip 165 that are stacked in a stepped manner in sequence. The substrate 110, the thirteenth chip 162, the fourteenth chip 163, the fifteenth chip 164, and the sixteenth chip 165 are sequentially connected by the sixth bonding wire 176. The sixteenth chip 165 is made by using the redistribution layer technology and is connected to the chip at the lowermost layer in the second chip group 130 through the second bonding wire 172.

[0073] It should be noted that the ninth chip 151, the tenth chip 152, the eleventh chip 153, and the twelfth chip 161 are all 0 channels, and the thirteenth chip 162, the fourteenth chip 163, the fifteenth chip 164, and the sixteenth chip 165 are all 1 channels.

[0074] In this embodiment, since the twelfth chip 161 is connected to the chip made by using the redistribution layer technology in the first chip group 120 through the first bonding wire 171 passing through the fluid layer 140 on the lead, on this basis, the sixteenth chip 165 is made by using the redistribution layer technology and is connected to the chip at the lowermost layer in the second chip group 130 through the second bonding wire 172. In this way, the first chip group 120 can also be connected to the third chip group 150, and the second chip group 130 can be connected to the fourth chip group 160 to realize the interconnection of two adjacent chip groups.

[0075] Combined with Figure 4 and Figure 5 shown, in one embodiment, the substrate 110 and multiple chips in the first chip group 120 are sequentially connected by the third bonding wire 173, and multiple chips in the second chip group 130 are sequentially connected by the fourth bonding wire 174.

[0076] In this embodiment, since multiple chips in the substrate 110 and the first chip group 120 are sequentially connected by the third bonding wires 173, and multiple chips in the second chip group 130 are sequentially connected by the fourth bonding wires 174, that is, each adjacent two chips in the first chip group 120 and between the substrate 110 and the first chip group 120 are interconnected by the third bonding wires 173, and each adjacent two chips in the second chip group 130 are interconnected by the fourth bonding wires 174. In this way, the interconnection between the chip group and the substrate 110 is achieved.

[0077] Combined with Figure 4 and Figure 5 As shown, further, the third bonding wires 173 are located on the side of the first chip group 120 away from the third chip group 150, and the fourth bonding wires 174 are located on the side of the second chip group 130 close to the fourth chip group 160.

[0078] In this embodiment, since the third bonding wires 173 are located on the side of the first chip group 120 away from the third chip group 150, and the fourth bonding wires 174 are located on the side of the second chip group 130 close to the fourth chip group 160. In this way, multiple chips in the first chip group 121 need to be arranged in a staggered manner, and multiple chips in the second chip group 130 also need to be arranged in a staggered manner. The staggering directions of the two can be different, thereby reducing the lateral space occupied by the first chip group 120 and the second chip group 130.

[0079] Combined with Figure 4 and Figure 5 As shown, in one embodiment, multiple chips in the third chip group 150 are sequentially connected by the fifth bonding wires 175, and multiple chips in the substrate 110 and the fourth chip group 160 are sequentially connected by the sixth bonding wires 176.

[0080] In this embodiment, since multiple chips in the third chip group 150 are sequentially connected by the fifth bonding wires 175, and multiple chips in the substrate 110 and the fourth chip group 160 are sequentially connected by the sixth bonding wires 176, that is, each adjacent two chips in the third chip group 150 are interconnected by the fifth bonding wires 175, and each adjacent two chips in the fourth chip group 160 and between the substrate 110 and the fourth chip group 160 are interconnected by the sixth bonding wires 176. In this way, the interconnection between the chip group and the substrate 110 is achieved.

[0081] Combined with Figure 4 and Figure 5 As shown, further, the fifth bonding wires 175 are located on the side of the third chip group 150 close to the first chip group 120, and the sixth bonding wires 176 are located on the side of the fourth chip group 160 away from the second chip group 130.

[0082] In this embodiment, since the fifth bonding wire 175 is located on the side of the third chip group 150 close to the first chip group 120, and the sixth bonding wire 176 is located on the side of the fourth chip group 160 away from the second chip group 130. In this way, multiple chips in the third chip group 123 need to be arranged in a staggered manner, and multiple chips in the fourth chip group 160 also need to be arranged in a staggered manner. The directions of the two staggered arrangements can be different, thereby reducing the lateral space occupied by the third chip group 150 and the fourth chip group 160.

[0083] In summary, the chip stacking structure 100 provided in this embodiment, on the basis of chip stacking, utilizes the FOW technology and the RDL technology to achieve the interconnection between every two adjacent chip groups. Compared with Figure 1 the single stacking structure shown, the bonding height of the bonding wire is lower, thereby reducing the process risk, and the stacking height is lower, making the thickness of the memory thinner, and the chip grinding thickness can be adjusted wider according to requirements. Compared with Figure 2 the double stacking structure shown, the lateral space occupied by chip stacking is effectively reduced. Compared with Figure 3 the double stacking four-row finger structure shown, it can eliminate the influence of stubs on the signal transmission quality during the wiring of the substrate 110.

[0084] In a second aspect, an embodiment of the present application provides a memory, including a main board and the chip stacking structure 100 in any of the above embodiments, and the chip stacking structure 100 is disposed on the main board.

[0085] Exemplarily, the main board can be a printed circuit board (PCB) or a flexible printed circuit board (FPC).

[0086] It can be understood that since the memory provided in this embodiment has the chip stacking structure 100 mentioned in any of the above embodiments, it has all the beneficial effects of the chip stacking structure 100, and will not be listed one by one here.

[0087] In a third aspect, an embodiment of the present application provides an electronic device, including the memory in the above embodiment. The electronic device includes any one of smart wearable products (such as smart watches, smart bracelets), mobile phones, tablets, computers, virtual reality (VR) terminal devices, and augmented reality (AR) terminal devices, and no specific limitation is made here.

[0088] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0089] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A chip stacking structure, characterized in that, Comprising: A substrate; At least two chip groups, which are arranged on the substrate at intervals. Among every two adjacent chip groups: one of the chip groups includes a first chip subgroup, a second chip subgroup and a fluid layer on the lead. The first chip subgroup is located between the substrate and the second chip subgroup, and the fluid layer on the lead is arranged between two chips in the first chip subgroup or between the first chip subgroup and the second chip subgroup; The other chip group includes a third chip subgroup and a fourth chip subgroup, and the third chip subgroup is arranged between the substrate and the fourth chip subgroup; Wherein, one chip in the first chip subgroup adjacent to the fluid layer on the lead is made by using the redistribution layer technology and is connected to the chip at the uppermost layer in the third chip subgroup through a first bonding wire passing through the fluid layer on the lead. The chip at the uppermost layer in the fourth chip subgroup is made by using the redistribution layer technology and is connected to the chip at the lowermost layer in the second chip subgroup through a second bonding wire.

2. The chip stacking structure according to claim 1, characterized in that, The first chip subgroup includes a first chip, a second chip, a third chip, a fourth chip and a fifth chip that are stacked in a stepped manner in sequence. The substrate, the first chip, the second chip, the third chip, the fourth chip and the fifth chip are connected in sequence through a third bonding wire. The fluid layer on the lead is arranged between the third chip and the fourth chip. The third chip is made by using the redistribution layer technology and is connected to the chip at the uppermost layer in the third chip subgroup through the first bonding wire passing through the fluid layer on the lead.

3. The chip stacking structure according to claim 2, wherein, The second chip subgroup includes a sixth chip, a seventh chip and an eighth chip that are stacked in a stepped manner in sequence. The sixth chip, the seventh chip and the eighth chip are connected in sequence through a fourth bonding wire. The sixth chip is connected to the chip made by using the redistribution layer technology in the fourth chip subgroup through the second bonding wire.

4. The chip stacking structure according to claim 1, wherein The third chip subgroup includes a ninth chip, a tenth chip and an eleventh chip that are stacked in a stepped manner in sequence. The ninth chip, the tenth chip and the eleventh chip are connected in sequence through a fifth bonding wire. The eleventh chip is connected to the chip made by using the redistribution layer technology in the first chip subgroup through the first bonding wire passing through the fluid layer on the lead.

5. The chip stacking structure according to claim 4, wherein The fourth chip subgroup includes a twelfth chip, a thirteenth chip, a fourteenth chip, a fifteenth chip and a sixteenth chip that are stacked in a stepped manner in sequence. The substrate, the twelfth chip, the thirteenth chip, the fourteenth chip, the fifteenth chip and the sixteenth chip are connected in sequence through a sixth bonding wire. The sixteenth chip is made by using the redistribution layer technology and is connected to the chip at the lowermost layer in the second chip subgroup through the second bonding wire.

6. The chip stacking structure according to claim 1, wherein The first chip group includes a first chip, a second chip, a third chip, and a fourth chip stacked in a stepped manner in sequence. The substrate, the first chip, the second chip, the third chip, and the fourth chip are sequentially connected by third bonding wires; the second chip group includes a fifth chip, a sixth chip, a seventh chip, and an eighth chip stacked in a stepped manner in sequence. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are sequentially connected by fourth bonding wires; wherein, the fifth chip is connected to the chip made by using the redistribution layer technology in the fourth chip group through the second bonding wire. The fluid layer on the lead is disposed between the fourth chip and the fifth chip. The fourth chip is made by using the redistribution layer technology and is connected to the chip located at the uppermost layer in the third chip group through the first bonding wire passing through the fluid layer on the lead.

7. The chip stacking structure according to claim 1, wherein The third chip group includes a ninth chip, a tenth chip, an eleventh chip, and a twelfth chip stacked in a stepped manner in sequence. The ninth chip, the tenth chip, the eleventh chip, and the twelfth chip are sequentially connected by fifth bonding wires. The twelfth chip is connected to the chip made by using the redistribution layer technology in the first chip group through the first bonding wire passing through the fluid layer on the lead.

8. The chip stack structure according to claim 7, wherein, The fourth chip group includes a thirteenth chip, a fourteenth chip, a fifteenth chip, and a sixteenth chip stacked in a stepped manner in sequence. The substrate, the thirteenth chip, the fourteenth chip, the fifteenth chip, and the sixteenth chip are sequentially connected by sixth bonding wires. The sixteenth chip is made by using the redistribution layer technology and is connected to the chip located at the lowermost layer in the second chip group through the second bonding wire.

9. The chip stacking structure according to any one of claims 1 to 8, characterized in that, The substrate and the multiple chips in the first chip group are sequentially connected by third bonding wires. The multiple chips in the second chip group are sequentially connected by fourth bonding wires.

10. The chip stacking structure according to claim 9, characterized in that, The third bonding wires are located on one side of the first chip group away from the third chip group. The fourth bonding wires are located on one side of the second chip group close to the fourth chip group.

11. The chip stack structure according to any one of claims 1 to 8, characterized in that The multiple chips in the third chip group are sequentially connected by fifth bonding wires. The substrate and the multiple chips in the fourth chip group are sequentially connected by sixth bonding wires.

12. The chip stack structure according to claim 11, wherein, The fifth bonding wires are located on one side of the third chip group close to the first chip group. The sixth bonding wires are located on one side of the fourth chip group away from the second chip group.

13. A memory, characterized in that, It includes a main board and the chip stacking structure according to any one of claims 1 to 12, and the chip stacking structure is disposed on the main board.

14. An electronic device, characterized in that, It includes the memory according to claim 13.

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