Chip clamp for static damage test

By designing chip fixtures for electrostatic damage testing and using circuit boards and limiting parts, the anti-static ability test of integrated circuit chips is achieved, solving the damage problem of chips in the existing technology in electrostatic discharge scenarios, and improving the accuracy and reliability of the test.

CN223166777UActive Publication Date: 2025-07-29XINHUO MICRO MEASUREMENT (CHENGDU) TECH CO LTD
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Patent Information

Application Number
CN202421370805.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-06-17
Publication Date
2025-07-29
Estimated Expiration
2034-06-17

AI Technical Summary

Technical Problem

The prior art is difficult to effectively simulate the electrostatic discharge scenarios encountered by integrated circuit chips during actual use, resulting in chip damage.

Method used

Design a chip fixture for electrostatic damage testing, including circuit board, conduction base, mounting base, support base, test section and limit section, and electrically connect through electrostatic test circuit to ensure stable positioning and electrical communication of the chip during the test process, simulating the electrostatic discharge environment.

Benefits of technology

The antistatic ability test of integrated circuit chips is realized to ensure that the chip is not damaged in a simulated electrostatic discharge environment, and improve the accuracy and reliability of the test.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a chip clamp for static damage test, which relates to the technical field of chip test, and comprises a static test circuit electrically connected, a circuit board provided with a conducting seat electrically connected with the static test circuit, and a chip clamp electrically connected with the conducting seat and electrically connected with the static test circuit. The conduction seat is used for being electrically connected with an electrostatic test circuit; a mounting seat; a supporting seat; a test unit; and two limiting parts. According to the utility model, the chip is placed in the support groove of the support seat and is electrically communicated with the top end of the test part, and the test part is communicated with the static test circuit through the conduction seat, so that the static test on the chip is completed, and the antistatic capability of the integrated circuit chip is acquired. In addition, through the arrangement of the limiting part, the electrical communication effect of the chip on the testing part is ensured. Therefore, the purpose of testing the antistatic capability of the integrated circuit chip by simulating the electrostatic discharge environment is effectively achieved.
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Description

Technical Field

[0001] The utility model relates to the technical field of chip testing, in particular to a chip fixture for electrostatic damage testing. Background Art

[0002] During the semiconductor manufacturing and the use of electronic components, electrostatic discharge is a serious problem. Electrostatic discharge refers to the phenomenon that static charges are rapidly transferred between objects with different potentials, usually occurring when a charged object comes into contact with or approaches a grounded object. This phenomenon can generate an instantaneous voltage as high as several thousand volts, causing irreversible damage to precision electronic components, especially integrated circuit chips.

[0003] Therefore, in the initial stage of integrated circuit chip design, it is necessary to simulate various electrostatic discharge scenarios that the chip may encounter during actual use according to the chip's usage environment, and then test the anti-static ability of the integrated circuit chip in the simulated electrostatic discharge environment. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a chip fixture for electrostatic damage testing, which can simulate the electrostatic discharge environment to test the anti-static ability of integrated circuit chips.

[0005] To achieve the above purpose, the utility model adopts the following technical scheme:

[0006] A chip fixture for electrostatic damage testing, including: electrically connected to an electrostatic test circuit, the fixture is electrically connected to the electrostatic test circuit, and the fixture further includes:

[0007] A circuit board, on which a conduction seat is provided, the conduction seat is electrically connected to the electrostatic test circuit, and the conduction seat is used for electrically connecting to the electrostatic test circuit;

[0008] A mounting seat, which is arranged on the circuit board, and a first opening is provided on the mounting seat, and the first opening of the mounting seat is located above the conduction seat;

[0009] A support seat, which is arranged above the mounting seat, the support seat is connected to the mounting seat, and a support groove is provided at the top of the support seat;

[0010] A test part, which penetrates through the support seat, and the test part is electrically connected to the conduction seat;

[0011] Two limiting parts, which are arranged in the support groove, the two limiting parts are symmetrically located on both sides of the top end of the test part, and the mutually remote sides of the two limiting parts are respectively slidably connected to the support seat.

[0012] In an alternative solution, the testing part includes:

[0013] A conducting member, which is disposed through the inside of the support base. A conducting surface is provided at the top of the conducting member, and the conducting surface is electrically connected to the chip.

[0014] A conducting end is provided at the bottom of the conducting member, and the conducting end is electrically connected to the conducting seat.

[0015] In an alternative solution, an insulating sleeve is provided at the first opening of the mounting base, and the insulating sleeve is used to isolate the contact between the mounting base and the conducting member.

[0016] In an alternative solution, first grooves are respectively formed on both sides of the support groove of the support base. The limiting part includes:

[0017] A spring, which is located in the first groove.

[0018] A sliding plate, one end of which is connected to the spring, and the sliding plate is slidably connected to the first groove.

[0019] A limiting plate, one side of which is connected to the other end of the sliding plate, and the other side of the limiting plate is located on one side of the conducting surface of the conducting member.

[0020] In an alternative solution, the mounting base is detachably connected to the circuit board.

[0021] In an alternative solution, it further includes:

[0022] Two clamping members, which are disposed on the circuit board, and the two clamping members are symmetrically arranged on both sides of the conducting seat.

[0023] Two clamping grooves, which are disposed at the bottom of the mounting base, and the two clamping grooves are respectively clamped and connected to the two clamping members.

[0024] The mounting base is detachably connected to the circuit board through the clamping grooves and the clamping members.

[0025] In an alternative solution, the mounting base and the support base are detachably connected.

[0026] In an alternative solution, a plurality of mounting holes are provided at the top of the mounting base, and a plurality of mounting posts are provided at the bottom of the support base. The mounting base and the support base are detachably connected by inserting the plurality of mounting posts into the mounting holes.

[0027] The beneficial effects of the present utility model are:

[0028] In the present utility model, a chip is placed in a support groove of a support base and electrically connected to the top of a test part. At the same time, the test part is connected to an electrostatic test circuit through a conduction base to complete the electrostatic test on the chip and collect the electrostatic resistance ability of the integrated circuit chip. In addition, by providing a limiting part, the electrical connection effect of the chip on the test part is ensured. That is, the purpose of effectively simulating the electrostatic discharge environment to test the electrostatic resistance ability of the integrated circuit chip is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 FIG. is an exploded schematic view of the overall structure of a chip fixture for electrostatic damage testing provided in an embodiment of the present utility model;

[0030] Figure 2 FIG. is a planar cross-sectional view of the overall structure of a chip fixture for electrostatic damage testing provided in an embodiment of the present utility model;

[0031] Figure 3 FIG. is a schematic view of the structure of a limiting part in a chip fixture for electrostatic damage testing provided in an embodiment of the present utility model.

[0032] The marks in the figures are shown as follows:

[0033] 1. Circuit board; 11. Conduction base; 12. Clamping part;

[0034] 2. Mounting base; 21. Clamping groove; 22. Insulating sleeve; 23. Mounting hole;

[0035] 3. Support base; 31. Mounting post; 32. Conducting part; 321. Conducting surface; 322. Conducting end; 33. Support groove;

[0036] 4. Limiting part; 41. Limiting plate; 411. Sliding plate; 42. Spring. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0038] It should be noted that all directional indications (such as up, down, left, right, front, back,...) in the embodiments of the present utility model are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0039] In the present utility model, unless otherwise clearly defined and limited, terms such as "connection" and "fixation" shall be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0040] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present utility model, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and / or" appearing throughout the text includes three parallel scenarios. Taking "A and / or B" as an example, it includes Scenario A, or Scenario B, or the scenario where both A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present utility model.

[0041] Embodiment

[0042] Refer to Figures 1 to 3, in this embodiment of the present utility model, in order to achieve the purpose of simulating an electrostatic discharge environment to test the electrostatic resistance of an integrated circuit chip, a chip fixture for electrostatic damage testing is provided here. The fixture is connected to an electrostatic test circuit to enable the chip to use the electrostatic test circuit on the fixture to test the electrostatic resistance of the integrated circuit chip. The fixture includes: a circuit board 1, a mounting base 2, a support base 3, a test part, and two limiting parts 4. A conducting seat 11 is provided on the circuit board 1. The conducting seat 11 is electrically connected to the electrostatic test circuit and is used to be electrically connected to the electrostatic test circuit to enable the chip to use the electrostatic test circuit on the fixture to test the electrostatic resistance of the integrated circuit chip. The mounting base 2 is arranged on the circuit board 1, and a first opening (not marked in the figure) is provided on the mounting base 2. The first opening of the mounting base 2 is located above the conducting seat 11. The support base 3 is arranged above the mounting base 2. The support base 3 is connected to the mounting base 2, and a support groove 33 is provided at the top of the support base 3. The test part is disposed through the support base 3. The top end of the test part is located inside the support groove 33, and the bottom end of the test part is located at the bottom of the support base 3. The test part is electrically connected to the conducting seat 11 to enable the test part to be electrically connected to the electrostatic test circuit through the conducting seat 11. Two limiting parts 4 are arranged in the support groove 33. The two limiting parts 4 are symmetrically located on both sides of the top end of the test part. The mutually remote sides of the two limiting parts 4 are respectively slidably connected to the support groove 33 to integrally limit the chip located at the top end of the test part and ensure the effect of subsequent testing the electrostatic resistance of the integrated circuit chip of the chip. In this embodiment, the chip is placed in the support groove 33 of the support base 3 and is electrically connected to the top end of the test part. At the same time, the test part is connected to the electrostatic test circuit through the conducting seat 11 to complete the electrostatic test of the chip and collect the electrostatic resistance of the integrated circuit chip. In addition, by setting the limiting parts 4, the electrical connection effect of the chip on the test part is ensured. That is, the purpose of effectively simulating an electrostatic discharge environment to test the electrostatic resistance of an integrated circuit chip is achieved. It should be noted that in this embodiment, the electrostatic test circuit can be correspondingly simulated according to the actual production environment of the chip.

[0043] In this embodiment, the testing unit includes: a conducting member 32. The conducting member 32 is disposed through the inside of the support base 3. A conducting surface 321 is provided at the top of the conducting member 32. The conducting surface 321 is electrically connected to the chip. A conducting end 322 is provided at the bottom of the conducting member 32. The conducting end 322 extends through the first opening on the mounting base 2 to the circuit board 1, and the conducting end 322 is electrically connected to the conducting seat 11, so as to enable the chip to be connected to the electrostatic test circuit through the conducting member 32 and the conducting seat 11. Here, the conducting member 32 is located directly above the conducting seat 11 through the first opening on the mounting base 2, so that the conducting seat 11 is aligned and electrically connected to the conducting end 322 on the conducting member 32, so as to enable the chip to use the electrostatic test circuit on the fixture to test the electrostatic resistance of the integrated circuit chip. In addition, in this embodiment, in order to reduce the influence of the mounting base 2 on the conducting member 32, an insulating sleeve 22 is provided at the first opening of the mounting base 2, and the insulating sleeve 22 is used to isolate the contact between the mounting base 2 and the conducting member 32.

[0044] Referring to Figure 2 and Figure 3 , in this embodiment, first grooves (not marked in the figure) are formed on both sides of the support groove 33 of the support base 3. The two limiting portions 4 are symmetrically disposed on both sides of the conducting surface 321 of the conducting member 32, so as to limit the chip electrically connected to the conducting surface 321 and prevent the chip from shifting during the test. Here, for the convenience of describing the limiting portion 4, one of the limiting portions 4 will be described. Specifically, the limiting portion 4 includes: a spring 42, a sliding plate 411, and a limiting plate 41. The spring 42 is located in the first groove. One end of the sliding plate 411 is connected to the spring 42, and the sliding plate 411 is slidably connected to the first groove. One side of the limiting plate 41 is connected to the other end of the sliding plate 411, and the other side of the limiting plate 41 is located on one side of the conducting surface 321 of the conducting member 32, so as to integrally position the chip located on the conducting surface 321 of the conducting member 32. That is, in this embodiment, the mutually remote sides of the two limiting plates 41 slide in the first groove of the support base 3 through the spring 42, so as to adjust the limiting space between the two limiting plates 41 to meet the requirement of integrally positioning the chip located on the conducting surface 321 of the conducting member 32 and prevent the chip from shifting during the test.

[0045] In this embodiment, in order to ensure that the conducting member 32 on the support base 3 is connected to the conducting base 11 on the circuit board 1, two clamping members 12 are provided on the circuit board 1, and the two clamping members 12 are symmetrically arranged on both sides of the conducting base 11. Clamping grooves 21 are provided on both sides of the bottom of the mounting base 2, and the two clamping grooves 21 are respectively connected to the two clamping members 12 in a clamping manner. That is, the bottom of the mounting base 2 is detachably connected to the clamping members 12 on the circuit board 1 through the two clamping grooves 21, so as to ensure that the first opening on the mounting base 2 is directly above the conducting base 11, and then it can be ensured that the conducting base 11 is in alignment and electrical connection with the conducting end 322 on the conducting member 32, so as to enable the chip to use the electrostatic test circuit on the fixture to test the electrostatic resistance of the integrated circuit chip.

[0046] In this embodiment, in order to facilitate the overall overhaul and maintenance of the fixture, the mounting base 2 and the support base 3 are detachably connected. Specifically, a plurality of mounting holes 23 are provided on the top of the mounting base 2, and a plurality of mounting posts 31 are provided on the bottom of the support base 3, and the mounting posts 31 are inserted into the mounting holes 23. That is, the mounting base 2 and the support base 3 are detachably connected by inserting a plurality of mounting posts 31 into the mounting holes 23. To achieve the convenience of detaching and overhauling between the mounting base 2 and the support base 3.

[0047] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.

Claims

1. A chip fixture for electrostatic damage testing, comprising: The electrostatic test circuit is electrically connected. It is characterized in that the fixture is electrically connected to the electrostatic test circuit, and the fixture further includes: A circuit board, on which a conduction seat is provided. The conduction seat is electrically connected to the electrostatic test circuit and is used for electrically connecting to the electrostatic test circuit; A mounting seat, which is arranged on the circuit board. The mounting seat is provided with a first opening, and the first opening of the mounting seat is located above the conduction seat; A support seat, which is arranged above the mounting seat. The support seat is connected to the mounting seat, and a support groove is provided at the top of the support seat; A test part, which is arranged through the support seat. The test part is electrically connected to the conduction seat; Two limiting parts, which are arranged in the support groove. The two limiting parts are symmetrically located on both sides of the top end of the test part, and the mutually remote sides of the two limiting parts are respectively slidably connected to the support seat.

2. The chip fixture for electrostatic damage testing according to claim 1, characterized in that The test part includes: A conduction piece, which is arranged through the interior of the support seat. A conduction surface is provided at the top of the conduction piece, and the conduction surface is electrically connected to the chip; A conduction end is provided at the bottom of the conduction piece, and the conduction end is electrically connected to the conduction seat.

3. The chip fixture for electrostatic damage testing according to claim 2, characterized in that, An insulating sleeve is provided at the first opening of the mounting seat, and the insulating sleeve is used to isolate the contact between the mounting seat and the conduction piece.

4. The chip fixture for electrostatic damage testing according to claim 2 or 3, characterized in that, First grooves are respectively provided on both sides of the support groove of the support seat. The limiting part includes: A spring, which is located in the first groove; A sliding plate, one end of which is connected to the spring, and the sliding plate is slidably connected to the first groove; A limiting plate, one side of which is connected to the other end of the sliding plate, and the other side of the limiting plate is located on one side of the conduction surface of the conduction piece.

5. A chip fixture for electrostatic damage testing according to claim 1, characterized in that, The mounting seat is detachably connected to the circuit board.

6. The chip fixture for electrostatic damage testing according to claim 5, characterized in that, It further includes: Two clamping parts, which are arranged on the circuit board, and the two clamping parts are symmetrically arranged on both sides of the conduction seat; Two clamping grooves, which are arranged at the bottom of the mounting seat, and the two clamping grooves are respectively clamped and connected to the two clamping parts; The mounting seat is detachably connected to the circuit board through the clamping grooves and the clamping parts.

7. The chip fixture for electrostatic damage testing according to claim 1, wherein, The mounting seat and the support seat are detachably connected.

8. The chip fixture for electrostatic damage testing according to claim 7, characterized in that, A plurality of mounting holes are provided at the top of the mounting seat, and a plurality of mounting posts are provided at the bottom of the support seat. The mounting seat and the support seat are detachably connected by inserting the plurality of mounting posts into the mounting holes.