Electronic paper pixel device, electronic paper and display device
By designing the slotted thin film transistor area B in the electronic paper pixel device, the space occupied by the pixel electrode layer is reduced and the electric field intensity is maintained, and the problem of deterioration of low-temperature optical visual effect of four-color electronic paper is solved, and the display effect is improved without increasing costs.
Patent Information
- Application Number
- CN202422196084.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-09-09
AI Technical Summary
The existing four-color electronic paper with TFT back panel has the problem of deteriorating low-temperature optical visual effect, resulting in white spots appearing in local areas of unit pixels, affecting the overall optical value.
An electronic paper pixel device is designed to reduce the space occupied by the pixel electrode layer and maintain the electric field strength by slotting in the thin film transistor area B, including setting slotting on the pixel electrode layer, with the groove width between 5um and 20um, ensuring that the thin film transistor area B is not covered with ITO or metal coating.
Reduce the probability and intensity of white spots at low temperatures, improve the display effect, and avoid the increase in cost caused by adding additional film layers.
Smart Images
Figure CN223167008U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, and particularly relates to an electronic paper pixel device, an electronic paper, and a display device. Background Art
[0002] An electronic paper is a display screen made using electrophoretic display technology. The electronic paper is formed by coating electronic ink on a thin film, which can be attached to a circuit of thin film transistors (TFT / PET / FPC, etc.). Controlled by a driving IC, it forms a pixel pattern. The electronic paper ink screen display has the characteristics of ultra-low power consumption, low-frequency display, and power saving, and has a wide application market in price tags, advertising signs, and bus stops.
[0003] Each pixel on a TFT-based electronic paper display screen is driven by a thin film transistor (Thin Film Transistor) integrated behind the pixel. A TFT display includes an array substrate (TFT Glass), and a pixel electrode layer (Pixel ITO) corresponding to the electrode layer is provided on the array substrate. The TFT-based electronic paper display screen drives the electronic paper particles by continuously applying a driving waveform voltage to each pixel by a driving IC chip to achieve the effect of displaying an image. Currently, when the electronic paper price tag is upgraded from three colors (black and white, red; black and white, yellow) to four colors (black and white, red, yellow), there is a problem of deteriorated low-temperature optical visual effect, and the display effect needs to be improved. The structure of the pixel electrode layer also affects the display effect.
[0004] With the increasing development speed of the application of electronic paper price tags, the demand of end customers for color electronic paper price tags is becoming stronger and stronger. Among them, the four-color electronic paper (black and white, red, yellow) has attracted much attention. However, currently, when the four-color electronic paper is paired with the existing TFT backplane, there are problems such as Figure 1 and Figure 2 shown in the deteriorated low-temperature optical visual effect. The specific phenomenon is as shown in Figure 1 and Figure 2 where white dots appear in the local area of the unit pixel, which will cause the overall optical value to decrease. The reason for the generation of white dots is that, as shown in Figures 3 to 5 the pixel electrode ITO above the pixel TFT is dug out, resulting in the formation of a weak electric field in the dug-out area, which affects the movement of the particles in the ink capsule, thus generating the white dot phenomenon.
[0005] Glossary: EPD is the abbreviation of the English "electronic paper display", and its Chinese meaning is electronic paper display.
[0006] TFT is the abbreviation of the English "Thin Film Transistor", and its Chinese meaning is thin film field effect transistor; each pixel on a TFT display is driven by a thin film transistor integrated behind it.
[0007] ITO is the abbreviation of the English phrase "Indium Tin Oxide", and its Chinese meaning is indium tin oxide. In this application, the ITO of the electronic paper refers to the conductive film layer material of the transparent conductive film shielding glass, which is mainly ITO (indium tin oxide semiconductor) film. Summary of the Invention
[0008] The technical problem to be solved by this application is to solve the problem in the prior art that, due to the pixel electrode ITO being dug out, a weak electric field is formed in the dug-out area, which affects the movement of particles in the ink capsule, resulting in the appearance of white dots. The pixel structure designed in this application can make the pixel area A of the pixel electrode layer as large as possible, so as to maintain the electric field strength even at low temperatures, reducing the probability and intensity of white dot occurrence.
[0009] The technical solution of this application to solve the above technical problem is an electronic paper pixel device, which is characterized in that it includes a common electrode layer, a pixel capacitor layer, a pixel electrode layer, and a thin-film transistor TFT; there is an isolation insulating layer between the pixel capacitor layer and the pixel electrode layer, and the pixel capacitor layer and the pixel electrode layer are electrically connected through a layer-changing hole that penetrates the above isolation insulating layer; there is an isolation insulating layer between the pixel capacitor layer and the common electrode layer; the output of the thin-film transistor TFT is connected to the pixel capacitor layer; the pixel electrode layer is above the above pixel capacitor layer; the pixel capacitor layer is above the above common electrode layer; the thin-film transistor TFT includes a semiconductor channel region; the above pixel electrode layer includes a pixel region A and a thin-film transistor region B; the pixel region A corresponds to the above pixel capacitor layer; the shape of the pixel region A is the same as that of the pixel capacitor layer; the thin-film transistor region B corresponds to the above thin-film transistor TFT; the thin-film transistor region B includes a slot corresponding to the above semiconductor channel region.
[0010] There are two such slots, and one end of the two slots is connected to the outside.
[0011] The above two slots are parallel to each other.
[0012] There is one such slot, the slot is close to the edge of the above pixel electrode layer, and one end of the slot is connected to the outside.
[0013] There is one such slot, the above semiconductor channel region is two vertical short lines, the slot is formed by two vertical slots connected to form an L shape, and one end of the slot is connected to the outside.
[0014] The above common electrode layer, pixel capacitor layer, and pixel electrode layer are ITO layers, and the slot part of the above thin-film transistor region B has no ITO coverage.
[0015] The above pixel electrode layer is a metal coating, and the slot part of the above thin-film transistor region B has no metal coating coverage.
[0016] The width of the above-mentioned slot is greater than 5um; the width of the above-mentioned slot is less than 20um.
[0017] Another technical solution of the present application to solve the above technical problem may also be an electronic paper, including the electronic paper pixel device as described above.
[0018] Another technical solution of the present application to solve the above technical problem may also be a display device, including the electronic paper as described above.
[0019] Beneficial effect 1 of the technical solution in the present application.
[0020] Beneficial effect 1 of the technical solution in the present application. The thin film transistor region B includes a slot corresponding to the above semiconductor channel region. The slot only corresponds to the semiconductor channel region, which can make the pixel region A of the pixel electrode layer as large as possible, so as to maintain the electric field strength even at low temperatures and reduce the probability and intensity of white dots.
[0021] Beneficial effect 1 of the technical solution in the present application. There are two slots, and one end of the two slots is connected to the outside, which is adapted to the corresponding thin film transistor TFT structure.
[0022] Beneficial effect 1 of the technical solution in the present application. The slots are parallel to each other, which is adapted to the corresponding thin film transistor TFT structure.
[0023] Beneficial effect 1 of the technical solution in the present application. There is one slot, the slot is close to the edge of the above pixel electrode layer, and one end of the slot is connected to the outside, further reducing the occupation of the pixel electrode layer and making the pixel region A of the pixel electrode layer as large as possible.
[0024] Beneficial effect 1 of the technical solution in the present application. The semiconductor channel region is two perpendicular short lines, and the above slot is formed by connecting two perpendicular slots to form an L shape, and one end of the slot is connected to the outside, which is adapted to the corresponding thin film transistor TFT structure.
[0025] Beneficial effect 1 of the technical solution in the present application. The slot part of the above thin film transistor region B has no ITO coverage, which is suitable for ITO application scenarios.
[0026] Beneficial effect 1 of the technical solution in the present application. The slot part of the thin film transistor region B has no metal coating coverage, which is suitable for application scenarios with metal coating coverage.
[0027] Beneficial effect 1 of the technical solution in the present application. The width of the slot is greater than 5um, which can give enough space to the semiconductor channel region. The width of the slot is less than 20um, and it can also minimize the space occupied by the semiconductor channel region, giving enough space to the pixel region to enhance the electric field strength at low temperatures and reduce the display problem of low-temperature white dots. Description of the Drawings
[0028] Figure 1 It is a schematic diagram showing that the optical visual effect of an existing technology electronic paper pixel device deteriorates at low temperatures;
[0029] Figure 2 It is a schematic diagram of the white point of an electronic paper pixel device at low temperatures;
[0030] Figure 3 It is a top view schematic diagram of an electronic paper pixel device in the prior art;
[0031] Figure 4 It is Figure 3 a schematic diagram of the ITO layer of the pixel electrode in
[0032] Figure 5 It is Figure 3 a schematic diagram of the AA cross-section in
[0033] Figure 6 It is a top view schematic diagram of Embodiment 1 of the electronic paper pixel device in the present application;
[0034] Figure 7 It is Figure 6 a schematic diagram of the ITO layer of the pixel electrode in
[0035] Figure 8 It is Figure 6 a schematic diagram of the AA cross-section in
[0036] Figure 9 It is a top view schematic diagram of Embodiment 2 of the electronic paper pixel device in the present application Figure 1 ;
[0037] Figure 10 It is a top view schematic diagram of Embodiment 2 of the electronic paper pixel device in the present application Figure 2 ;
[0038] Figure 11 It is Figure 10 a schematic diagram of the ITO layer of the pixel electrode in
[0039] Figure 12 It is Figure 10 a schematic diagram of the AA cross-section in
[0040] Figure 13 It is a top view schematic diagram of Embodiment 3 of the electronic paper pixel device in the present application;
[0041] Figure 14 It is Figure 13 a schematic diagram of the ITO layer of the pixel electrode in
[0042] Figure 15 It is a display schematic diagram of an electronic paper pixel device at low temperatures. Detailed implementation manners
[0043] The following further details the embodiments of the present application in conjunction with the accompanying drawings.
[0044] It should be noted that the following is a description of the preferred embodiments of the present application, which does not constitute any limitation to the present application. The description of the preferred embodiments of the present application is only for the illustration of the general principles of the present application. The embodiments described in the present application are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.
[0045] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and technical features numbered with Arabic numerals such as 1, 2, 3, etc., as well as numbers such as "A" and "B", are only for descriptive purposes, just for the convenience of explanation, and do not represent the order relationship in time or space; it cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second", and numbered with Arabic numerals such as 1, 2, 3, etc. may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "several" is two or more, unless otherwise specifically defined.
[0046] With the increasingly rapid development of the application of electronic paper price tags, the demand of end customers for color electronic paper price tags is becoming stronger and stronger. Among them, four-color electronic paper (black and white, red and yellow) has attracted much attention. However, at present, when four-color electronic paper is paired with the existing TFT backplane, there is a problem that the low-temperature optical visual effect becomes worse. The specific phenomena are as Figure 1 and Figure 2 shown, white dots appear in the local area of the unit pixel, resulting in a decrease in the overall optical value. The reason for the appearance of white dots is that the pixel electrode ITO above the pixel TFT is dug out, as Figure 3 , Figure 4 and Figure 5 shown; the pixel electrode layer does not cover the entire pixel area. This causes a weak electric field to be formed in the dug-out area, affecting the movement of particles in the ink capsule, and thus the white dot phenomenon occurs. As Figure 4 the pixel electrode ITO layer is missing in the lower left corner. As Figure 5As shown, in the virtual frame area on the left, there is no pixel electrode coverage, so the electric field in this area will weaken, resulting in white dot phenomenon at low temperatures.
[0047] As Figures 6 to 8 shown, in an embodiment of an electronic paper pixel device, it includes a common electrode layer M10, a pixel capacitance layer M30, a pixel electrode layer M50, and a thin film transistor TFT; the thin film transistor TFT is the semiconductor layer M90. There is an isolation insulating layer between the pixel capacitance layer M30 and the pixel electrode layer M50, and the pixel capacitance layer M30 and the pixel electrode layer M50 are electrically connected through a via hole M60 that penetrates the above-mentioned isolation insulating layer; there is an isolation insulating layer between the pixel capacitance layer M30 and the common electrode layer M10; the output of the thin film transistor TFT is connected to the pixel capacitance layer M30; the pixel electrode layer M50 is above the above-mentioned pixel capacitance layer M30; the pixel capacitance layer M30 is above the above-mentioned common electrode layer M10; the thin film transistor TFT includes a semiconductor channel region 280; the above-mentioned pixel electrode layer M50 includes a pixel region A100 and a thin film transistor region B200; the pixel region A100 corresponds to the above-mentioned pixel capacitance layer M30; the shape of the pixel region A100 is the same as that of the pixel capacitance layer M30; the thin film transistor region B200 corresponds to the above-mentioned thin film transistor TFT; the thin film transistor region B200 includes a slot 270 corresponding to the above-mentioned semiconductor channel region 280. Figure 6 The TFT channel region M80 in
[0048] In some embodiments, the above-mentioned common electrode layer M10, pixel capacitance layer M30, and pixel electrode layer M50 are ITO layers, and a part of the slot 270 in the above-mentioned thin film transistor region B200 has no ITO coverage.
[0049] In some embodiments, the above-mentioned pixel electrode layer M50 is a metal coating, and a part of the slot 270 in the above-mentioned thin film transistor region B200 has no metal coating coverage.
[0050] As Figure 7 shown, the above-mentioned slot 270 is two, and one end of the two slots 270 is connected to the outside. The two slots 270 are parallel to each other.
[0051] As Figures 9 to 11 shown, the above-mentioned slot 270 is one, the slot 270 is close to the edge of the above-mentioned pixel electrode layer M50, and one end of the slot 270 is connected to the outside.
[0052] As Figures 13 to 14 shown, the above-mentioned slot 270 is one, the above-mentioned semiconductor channel region 280 is two vertical short lines, the above-mentioned slot 270 is formed by connecting two vertical slots to form an L shape, and one end of the slot 270 is connected to the outside.
[0053] AsFigure 7 , Figure 11 and Figure 14 As shown in Figure 14 , the width of the above-mentioned slot 270 is greater than 5 μm; the width of the above-mentioned slot 270 is less than 20 μm.
[0054] An electronic paper includes the above-mentioned electronic paper pixel device. A display device includes the above-mentioned electronic paper.
[0055] In this application, to solve the problem of deteriorated visual effect at low temperature, optimization design is carried out from the perspective of the TFT backplane for improvement. The currently feasible method is to add an organic photoresist layer to fill back the area of the pixel ITO layer that has been dug out, but this will increase the cost of the TFT backplane and is not conducive to the competitiveness of the product.
[0056] This application mainly improves the low-temperature visual effect by optimizing the design of TFT pixels without adding new film layers. The specific design method is to reduce the distance between pixel electrodes ITO and ITO. For example, Figures 6 to 8 As shown in the pixel design of Scheme 1, only the pixel ITO electrode is dug open in the channel region of the TFT device, and its cross-sectional schematic diagram is as Figure 8 shown. The shape difference of its pixel electrode is as Figure 7 shown. By reducing the spacing between ITOs, the low-temperature visual effect can be significantly improved.
[0057] Scheme 2 is to design the TFT from a "work" shape to a "one" shape. Its planar schematic diagram is as Figures 9 to 11 shown, and its cross-sectional schematic diagram is as Figure 12 shown. The double-gate TFTs are strung together by the gate line, that is, the data line M20, which can effectively optimize the pixel space while avoiding the pixel electrode from being dug open twice. The shape of the pixel electrode layer M50 is as Figure 11 shown.
[0058] Scheme 3 is to design the TFT from a "one" shape to an "L" shape, as Figures 13 to 14 shown, which can effectively avoid the excessive height of the "one"-shaped TFT. The shape of the pixel electrode layer M50 is as Figure 14 shown.
[0059] The above-mentioned new pixel TFT design specifically includes one of the following features but is not limited to a single feature: the gap range of the area where the pixel electrode is dug open is in the range of 5 μm to 20 μm.
[0060] The channel region of the pixel electrode needs to be kept free of pixel electrode (such as: ITO, metal layers such as Mo and Mo alloys, Mo-Al) coverage; the new pixel TFT is designed to be in a one shape or an L shape; the semiconductor layer a_Si of the new pixel TFT is connected in series on one gate line, that is, the data line M20;
[0061] The new pixel TFT device is not limited to being perpendicular to the scan line M70, and can also be parallel to the scan line M70.
[0062] Figure 15 It is a schematic diagram of the display of the electronic paper pixel device in this application at low temperature. The display effect is good, and the white dots in Figure 2 can no longer be seen.
[0063] As shown in the attached drawings, the above are only embodiments of this application, and do not limit the patent scope of this application. Any equivalent structure or equivalent process transformation made by using the content of the application specification and the attached drawings, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of this application.
Claims
1. An electronic paper pixel device, characterized in that, It includes a common electrode layer, a pixel capacitor layer, a pixel electrode layer, and a thin-film transistor (TFT); An isolation insulating layer is included between the pixel capacitor layer and the pixel electrode layer. The pixel capacitor layer and the pixel electrode layer are electrically connected through a via hole that penetrates the isolation insulating layer; An isolation insulating layer is included between the pixel capacitor layer and the common electrode layer; The output of the thin-film transistor (TFT) is connected to the pixel capacitor layer; The pixel electrode layer is above the pixel capacitor layer; The pixel capacitor layer is above the common electrode layer; The thin-film transistor (TFT) includes a semiconductor channel region; The pixel electrode layer includes a pixel region A and a thin-film transistor region B; The pixel region A corresponds to the pixel capacitor layer; The shape of the pixel region A is the same as that of the pixel capacitor layer; The thin-film transistor region B corresponds to the thin-film transistor (TFT); the thin-film transistor region B includes a slot corresponding to the semiconductor channel region.
2. The electronic paper pixel device according to claim 1, wherein There are two slots, and one end of the two slots communicates with the outside.
3. The electronic paper pixel device according to claim 2, wherein The two slots are parallel to each other.
4. The electronic paper pixel device according to claim 1, wherein There is one slot, the slot is close to the edge of the pixel electrode layer, and one end of the slot communicates with the outside.
5. The electronic paper pixel device according to claim 1, wherein There is one slot, the semiconductor channel region is two perpendicular short lines, the slot is formed by connecting two perpendicular slots to form an L shape, and one end of the slot communicates with the outside.
6. The electronic paper pixel device according to any one of claims 1 to 5, wherein The common electrode layer, the pixel capacitor layer, and the pixel electrode layer are ITO layers, and the slot part of the thin-film transistor region B has no ITO coverage.
7. The electronic paper pixel device according to any one of claims 1 to 5, wherein The pixel electrode layer is a metal coating, and the slot part of the thin-film transistor region B has no metal coating coverage.
8. The electronic paper pixel device according to any one of claims 1 to 5, characterized in that, The width of the slot is greater than 5 μm; The width of the slot is less than 20 μm.
9. An electronic paper, wherein It includes the electronic paper pixel device according to any one of claims 1 to 8.
10. A display device, wherein It includes the electronic paper according to claim 9.