Charging and discharging management circuit of energy storage element

Abstract

The utility model discloses a charging and discharging management circuit of an energy storage element. The charging and discharging management circuit comprises an input end Vin, an output end Vout, a straight-through loop, a charging loop, a discharging control loop and an anti-reverse charging circuit, the input end Vin is connected with a power supply, and the output end Vout is connected with a load; the straight-through loop comprises a diode D1 and is used for directly supplying power to a load from an input end vin during power supply; the charging loop comprises a diode D2, a current-limiting resistor R1 and an energy storage capacitor C1, and the power supply charges the energy storage capacitor C1 through the diode D2 and the current-limiting resistor R1; the energy storage capacitor C1 supplies power to the load through the discharge control loop and the anti-reverse charging circuit; the discharge control loop comprises a first switch tube Q1 and a control input port, and the control input port inputs a control signal to turn off the first switch tube Q1 so as to turn off the output of the energy storage capacitor C1. According to the circuit, rapid power-on and rapid power-off functions of the power supply circuit with energy storage elements such as the energy storage capacitor are realized.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, in particular to a charge and discharge management circuit for energy storage components. Background Art

[0002] In some power supply occasions of electronic circuits, there are large energy storage components (such as large capacitor components) in the power supply circuit, which may cause the output of the backend voltage regulator chip to rise slowly, or the output of the voltage regulator chip to drop slowly after power-off. In this power supply situation, the MCU at the power supply backend may freeze and fail to operate.

[0003] In the process, this method brings the following problems:

[0004] 1. The power supply rises too slowly, resulting in poor power-on reset of the MCU.

[0005] 2. The power-off drops too slowly. Due to the different operating voltage ranges of different chips, it may cause abnormal circuit states, or even the MCU freezes or fails to operate. Content of the Utility Model

[0006] To solve the above problems of the prior art, the utility model provides a charge and discharge management circuit for energy storage components. The technical solution is as follows:

[0007] A charge and discharge management circuit for energy storage components includes an input terminal Vin, an output terminal Vout, a direct-through circuit, a charging circuit, a discharge control circuit, and an anti-reverse charging circuit;

[0008] The input terminal Vin is connected to a power supply, and the output terminal Vout is connected to a load;

[0009] The direct-through circuit includes a diode D1 for directly supplying power to the load from the input terminal Vin during power supply; the anode of the diode D1 is connected to the input terminal Vin, and the cathode of the diode D1 is connected to the output terminal Vout;

[0010] The charging circuit includes a diode D2, a current-limiting resistor R1, and an energy storage capacitor C1; the power supply charges the energy storage capacitor C1 through the diode D2 and the current-limiting resistor R1;

[0011] The energy storage capacitor C1 supplies power to the load through the discharge control circuit and the anti-reverse charging circuit;

[0012] The discharge control circuit includes a first switching transistor Q1 and a control input port, and the control input port inputs a control signal to turn off the first switching transistor Q1 to turn off the output of the energy storage capacitor C1.

[0013] Further, the first switching transistor Q1 is a PMOS transistor, the source of the PMOS transistor is connected to the positive electrode of the energy storage element; the drain of the PMOS transistor is connected to the input end of the anti-reverse charging circuit.

[0014] Further, at least one discharge control branch is connected to the control end of the first switching transistor Q1. The discharge control branch includes a second switching transistor, whose input end is connected to the control end of the first switching transistor Q1; its output end is grounded, and its control end is connected to the control input port.

[0015] Further, the second switching transistor is an NPN transistor or an NMOS transistor.

[0016] Further, a delay circuit is further included. The output end of the delay circuit is connected to the control end of the first switching transistor Q1, and is used to realize the voltage slow-down control of the control end of the first switching transistor Q1.

[0017] Further, the delay circuit includes a resistor R2 and a capacitor C2. One end of the resistor R2 is connected to the positive electrode of the energy storage capacitor C1, the other end of the resistor R2 is connected to one end of the capacitor C2 and the control end of the first switching transistor Q1, and the other end of the capacitor C2 is grounded.

[0018] Further, the anti-reverse charging circuit includes a MOS transistor Q2, a switching transistor Q3 and a switching transistor Q4; the input end of the anti-reverse charging circuit is connected to the drain of the MOS transistor Q2 and the emitter of the switching transistor Q3; the output end of the anti-reverse charging circuit is connected to the source of the MOS transistor Q2 and the emitter of the switching transistor Q4; the base of the switching transistor Q3 is connected to the collector of the switching transistor Q3 and the base of the switching transistor Q4; the collector of the switching transistor Q3 is grounded through a resistor R5; the collector of the switching transistor Q4 is connected to the gate of the MOS transistor Q2 and is grounded through a resistor R6.

[0019] Further, the anti-reverse charging circuit includes a diode D5, and the cathode of the diode D5 is connected to the output end Vout.

[0020] Further, the charge and discharge management circuit of the energy storage element further includes a power-off detection circuit. The input end of the power-off detection circuit is connected to the input end Vin, and the output end of the power-off detection circuit is connected to the control input port of the discharge control loop, and is used to output a high-level signal when it detects that the input voltage is less than the set threshold.

[0021] The utility model realizes the following technical effects:

[0022] This circuit realizes the functions of rapid power - on and rapid power - off of a power - supply circuit with energy - storage components such as an energy - storage capacitor. Thus, it solves the problem that the power - supply rise is too slow, resulting in poor power - on reset of the MCU, and the problem that the power - off decline is too slow, leading to abnormal circuit states and even the MCU crashing and being unable to operate. Description of the Drawings

[0023] Figure 1 is the system block diagram of the charge - discharge management circuit of the energy - storage component of the present utility model;

[0024] Figure 2 is the first embodiment of the charge - discharge management circuit of the energy - storage component of the present utility model;

[0025] Figure 3 is the second embodiment of the charge - discharge management circuit of the energy - storage component of the present utility model;

[0026] Figure 4 is the third embodiment of the charge - discharge management circuit of the energy - storage component of the present utility model;

[0027] Figure 5 is an example of a power - down detection circuit. Detailed Embodiments

[0028] To further illustrate the embodiments, the present utility model provides drawings. These drawings are part of the disclosure of the present utility model, mainly used to illustrate the embodiments, and can be combined with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, those of ordinary skill in the art should be able to understand other possible implementation manners and the advantages of the present utility model.

[0029] Now, the present utility model will be further described in combination with the drawings and detailed embodiments.

[0030] As Figure 1 shown, the present utility model provides a charge - discharge management circuit for an energy - storage component, mainly including circuits such as diode D1, diode D2, charging current - limiting resistor R1, energy - storage capacitor C1, discharge control loop 10, and anti - reverse - charge circuit 20. Among them:

[0031] Diode D1 constitutes a direct - through circuit. Diode D1 is connected between the input terminal Vin and the output terminal Vout of the charge - discharge circuit of energy - storage capacitor C1, so that during the slow - rising charging process of energy - storage capacitor C1, the output terminal Vout can directly obtain voltage from the input terminal Vin through diode D1, enabling the voltage of the output terminal Vout to rise rapidly, effectively solving the problem of poor power - on reset of the MCU caused by too slow power - supply rise.

[0032] The diode D2, resistor R1, and energy storage capacitor form a charging circuit, and the power supply supplies power to the energy storage capacitor C1 through the diode D2 and resistor R1. The diode D2 is an anti-reverse connection diode to prevent the electricity of the energy storage capacitor C1 from flowing back and discharging from the Vin terminal when the Vin voltage drops.

[0033] Preferably, the diode D2 uses a high-power, low-voltage-drop Schottky rectifier diode.

[0034] The resistor R1 is a charging current-limiting resistor, and the resistance value and rated power value of the resistor can be set according to the actual circuit requirements, which can effectively reduce the requirement for the instantaneous current output of the power supply device and achieve better applicability.

[0035] The discharge control circuit 10 includes a switching device and a control input port. A control signal can be input through the control input port to turn off the switching device to turn off the output of the energy storage capacitor C1, solving the abnormal problem caused by the slow power-down of the output terminal Vout. This control input port can be controlled by the backend MCU or connected to the power-down detection circuit at the front-end Vin input to respond to the power-down. At the same time, controlling the energy storage element to turn off the output also has an energy-saving effect and reduces unnecessary energy storage consumption.

[0036] The anti-reverse charging circuit prevents the output terminal Vout from reverse charging the energy storage capacitor C1.

[0037] Embodiment 1:

[0038] In this embodiment, the discharge control circuit consists of Q1, R2, C2, Q5, Q6, R4, R7, R8, R3, etc. Among them, Q5, R4, R7 and R3, R8, Q6 form two parallel discharge branches, which are respectively controlled by the discharge control signals Ctrl1 and Ctrl2. The discharge control signals Ctrl1 and Ctrl2 can be provided by the MCU or other protection circuits.

[0039] In this embodiment, Q1 uses a PMOS transistor. Since the PMOS transistor has a body diode for circuit protection, for effectively cutting off the output of the energy storage capacitor, when the PMOS transistor is applied, its source electrode is used as the input terminal and the drain electrode is used as the output terminal.

[0040] In this embodiment, a delay circuit is also included. The delay circuit consists of R2 and C2, and the delay turn-off time can be set to provide multi-level power voltage protection requirements.

[0041] In this embodiment, the delay circuit can also adopt a chip scheme similar to NE555 for delay triggering, but it may increase the energy consumption of the energy storage element.

[0042] In this embodiment, the anti - reverse charging circuit consists of Q2, Q3, Q4, R5, and R6. The connection relationship is as follows: Q2 is a PMOS transistor, Q3 and Q4 are PNP bipolar transistors; the output end of the discharge control loop is connected to the drain of Q2 and the emitter of Q3; the output end Vout is connected to the source of Q2 and the emitter of Q4; the bases of Q3 and Q4 are connected and also connected to the collector of Q3; the collector of Q3 is grounded through the resistor R5; the collector of Q4 is connected to the gate of Q2 and grounded through the resistor R6. In this circuit, Q2 can prevent the reverse charging of the output end Vout to the energy storage element; Q2 uses a PMOS transistor with a low on - resistance, which can achieve a smaller voltage drop output, reduce heat loss, and improve efficiency. The functions of Q3 and Q4 are to control the gate voltage of Q2 to achieve the control of the on - and off - states of Q2. At the same time, Q3 and Q4 use bipolar transistors, which can form a stable voltage difference of 0.7V between their bases and emitters; since the bases of Q3 and Q4 are connected together, when the drain voltage of Q2 is higher than the source voltage of Q2, the base voltage of Q3 is lower than the emitter of Q3, and then Q3 conducts. Since the base and collector of Q3 are connected together and also connected to the base of Q4, the conduction of Q3 clamps the base voltage of Q3 (which is also the base of Q4) to the drain voltage of Q2 minus 0.7V. Since the drain voltage of Q2 is higher than the source voltage of Q2 at this time, the voltage difference between the base and emitter of Q4 is less than 0.7V, and Q4 is in the off - state. Therefore, the gate voltage of Q2 is at a low level (pulled down to ground by the resistor), making Q2 conduct and output externally; when the drain voltage of Q2 is lower than the source voltage of Q2, the voltage between the base and emitter of Q4 is equal to 0.7V, so Q4 is in the on - state and Q3 is in the off - state (the voltage difference between the base and emitter of Q3 is less than the conduction voltage), so the gate voltage of Q2 is at a high level (the source voltage of Q2 minus the conduction voltage drop of Q4), making Q2 in the cut - off state and closing the reverse - charging path. In addition, by selecting appropriate resistance values of R5 and R6, the self - discharge current of the energy storage element circuit can be controlled.

[0043] Embodiment 2:

[0044] As Figure 3 shown, in this embodiment, the anti - reverse charging circuit 20 consists of the diode D5. The anode of D5 is connected to the output end of the discharge control loop, and the cathode of D5 is connected to the output end Vout. Preferably, the diode D5 is a Schottky rectifier diode with a low voltage drop.

[0045] Under the allowable charging loss, the switching device Q7 in the main circuit of the discharge control loop can also be a power bipolar transistor.

[0046] In this embodiment, more discharge branches can be set to achieve more flexible discharge output control. The switching devices Q8, Q9, Q10, and Q11 of the discharge branches can be bipolar transistors or MOS transistors.

[0047] Embodiment 3:

[0048] As Figure 4 shown, the charge and discharge management circuit of this energy storage element further includes a power-down detection circuit 30, and the power-down signal generated by the power-down detection circuit 30 is used as a discharge control signal or a kind of turn-off output of the energy storage capacitor C1 for the discharge control signal. As Figure 5 shown, a specific circuit example of a simple power-down detection circuit 30 is given, where Vin is the power supply and Ctrl is the discharge control signal.

[0049] The utility model achieves the following technical effects:

[0050] This circuit realizes the functions of rapid power-on and rapid power-off of the power supply circuit with energy storage elements such as energy storage capacitors. Thus, it solves the problem that the power supply rises too slowly, resulting in poor power-on reset of the MCU, and the problem that the circuit state is abnormal due to too slow power-off descent, and even the problem that the MCU crashes and cannot operate.

[0051] Although the utility model is specifically shown and described in combination with the preferred embodiments, those skilled in the art should understand that various changes can be made to the utility model in terms of form and details without departing from the spirit and scope of the utility model defined by the appended claims, and all of them are within the protection scope of the utility model.

Claims

1. A charge-discharge management circuit for an energy storage element, characterized in that: It includes an input terminal Vin, an output terminal Vout, a direct-through circuit, a charging circuit, a discharge control circuit, and an anti-reverse charging circuit; The input terminal Vin is connected to a power supply, and the output terminal Vout is connected to a load; The direct-through circuit includes a diode D1, which is used to directly supply power to the load from the input terminal Vin during power supply; the anode of the diode D1 is connected to the input terminal Vin, and the cathode of the diode D1 is connected to the output terminal Vout; The charging circuit includes a diode D2, a current-limiting resistor R1, and an energy storage capacitor C1; the power supply charges the energy storage capacitor C1 through the diode D2 and the current-limiting resistor R1; The energy storage capacitor C1 supplies power to the load through the discharge control circuit and the anti-reverse charging circuit; The discharge control circuit includes a first switching tube Q1 and a control input port, and a control signal is input to the control input port to turn off the first switching tube Q1 to turn off the output of the energy storage capacitor C1.

2. The charge and discharge management circuit of the energy storage element according to claim 1, characterized in that: The first switching tube Q1 is a PMOS tube, and the source of the PMOS tube is connected to the positive pole of the energy storage element; the drain of the PMOS tube is connected to the input end of the anti-reverse charging circuit.

3. The charge and discharge management circuit of the energy storage element according to claim 1, characterized in that: At least one discharge control branch is connected to the control end of the first switching tube Q1. The discharge control branch includes a second switching tube, and its input end is connected to the control end of the first switching tube Q1; Its output end is grounded, and its control end is connected to the control input port.

4. The charge and discharge management circuit of the energy storage element according to claim 3, wherein: The second switching tube is an NPN triode or an NMOS tube.

5. The charge and discharge management circuit of the energy storage element according to claim 1, characterized in that: It further includes a delay circuit, and the output end of the delay circuit is connected to the control end of the first switching tube Q1, which is used to realize the voltage slow-down control of the control end of the first switching tube Q1.

6. The charge and discharge management circuit of the energy storage element according to claim 5, characterized in that: The delay circuit includes a resistor R2 and a capacitor C2. One end of the resistor R2 is connected to the positive pole of the energy storage capacitor C1, the other end of the resistor R2 is connected to one end of the capacitor C2 and the control end of the first switching tube Q1, and the other end of the capacitor C2 is grounded.

7. The charge and discharge management circuit of the energy storage element according to claim 1, characterized in that: The anti-reverse charging circuit includes a MOS tube Q2, a switching tube Q3, and a switching tube Q4; the input end of the anti-reverse charging circuit is connected to the drain of the MOS tube Q2 and the emitter of the switching tube Q3; the output end of the anti-reverse charging circuit is connected to the source of the MOS tube Q2 and the emitter of the switching tube Q4; the base of the switching tube Q3 is connected to the collector of the switching tube Q3 and the base of the switching tube Q4; the collector of the switching tube Q3 is grounded through a resistor R5; the collector of the switching tube Q4 is connected to the gate of the MOS tube Q2 and is grounded through a resistor R6.

8. The charge and discharge management circuit of the energy storage element according to claim 1, characterized in that: The anti-reverse charging circuit includes a diode D5, and the cathode of the diode D5 is connected to the output terminal Vout.

9. The charge and discharge management circuit of the energy storage element according to claim 1, wherein: The diode D2 is a Schottky rectifier diode.

10. The charge and discharge management circuit of the energy storage element according to claim 1, characterized in that: It further includes a power-down detection circuit. The input end of the power-down detection circuit is connected to the input terminal Vin, and the output end of the power-down detection circuit is connected to the control input port of the discharge control circuit, which is used to output a high-level signal when it detects that the input voltage is less than a set threshold.

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