Control circuit
By using on-chip soft start capacitors, especially soft start capacitors of the supra-level and below types, high cost and packaging problems caused by large capacity capacitors on the off-chip are solved, and a low-cost and easy-to-package circuit design is achieved.
Patent Information
- Application Number
- CN202422286589.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-09-19
AI Technical Summary
In the prior art, large capacity capacitors on the chip result in high production costs and difficult packaging, which cannot effectively reduce the production costs of the circuit.
Use on-chip soft start capacitors, especially soft start capacitors of the supra-level and below types, to slowly increase the total output voltage by controlling the voltage value of the soft start capacitor to avoid overshoot.
It reduces production costs and is easy to package, achieving safe and reliable operation of the circuit.
Smart Images
Figure CN223168231U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of circuits, and in particular to a control circuit for reducing costs. Background Art
[0002] With the continuous development of technology, the living and production levels of people are also constantly improving. Among them, circuits have been widely used in all walks of life, greatly facilitating people's production and life. In order to supply a suitable voltage to a specific circuit, a modulation circuit is required to modulate the input voltage to obtain a suitable output voltage so that the specific circuit can operate normally. When powering on, a large peak current is likely to occur, and the peak current will damage the subsequent circuit. To avoid overshoot, the modulation circuit needs to cooperate with an off-chip large-capacitance capacitor to make the output voltage rise slowly to ensure the safety of the subsequent circuit.
[0003] However, in the existing solutions, the off-chip large-capacitance capacitor at the nano-farad level is in an off-chip form, which results in a higher production cost and is not easy to package. Utility Model Content
[0004] The embodiments of the present application provide a control circuit for reducing costs.
[0005] In the first aspect of the embodiments of the present application, a control circuit is provided, including: a soft start module, a drive module, a first resistor, and a second resistor;
[0006] The drive input terminal of the drive module is used as the total input terminal of the control circuit, the output terminal of the drive module is used as the total output terminal of the control circuit, the first end of the first resistor is connected to the total output terminal, and the second end of the first resistor is grounded through the second resistor;
[0007] The feedback input terminal of the drive module is connected to the second end of the first resistor, the reference input terminal of the drive module is used to receive a preset reference voltage signal, and the soft start input terminal of the drive module is connected to the soft start module. Among them, a soft start capacitor at the picofarad level or below is provided in the soft start module, so that when the voltage value at the feedback input terminal is less than the value of the reference voltage signal, the voltage value of the soft start capacitor is controlled to make the voltage value at the soft start input terminal rise slowly, and then make the voltage value at the total output terminal rise slowly.
[0008] Optionally, the drive module includes: an error amplification sub-module and a drive sub-module;
[0009] The first error input terminal of the error amplification sub-module serves as the soft start input terminal. The error amplification sub-module is connected to the soft start module through the first error input terminal. The second error input terminal of the error amplification sub-module serves as the reference input terminal for receiving the reference voltage signal. The third error input terminal of the error amplification sub-module serves as the feedback input terminal. The error amplification sub-module is connected to the second end of the first resistor through the third error input terminal;
[0010] The output terminal of the error amplification sub-module is connected to the first input terminal of the drive sub-module. The second input terminal of the drive sub-module serves as the total input terminal. The output terminal of the drive sub-module serves as the output terminal of the drive module.
[0011] Optionally, the drive sub-module includes: a power transistor;
[0012] The gate of the power transistor is connected to the output terminal of the error amplification sub-module. The source of the power transistor serves as the total input terminal. The drain of the power transistor serves as the total output terminal. The drain of the power transistor is connected to the first end of the first resistor.
[0013] Optionally, the drive sub-module includes: a first comparator, an RS flip-flop, a first drive unit, a second drive unit, a first Nmos transistor, a second Nmos transistor, a first capacitor, a second capacitor, and a first inductor;
[0014] The inverting input terminal of the first comparator is used to receive the current detection signal. The non-inverting input terminal of the first comparator serves as the first input terminal of the drive sub-module. The non-inverting input terminal of the first comparator is connected to the output terminal of the error amplification sub-module. The output terminal of the first comparator is respectively connected to the input terminals of the first drive unit and the second drive unit. The output terminal of the first drive unit is respectively connected to the first end of the first capacitor and the gate of the first Nmos transistor. The output terminal of the second drive unit is connected to the gate of the second Nmos transistor. The drain of the first Nmos transistor serves as the total input terminal. The source of the first Nmos transistor is respectively connected to the second end of the first capacitor, the first end of the first inductor, and the drain of the second Nmos transistor. The source of the second Nmos transistor is grounded. The second end of the first inductor is connected to the first end of the second capacitor. The second end of the second capacitor is grounded. The first end of the second capacitor serves as the total output terminal.
[0015] Optionally, the error amplification sub-module includes: a first Pmos transistor, a second Pmos transistor, a third Pmos transistor, a third Nmos transistor, a fourth Nmos transistor, a fifth Nmos transistor, a first current source, and a second current source;
[0016] The negative terminals of the first current source and the second current source are both connected to the VDD terminal. The positive terminal of the first current source is respectively connected to the sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor. The gate of the first PMOS transistor serves as the soft-start input terminal and is connected to the soft-start module. The gate of the second PMOS transistor serves as the reference input terminal. The gate of the third PMOS transistor serves as the feedback input terminal and is connected to the second end of the first resistor. The drain of the first PMOS transistor is respectively connected to the drains of the second PMOS transistor, the drain of the third NMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth NMOS transistor. The drain of the third PMOS transistor is respectively connected to the drain of the fourth NMOS transistor and the gate of the fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the positive terminal of the second current source. The sources of the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are all grounded. The drain of the fifth NMOS transistor serves as the output terminal of the error amplification sub-module and is connected to the drive sub-module.
[0017] Optionally, the soft-start module includes: an oscillator and a soft-start sub-module;
[0018] The soft-start sub-module is respectively connected to the oscillator and the drive module. The soft-start capacitor is disposed in the soft-start sub-module. The soft-start sub-module is configured to receive the pulse signal input by the oscillator and slowly charge the soft-start capacitor based on the pulse signal, so that the voltage value at the soft-start input terminal rises slowly.
[0019] Optionally, the soft-start sub-module includes: a soft-start PMOS transistor, a soft-start current source, and the soft-start capacitor;
[0020] The gate of the soft-start PMOS transistor is connected to the oscillator. The source of the soft-start PMOS transistor is connected to the VDD terminal. The drain of the soft-start PMOS transistor is connected to the negative terminal of the soft-start current source. The positive terminal of the soft-start current source is grounded through the soft-start capacitor, and the positive terminal of the soft-start current source is connected to the drive module.
[0021] Optionally, the oscillator includes: a inverters;
[0022] The a inverters are connected in series. The input terminal of the first inverter is connected to the output terminal of the last inverter. The output terminal of the last inverter serves as the output terminal of the oscillator and is connected to the soft-start sub-module. Wherein, a is an odd number greater than 0. If a ≥ 3, the output terminal of the b-th inverter is connected to the input terminal of the (b + 1)-th inverter, and b is a positive integer less than a.
[0023] Optionally, the oscillator further includes: c D flip-flops;
[0024] The input terminal of each of the D flip-flops is connected to its respective inverted output terminal. The clock terminal of the first D flip-flop is connected to the output terminal of the last inverter. The positive output terminal of the last D flip-flop is connected to the soft start sub-module. Wherein, c is a positive integer. If c≥2, the positive output terminal of the d-th D flip-flop is connected to the clock terminal of the (d + 1)-th D flip-flop, and d is a positive integer less than c.
[0025] Optionally, the oscillator further includes: at least one control branch, and the control branch includes a branch capacitor and a branch Nmos transistor;
[0026] In each of the control branches, the gate of the branch Nmos transistor is connected to an external control, the source of the branch Nmos transistor is grounded, and the drain of the branch Nmos transistor is connected to the output terminal of the last inverter through the branch capacitor.
[0027] As can be seen from the above technical solutions, the embodiments of the present application have the following advantages:
[0028] A soft start module is provided in the control circuit of the present application. The soft start capacitor in the soft start module is of a picofarad level or less type, and the soft start capacitor is in the form of an on-chip capacitor. Controlling the voltage value of the soft start capacitor can control the voltage value of the total output terminal. This makes the production cost relatively low and easy to package. Description of the Drawings
[0029] Figure 1 It is a schematic diagram of an embodiment of a control circuit disclosed in the present application;
[0030] Figure 2 It is a schematic diagram of another embodiment of a control circuit disclosed in the present application;
[0031] Figure 3 It is a schematic diagram when the control circuit of the present application is an LDO circuit;
[0032] Figure 4 It is a schematic diagram when the control circuit of the present application is a DC-DC circuit;
[0033] Figure 5 It is a schematic diagram of the error amplification sub-module of the present application;
[0034] Figure 6 It is a schematic diagram of the soft start sub-module of the present application;
[0035] Figure 7 It is a schematic diagram of an oscillator without digital control function of the present application;
[0036] Figure 8Schematic diagram of an oscillator with digital control function for this application;
[0037] Figure 9 Schematic diagram of the simulation result for this application. Detailed implementation manners
[0038] The following further elaborates on this application in conjunction with the accompanying drawings.
[0039] The embodiment of this application provides a control circuit for cost reduction.
[0040] In order for a specific circuit module to operate properly, an appropriate voltage needs to be provided for it. In existing solutions, in order to avoid overshoot, an off-chip large-capacity capacitor is used to make the input voltage value of the specific circuit rise slowly. However, the off-chip large-capacity capacitor in this solution is in an off-chip form and has a large capacity, resulting in higher production costs and increased packaging difficulty. To solve the above problems, this application provides a control circuit. The soft-start capacitor included in the soft-start module of the control circuit is in an on-chip form and has a small capacity, which is of the picofarad level and below, enabling lower production costs and easier packaging while meeting the soft-start requirement.
[0041] To enable those skilled in the art to better understand the solution of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only a part of the embodiments of this invention, rather than all of the embodiments. Based on the embodiments of this invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this invention.
[0042] The terms "first", "second", "third", "fourth", etc. in the specification and claims of this invention and the above accompanying drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order different from that shown or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.
[0043] The following describes a control circuit of this application. Please refer to Figure 1 , an embodiment of a control circuit of this application includes: a soft-start module, a drive module, a first resistor, and a second resistor;
[0044] The drive input terminal of the drive module serves as the total input terminal of the control circuit, the output terminal of the drive module serves as the total output terminal of the control circuit, the first end of the first resistor is connected to the total output terminal, and the second end of the first resistor is grounded through the second resistor;
[0045] The feedback input terminal of the drive module is connected to the second end of the first resistor. The reference input terminal of the drive module is used to receive a preset reference voltage signal. The soft start input terminal of the drive module is connected to the soft start module. Among them, a soft start capacitor of picofarad level or below is provided in the soft start module. When the voltage value at the feedback input terminal is less than the value of the reference voltage signal, the voltage value of the soft start capacitor is controlled so that the voltage value at the soft start input terminal rises slowly, and then the voltage value at the total output terminal rises slowly.
[0046] The working principle of the control circuit in this embodiment is as follows: When powered on, there is an input signal at the total input terminal, the soft start module starts to work, and a reference voltage is input to the reference input terminal of the drive module. The drive module compares the voltage values at both ends of the reference input terminal and the feedback input terminal. If the voltage at the reference input terminal is larger, the voltage value at the total output terminal is controlled in combination with the signal at the soft start input terminal. Since the soft start capacitor is set to rise slowly, the voltage value at the output terminal of the drive module also rises slowly until the voltage values at both ends of the reference input terminal and the feedback input terminal are equal. At this time, the voltage value at the total output terminal remains unchanged.
[0047] In the embodiment of the present application, a soft start module is provided in the control circuit. The soft start capacitor in the soft start module is of picofarad level or below type, and the soft start capacitor is in the form of on-chip. Controlling the voltage value of the soft start capacitor can control the voltage value at the total output terminal. This makes the production cost lower and is easy to package.
[0048] Please refer to Figures 2 to 9 , Another embodiment of a control circuit of the present application includes: a soft start module, a drive module, a first resistor R1, and a second resistor R2;
[0049] The drive input terminal of the drive module serves as the total input terminal of the control circuit, the output terminal of the drive module serves as the total output terminal of the control circuit, the first end of the first resistor R1 is connected to the total output terminal, and the second end of the first resistor R1 is grounded through the second resistor R2. Among them, the total input terminal is the VIN terminal, and the total output terminal is the VOUT terminal. The drive module is used to provide voltage for the subsequent circuit (i.e., the voltage at the VOUT terminal), and the soft start module can implement soft start control to prevent the voltage at the VOUT terminal from rising too fast.
[0050] The feedback input terminal VFB of the driving module is connected to the second terminal of the first resistor R1. The reference input terminal VREF of the driving module is used to receive a preset reference voltage signal. The soft start input terminal VST of the driving module is connected to the soft start module. Among them, a soft start capacitor CSS of picofarad level and below is provided in the soft start module. When the voltage value of the feedback input terminal VFB is less than the value of the reference voltage signal, the voltage value of the soft start capacitor CSS is controlled to make the voltage value of the soft start input terminal VST rise slowly, and then the voltage value of the total output terminal rises slowly. Specifically, the value of the reference voltage signal needs to be determined according to the required voltage value of the total output terminal and the resistance values of the first resistor R1 and the second resistor R2. Based on the voltage division principle, it can be obtained that the voltage value of the feedback input terminal VFB is the real-time voltage value of the second resistor R2.
[0051] Among them, the internal structure of the driving module can be any type, and specific details are not limited here. For the convenience of understanding, one implementation method is used for illustration in this embodiment. Please refer to Figure 2 , in this embodiment, the driving module includes: an error amplification sub-module and a driving sub-module;
[0052] The first error input terminal of the error amplification sub-module serves as the soft start input terminal VST. The error amplification sub-module is connected to the soft start module through the first error input terminal. The second error input terminal of the error amplification sub-module serves as the reference input terminal VREF for receiving the reference voltage signal. The third error input terminal of the error amplification sub-module serves as the feedback input terminal VFB. The error amplification sub-module is connected to the second terminal of the first resistor R1 through the third error input terminal;
[0053] The output terminal of the error amplification sub-module is connected to the first input terminal of the driving sub-module. The second input terminal of the driving sub-module serves as the total input terminal. The output terminal of the driving sub-module serves as the output terminal of the driving module.
[0054] The driving sub-module can have various structural types, and specific details are not limited here. Please refer to Figure 3 , if the control circuit is an LDO circuit, the driving sub-module includes: a power transistor P;
[0055] The gate of the power transistor P is connected to the output terminal of the error amplification sub-module. The source of the power transistor P serves as the total input terminal. The drain of the power transistor P serves as the total output terminal. The drain of the power transistor P is connected to the first terminal of the first resistor R1. Specifically, when the voltage value at the VFB terminal is smaller than that at the VREF terminal, the gate level of the power transistor P is at a low level, the power transistor P is turned on, and the voltage at the VOUT terminal rises slowly with the voltage at the VST terminal.
[0056] Please refer to Figure 4 , if the control circuit is a DC-DC circuit, the driving sub-module includes: a first comparator B1, an RS flip-flop, a first driving unit, a second driving unit, a first Nmos transistor Q1, a second Nmos transistor Q2, a first capacitor C1, a second capacitor C2, and a first inductor L1;
[0057] The inverting input terminal of the first comparator B1 is used to receive a current detection signal. The non-inverting input terminal of the first comparator B1 serves as the first input terminal of the driving sub-module. The non-inverting input terminal of the first comparator B1 is connected to the output terminal of the error amplification sub-module. The output terminal of the first comparator B1 is respectively connected to the input terminals of the first driving unit and the second driving unit. The output terminal of the first driving unit is respectively connected to the first terminal of the first capacitor C1 and the gate of the first Nmos transistor Q1. The output terminal of the second driving unit is connected to the gate of the second Nmos transistor Q2. The drain of the first Nmos transistor Q1 serves as the total input terminal. The source of the first Nmos transistor Q1 is respectively connected to the second terminal of the first capacitor C1, the first terminal of the first inductor L1, and the drain of the second Nmos transistor Q2. The source of the second Nmos transistor Q2 is grounded. The second terminal of the first inductor L1 is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is grounded. The first terminal of the second capacitor C2 serves as the total output terminal. Among them, the type of the switching transistor can be replaced, and specific details are not limited here.
[0058] For ease of understanding, in this embodiment, the implementation manner of the driving sub-module corresponding to the case where the control circuit is an LDO circuit is described.
[0059] Specifically, please refer to Figure 5 , in one implementation manner, the error amplification sub-module includes: a first Pmos transistor Q3, a second Pmos transistor Q4, a third Pmos transistor Q5, a third Nmos transistor Q6, a fourth Nmos transistor Q7, a fifth Nmos transistor Q8, a first current source, and a second current source;
[0060] The negative terminals of the first current source and the second current source are both connected to the VDD terminal. The positive terminal of the first current source is respectively connected to the source electrodes of the first PMOS transistor Q3, the second PMOS transistor Q4, and the third PMOS transistor Q5. The gate of the first PMOS transistor Q3 serves as the soft-start input terminal VST and is connected to the soft-start module. The gate of the second PMOS transistor Q4 serves as the reference input terminal VREF. The gate of the third PMOS transistor Q5 serves as the feedback input terminal VFB and is connected to the second end of the first resistor R1. The drain of the first PMOS transistor Q3 is respectively connected to the drain of the second PMOS transistor Q4, the drain of the third NMOS transistor Q6, the gate of the third NMOS transistor Q6, and the gate of the fourth NMOS transistor Q7. The drain of the third PMOS transistor Q5 is respectively connected to the drain of the fourth NMOS transistor Q7 and the gate of the fifth NMOS transistor Q8. The drain of the fifth NMOS transistor Q8 is connected to the positive terminal of the second current source. The source electrodes of the third NMOS transistor Q6, the fourth NMOS transistor Q7, and the fifth NMOS transistor Q8 are all grounded. The drain of the fifth NMOS transistor Q8 serves as the output terminal of the error amplification sub-module and is connected to the drive sub-module.
[0061] It can be understood that the soft-start module can be any type of structure, and specific details are not limited here. For the sake of understanding, this embodiment is described in one implementation manner, that is, the soft-start module includes: an oscillator and a soft-start sub-module;
[0062] The soft-start sub-module is respectively connected to the oscillator and the drive module. The soft-start capacitor CSS is disposed in the soft-start sub-module. The soft-start sub-module is used to receive the pulse signal input by the oscillator and slowly charge the soft-start capacitor CSS based on the pulse signal, so that the voltage value of the soft-start input terminal VST slowly rises.
[0063] Specifically, please refer to Figure 6 , the soft-start sub-module includes: a soft-start PMOS transistor SW, a soft-start current source IST, and the soft-start capacitor CSS;
[0064] The gate of the soft-start PMOS transistor SW is connected to the oscillator. The source of the soft-start PMOS transistor SW is connected to the VDD terminal. The drain of the soft-start PMOS transistor SW is connected to the negative terminal of the soft-start current source IST. The positive terminal of the soft-start current source IST is grounded through the soft-start capacitor CSS. The positive terminal of the soft-start current source IST is connected to the drive module.
[0065] The frequency required for the soft - start Pmos transistor SW can be set through an oscillator. The type of the oscillator is not limited here. In one implementation, the oscillator includes: a inverters;
[0066] The a inverters are connected in series. The input terminal of the first inverter is connected to the output terminal of the last inverter, and the output terminal of the last inverter serves as the output terminal of the oscillator and is connected to the soft - start sub - module. Here, a is an odd number greater than 0. If a≥3, the output terminal of the b - th inverter is connected to the input terminal of the (b + 1)-th inverter, where b is a positive integer less than a. Among them, the more the number of inverters, the smaller the frequency, and the slower the rising speed of the VOUT terminal. The fewer the number of inverters, the larger the frequency, and the faster the rising speed of the VOUT terminal. In this embodiment, a is taken as 3 for illustration.
[0067] Since the frequency generated by the oscillator is generally high, a flip - flop is introduced to divide the relevant signal frequency to obtain a smaller frequency. Specifically, please refer to Figure 7 The oscillator further includes: c D flip - flops;
[0068] The input terminal of each D flip - flop is connected to its own inverted output terminal. The clock terminal of the first D flip - flop is connected to the output terminal of the last inverter, and the positive output terminal of the last D flip - flop is connected to the soft - start sub - module. Here, c is a positive integer. If c≥2, the positive output terminal of the d - th D flip - flop is connected to the clock terminal of the (d + 1)-th D flip - flop, where d is a positive integer less than c. Among them, the flip - flop can perform frequency division to make the frequency smaller. In this embodiment, c is taken as 2 for illustration.
[0069] In order to be able to freely adjust the frequency, digital control can also be added. Specifically, please refer to Figure 8 The oscillator further includes: at least one control branch. The control branch includes a branch capacitor and a branch Nmos transistor;
[0070] In each control branch, the gate of the branch Nmos transistor is connected to external control, the source of the branch Nmos transistor is grounded, and the drain of the branch Nmos transistor is connected to the output terminal of the last inverter through the branch capacitor. In this embodiment, four control branches are used for illustration, that is, there is 4 - bit digital control, a total of 16 cases. The capacitance values of the branch capacitors in each control branch are different. The larger the capacitance value, the greater the delay of the control branch, resulting in a smaller final pulse signal frequency.
[0071] This embodiment is described with an oscillator having a digital control function.
[0072] The working principle of the control circuit in this embodiment will be described by way of example. When the control circuit is powered on and there is an input signal at the general input terminal, at this time, since no current flows through the second resistor R2, the voltage at the VFB terminal is 0, while the VREF terminal is already at a high level, and the oscillator has not given a pulse signal to the gate of the soft-start Pmos transistor SW, so the soft-start Pmos transistor SW is not conducting at the beginning, the soft-start current source IST is not working, and the voltage of the soft-start capacitor CSS is 0, that is, the VST terminal is 0. Then the first Pmos transistor Q3 and the third Pmos transistor Q5 conduct, the second Pmos transistor Q4 is turned off, and both the first Pmos transistor Q3 and the third Pmos transistor Q5 have drain currents, which causes the fourth Nmos transistor Q7 to conduct, and then the fifth Nmos transistor Q8 conducts. The fifth Nmos transistor Q8 has a drain current, and the gate of the power transistor P is at a low level, and the power transistor P conducts, and the voltage at the VOUT terminal starts to rise. Next, in the oscillator, the control branch based on the digital control function can provide 16 frequency adjustment situations. After selecting one of them, a pulse signal with the corresponding frequency is input to the gate of the soft-start Pmos transistor SW. The soft-start current source IST intermittently charges the soft-start capacitor CSS, and the voltage at the VST terminal slowly rises. Since the voltage at the VST terminal rises faster than the voltage at the VFB terminal, the drain current of the first Pmos transistor Q3 increases. Under the action of the current mirror, the drain current of the fourth Nmos transistor Q7 also increases, and the drain voltage value of the fourth Nmos transistor Q7 increases, which in turn causes the drain voltage of the power transistor P to slowly rise. When the voltage at the VFB terminal rises to the reference voltage and is equal to that of VREF, the first Pmos transistor Q3 is turned off, the second Pmos transistor Q4 conducts, the power transistor P remains conducting, and the voltage at the VOUT terminal remains unchanged. Figure 9 The simulation result of the control circuit is shown. At room temperature, the soft-start time is 1 ms.
[0073] In this embodiment, the soft-start capacitor CSS in the soft-start module is of the picofarad level or below, and the soft-start capacitor CSS is in the form of on-chip. By setting the oscillator to control the charging speed of the soft-start capacitor CSS, the rising speed of the voltage value at the general output terminal can be controlled. For example, only an internal 4 pF capacitor can achieve a soft-start power-on time of 1 ms, which is significant for avoiding overshoot at the VOUT terminal during power-on. This makes the production cost lower and is easy to package. And the oscillator can implement the digital control function to control the pulse signal frequency and thus control the charging speed of the soft-start capacitor CSS to meet the user's customized needs. In addition, the soft-start sub-module has a simple structure, which greatly saves the chip area.
[0074] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing embodiments and will not be elaborated herein.
[0075] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical, or other forms.
[0076] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0077] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.
[0078] As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.
Claims
1. A control circuit, characterized in that, Comprising: A soft start module, a driving module, a first resistor, and a second resistor; The driving input terminal of the driving module serves as the total input terminal of the control circuit, the output terminal of the driving module serves as the total output terminal of the control circuit, the first end of the first resistor is connected to the total output terminal, and the second end of the first resistor is grounded through the second resistor; The feedback input terminal of the driving module is connected to the second end of the first resistor, the reference input terminal of the driving module is used to receive a preset reference voltage signal, the soft start input terminal of the driving module is connected to the soft start module, wherein a soft start capacitor of picofarad level or below is provided in the soft start module, so that when the voltage value at the feedback input terminal is less than the value of the reference voltage signal, the voltage value of the soft start capacitor is controlled to make the voltage value at the soft start input terminal rise slowly, and then make the voltage value at the total output terminal rise slowly.
2. The control circuit according to claim 1, wherein The driving module includes: an error amplification sub-module and a driving sub-module; The first error input terminal of the error amplification sub-module serves as the soft start input terminal, the error amplification sub-module is connected to the soft start module through the first error input terminal, the second error input terminal of the error amplification sub-module serves as the reference input terminal for receiving the reference voltage signal, the third error input terminal of the error amplification sub-module serves as the feedback input terminal, and the error amplification sub-module is connected to the second end of the first resistor through the third error input terminal; The output terminal of the error amplification sub-module is connected to the first input terminal of the driving sub-module, the second input terminal of the driving sub-module serves as the total input terminal, and the output terminal of the driving sub-module serves as the output terminal of the driving module.
3. The control circuit according to claim 2, wherein The driving sub-module includes: a power tube; The gate of the power tube is connected to the output terminal of the error amplification sub-module, the source of the power tube serves as the total input terminal, the drain of the power tube serves as the total output terminal, and the drain of the power tube is connected to the first end of the first resistor.
4. The control circuit according to claim 2, wherein, The driving sub-module includes: a first comparator, an RS flip-flop, a first driving unit, a second driving unit, a first Nmos transistor, a second Nmos transistor, a first capacitor, a second capacitor, and a first inductor; The inverting input terminal of the first comparator is used to receive a current detection signal. The non-inverting input terminal of the first comparator serves as the first input terminal of the driving sub-module. The non-inverting input terminal of the first comparator is connected to the output terminal of the error amplification sub-module. The output terminal of the first comparator is respectively connected to the input terminals of the first driving unit and the second driving unit. The output terminal of the first driving unit is respectively connected to the first terminal of the first capacitor and the gate of the first Nmos transistor. The output terminal of the second driving unit is connected to the gate of the second Nmos transistor. The drain of the first Nmos transistor serves as the total input terminal. The source of the first Nmos transistor is respectively connected to the second terminal of the first capacitor, the first terminal of the first inductor, and the drain of the second Nmos transistor. The source of the second Nmos transistor is grounded. The second terminal of the first inductor is connected to the first terminal of the second capacitor. The second terminal of the second capacitor is grounded. The first terminal of the second capacitor serves as the total output terminal.
5. The control circuit according to claim 2, wherein The error amplification sub-module includes: a first Pmos transistor, a second Pmos transistor, a third Pmos transistor, a third Nmos transistor, a fourth Nmos transistor, a fifth Nmos transistor, a first current source, and a second current source; The negative terminals of the first current source and the second current source are both connected to the VDD terminal. The positive terminal of the first current source is respectively connected to the source of the first Pmos transistor, the source of the second Pmos transistor, and the source of the third Pmos transistor. The gate of the first Pmos transistor serves as the soft start input terminal and is connected to the soft start module. The gate of the second Pmos transistor serves as the reference input terminal. The gate of the third Pmos transistor serves as the feedback input terminal and is connected to the second terminal of the first resistor. The drain of the first Pmos transistor is respectively connected to the drain of the second Pmos transistor, the drain of the third Nmos transistor, the gate of the third Nmos transistor, and the gate of the fourth Nmos transistor. The drain of the third Pmos transistor is respectively connected to the drain of the fourth Nmos transistor and the gate of the fifth Nmos transistor. The drain of the fifth Nmos transistor is connected to the positive terminal of the second current source. The sources of the third Nmos transistor, the fourth Nmos transistor, and the fifth Nmos transistor are all grounded. The drain of the fifth Nmos transistor serves as the output terminal of the error amplification sub-module and is connected to the driving sub-module.
6. The control circuit according to claim 1, wherein The soft start module includes: an oscillator and a soft start sub-module; The soft start sub-module is respectively connected to the oscillator and the driving module. The soft start capacitor is arranged in the soft start sub-module. The soft start sub-module is used to receive the pulse signal input by the oscillator and slowly charge the soft start capacitor based on the pulse signal, so that the voltage value of the soft start input terminal rises slowly.
7. The control circuit according to claim 6, characterized in that, The soft start sub-module includes: a soft start Pmos transistor, a soft start current source, and the soft start capacitor; The gate of the soft-start Pmos transistor is connected to the oscillator, the source of the soft-start Pmos transistor is connected to the VDD terminal, the drain of the soft-start Pmos transistor is connected to the negative terminal of the soft-start current source, the positive terminal of the soft-start current source is grounded through the soft-start capacitor, and the positive terminal of the soft-start current source is connected to the drive module.
8. The control circuit according to claim 6, characterized in that The oscillator includes: a inverters; The a inverters are connected in series, the input terminal of the first inverter is connected to the output terminal of the last inverter, and the output terminal of the last inverter is used as the output terminal of the oscillator and is connected to the soft-start sub-module. Wherein, a is an odd number greater than 0. If a≥3, the output terminal of the b-th inverter is connected to the input terminal of the (b + 1)-th inverter, and b is a positive integer less than a.
9. The control circuit according to claim 8, wherein The oscillator further includes: c D flip-flops; The input terminal of each D flip-flop is connected to its respective inverted output terminal. The clock terminal of the first D flip-flop is connected to the output terminal of the last inverter, and the positive output terminal of the last D flip-flop is connected to the soft-start sub-module. Wherein, c is a positive integer. If c≥2, the positive output terminal of the d-th D flip-flop is connected to the clock terminal of the (d + 1)-th D flip-flop, and d is a positive integer less than c.
10. The control circuit according to claim 9, characterized in that, The oscillator further includes: at least one control branch, and the control branch includes a branch capacitor and a branch Nmos transistor; In each of the control branches, the gate of the branch Nmos transistor is connected to an external control, the source of the branch Nmos transistor is grounded, and the drain of the branch Nmos transistor is connected to the output terminal of the last inverter through the branch capacitor.