Ultra-low container device and ultra-low-capacity TVS (Transient Voltage Suppressor) tube array structure

Abstract

The utility model relates to an ultra-low container device, in particular to an ultra-low container device and an ultra-low-capacity TVS (Transient Voltage Suppressor) tube array structure, which are characterized in that a first N-type diffusion region, a first P-type diffusion region, a second N-type diffusion region, a third N-type diffusion region, a second P-type diffusion region and a fourth N-type diffusion region are sequentially embedded between an N-type epitaxial layer and an isolating layer from left to right; the N-type epitaxial layer is provided with a plurality of isolation grooves, and the isolation grooves extend downwards into the P-type substrate layer. A first front metal layer and a second front metal layer are arranged at the top of the isolation layer, and the first front metal layer is attached to the first N-type diffusion region and the first P-type diffusion region; the second front metal layer is attached to the second N-type diffusion region, the third N-type diffusion region, the second P-type diffusion region and the fourth N-type diffusion region. According to the utility model, the overall stability of the ultra-low-capacitance TVS tube array can be improved, and the working voltage range of the ultra-low-capacitance TVS tube array can be widened.

Description

Technical Field

[0001] The utility model relates to ultra-low capacitance components, in particular to an ultra-low capacitance component and an ultra-low capacitance TVS tube array structure. Background Art

[0002] In the field of ESD (electrostatic discharge) protection, ultra-low capacitance TVS (transient voltage suppressor) tube arrays are widely used because they can effectively protect electronic devices from damage caused by transient voltage impacts such as electrostatic discharge. However, different application environments have different requirements for the working voltage of TVS tubes.

[0003] The traditional approach is to integrate the capacitance reduction part and the TVS part together. Although such a design simplifies the packaging process, it brings complexity in the manufacturing process because the mutual influence between the two parts of the devices needs to be considered simultaneously. Especially at different working voltages, how to ensure the stability of the overall performance becomes a challenge. Summary of the Utility Model

[0004] The purpose of the utility model is to solve the technical problem that the existing ultra-low capacitance TVS tube arrays cannot guarantee the stability of the overall performance at different working voltages, and to provide an ultra-low capacitance component and an ultra-low capacitance TVS tube array structure.

[0005] To solve the above technical problems, the technical solution provided by the utility model is as follows:

[0006] An ultra-low capacitance component, comprising a back metal layer, a P-type substrate layer, a P-type epitaxial layer, an N-type epitaxial layer, and an isolation layer that are sequentially bonded from bottom to top;

[0007] An N-type buried layer is provided between the P-type epitaxial layer and the N-type epitaxial layer;

[0008] A first N-type diffusion region, a first P-type diffusion region, a second N-type diffusion region, a third N-type diffusion region, a second P-type diffusion region, and a fourth N-type diffusion region are sequentially embedded between the N-type epitaxial layer and the isolation layer from left to right;

[0009] Isolation grooves are formed on the N-type epitaxial layer on both sides of the first N-type diffusion region, on both sides of the first P-type diffusion region and the second N-type diffusion region, on both sides of the third N-type diffusion region, the second P-type diffusion region, and the fourth N-type diffusion region, and the isolation grooves extend downward into the P-type substrate layer;

[0010] First N-type diffusion region contact holes, first P-type diffusion region contact holes, and second N-type diffusion region contact holes corresponding to the first N-type diffusion region, the first P-type diffusion region, and the second N-type diffusion region respectively, and combined contact holes corresponding to the third N-type diffusion region, the second P-type diffusion region, and the fourth N-type diffusion region are formed on the isolation layer;

[0011] On the top of the isolation layer, there are a first front metal layer and a second front metal layer. The first front metal layer is attached to the first N-type diffusion region and the first P-type diffusion region through the first N-type diffusion region contact hole and the first P-type diffusion region contact hole; the second front metal layer is attached to the second N-type diffusion region, the third N-type diffusion region, the second P-type diffusion region and the fourth N-type diffusion region through the second N-type diffusion region contact hole and the combined contact hole.

[0012] Further, the material of the P-type substrate layer is silicon with a <100> crystal orientation, and its resistivity is 0.002 - 0.006 Ω·cm.

[0013] Further, the thickness of the P-type epitaxial layer is 5 - 10 μm, and the resistivity is 5 - 10 Ω·cm.

[0014] Further, the resistivity of the N-type epitaxial layer is 60 - 150 Ω·cm, and the thickness is 5 μm - 10 μm.

[0015] Further, the depth of the isolation groove is 19 μm.

[0016] Further, the thickness of the first front metal layer and the second front metal layer is 4 μm, and the material is silicon-aluminum alloy.

[0017] Further, the material of the back metal layer is titanium-nickel-silver.

[0018] Further, the doping material of the first N-type diffusion region, the second N-type diffusion region, the third N-type diffusion region and the fourth N-type diffusion region is phosphorus; the doping material of the first P-type diffusion region and the second P-type diffusion region is boron.

[0019] Further, the doping material of the N-type buried layer is phosphorus.

[0020] The present utility model also provides an ultra-low capacitance TVS tube array structure based on the aforementioned ultra-low capacitance device, including a TVS tube and a plurality of ultra-low capacitance devices connected in parallel; the VCC ends of the plurality of ultra-low capacitance devices are all connected to the cathode of the TVS tube, and the GND ends are connected to the anode of the TVS tube;

[0021] The first front metal layer of the ultra-low capacitance device is attached to the first N-type diffusion region and the first P-type diffusion region as the IO end of the ultra-low capacitance device;

[0022] The second front metal layer of the ultra-low capacitance device is attached to the second N-type diffusion region, the third N-type diffusion region, the second P-type diffusion region and the fourth N-type diffusion region as the VCC end of the ultra-low capacitance device;

[0023] The P-type substrate layer of the ultra-low capacitance device is attached to the back metal layer as the GND end of the ultra-low capacitance device.

[0024] Compared with the prior art, the beneficial effects of the present utility model are as follows:

[0025] The ultra-low capacitance device and the ultra-low capacitance TVS tube array structure provided by the present utility model separate the ultra-low capacitance device from the TVS tube. By reducing the doping concentration of the N-type epitaxial layer, P-type epitaxial layer, and N-type buried layer, or increasing the thickness of the N-type epitaxial layer, P-type epitaxial layer, and N-type buried layer, the overall capacitance of the ultra-low capacitance device can be reduced, and the reverse breakdown voltage of the ultra-low capacitance device can be increased; it helps to improve the overall stability of the ultra-low capacitance TVS tube array and broaden the working voltage range of the ultra-low capacitance TVS tube array. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of an embodiment of the present utility model;

[0027] Figure 2 is an equivalent circuit diagram of the ultra-low capacitance device in the embodiment of the present utility model;

[0028] Figure 3 is an equivalent circuit diagram of the ultra-low capacitance TVS tube array structure in the embodiment of the present utility model.

[0029] Description of reference numerals: 1 - back metal layer, 2 - P-type substrate layer, 3 - P-type epitaxial layer, 4 - N-type epitaxial layer, 5 - isolation layer, 6 - N-type buried layer, 7 - first N-type diffusion region, 8 - first P-type diffusion region, 9 - second N-type diffusion region, 10 - third N-type diffusion region, 11 - second P-type diffusion region, 12 - fourth N-type diffusion region, 13 - isolation groove, 14 - first front metal layer, 15 - second front metal layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Next, the technical solutions in the present utility model will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without making creative efforts fall within the protection scope of the present utility model.

[0031] As Figure 1 shown, an ultra-low capacitance device includes a back metal layer 1, a P-type substrate layer 2, a P-type epitaxial layer 3, an N-type epitaxial layer 4, and an isolation layer 5 that are sequentially bonded from bottom to top; an N-type buried layer 6 is provided between the P-type epitaxial layer 3 and the N-type epitaxial layer 4;

[0032] A first N-type diffusion region 7, a first P-type diffusion region 8, a second N-type diffusion region 9, a third N-type diffusion region 10, a second P-type diffusion region 11, and a fourth N-type diffusion region 12 are sequentially embedded between the N-type epitaxial layer 4 and the isolation layer 5 from left to right;

[0033] Isolation grooves 13 are formed on the N-type epitaxial layer 4 on both sides of the first N-type diffusion region 7, on both sides of the first P-type diffusion region 8 and the second N-type diffusion region 9, on both sides of the third N-type diffusion region 10, on both sides of the second P-type diffusion region 11 and the fourth N-type diffusion region 12, and the isolation grooves 13 extend downward into the P-type substrate layer 2;

[0034] Contact holes for the first N-type diffusion region 7, contact holes for the first P-type diffusion region 8, and contact holes for the second N-type diffusion region 9 corresponding to the first N-type diffusion region 7, the first P-type diffusion region 8, and the second N-type diffusion region 9 respectively are formed on the isolation layer 5, and combined contact holes corresponding to the third N-type diffusion region 10, the second P-type diffusion region 11, and the fourth N-type diffusion region 12 are formed;

[0035] A first front metal layer 14 and a second front metal layer 15 are provided on the top of the isolation layer 5. The first front metal layer 14 is bonded to the first N-type diffusion region 7 and the first P-type diffusion region 8 through the contact holes for the first N-type diffusion region 7 and the contact holes for the first P-type diffusion region 8; the second front metal layer 15 is bonded to the second N-type diffusion region 9, the third N-type diffusion region 10, the second P-type diffusion region 11, and the fourth N-type diffusion region 12 through the contact holes for the second N-type diffusion region 9 and the combined contact holes.

[0036] The material of the P-type substrate layer 2 is silicon with a <100> crystal orientation, and its resistivity is 0.002 - 0.006 Ω·cm.

[0037] The thickness of the P-type epitaxial layer 3 is 5 - 10 μm, and its resistivity is 5 - 10 Ω·cm.

[0038] The resistivity of the N-type epitaxial layer 4 is 60 - 150 Ω·cm, and its thickness is 5 μm - 10 μm.

[0039] The depth of the isolation groove 13 is 19 μm.

[0040] The thickness of the first front metal layer 14 and the second front metal layer 15 is 4 μm, and the material is silicon-aluminum alloy.

[0041] The material of the back metal layer 1 is titanium-nickel-silver.

[0042] The doping material of the first N-type diffusion region 7, the second N-type diffusion region 9, the third N-type diffusion region 10, and the fourth N-type diffusion region 12 is phosphorus; the doping material of the first P-type diffusion region 8 and the second P-type diffusion region 11 is boron.

[0043] The doping material of the N-type buried layer 6 is phosphorus.

[0044] In this embodiment, an ultra-low capacitance device is formed through the following steps, specifically:

[0045] 1) Through an epitaxial process, P-type epitaxial growth is performed on the P-type substrate layer 2 to form a P-type epitaxial layer 3;

[0046] 2) Form an N-type buried layer 6 on the P-type epitaxial layer 3 using the photo, implant, and drive-in processes; wherein, the photo process is an exposure and development (defining device patterns) process, the implant process is an ion implantation (doping) process, and the drive-in process is a push (pushing the junction and activating doping ions) process;

[0047] 3) Conduct N-type epitaxial growth on the P-type epitaxial layer 3 and the N-type buried layer 6 through the epitaxial process to form an N-type epitaxial layer 4;

[0048] 4) Use the photo, implant, and drive-in processes to form a first N-type diffusion region 7, a first P-type diffusion region 8, a second N-type diffusion region 9, a third N-type diffusion region 10, a second P-type diffusion region 11, and a fourth N-type diffusion region 12 that are distributed in sequence from left to right on the N-type epitaxial layer 4;

[0049] 5) Form an isolation trench 13 through the deep trench process;

[0050] 6) Deposit an isolation layer 5 on the N-type epitaxial layer 4;

[0051] 7) Open a first N-type diffusion region 7 contact hole, a first P-type diffusion region 8 contact hole, and a second N-type diffusion region 9 contact hole corresponding to the first N-type diffusion region 7, the first P-type diffusion region 8, and the second N-type diffusion region 9 respectively, as well as a combined contact hole corresponding to the third N-type diffusion region 10, the second P-type diffusion region 11, and the fourth N-type diffusion region 12 on the isolation layer 5;

[0052] The first front metal layer 14 is bonded to the first N-type diffusion region 7 and the first P-type diffusion region 8 through the first N-type diffusion region 7 contact hole and the first P-type diffusion region 8 contact hole; the second front metal layer 15 is bonded to the second N-type diffusion region 9, the third N-type diffusion region 10, the second P-type diffusion region 11, and the fourth N-type diffusion region 12 through the second N-type diffusion region 9 contact hole and the combined contact hole.

[0053] Among them, the first front metal layer 14 is bonded to the first N-type diffusion region 7 and the first P-type diffusion region 8 as the IO terminal of the ultra-low capacitance device; the second front metal layer 15 is bonded to the second N-type diffusion region 9, the third N-type diffusion region 10, the second P-type diffusion region 11, and the fourth N-type diffusion region 12 as the VCC terminal of the ultra-low capacitance device; the P-type substrate layer 2 is bonded to the back metal layer 1 as the GND terminal of the ultra-low capacitance device.

[0054] In this embodiment, the P-type epitaxial layer 3, the N-type epitaxial layer 4, and the first N-type diffusion region 7 form a first diode, denoted as D1; the first P-type diffusion region 8, the N-type epitaxial layer 4, and the second N-type diffusion region 9 form a second diode, denoted as D2; the first P-type diffusion region 8, the N-type epitaxial layer 4, the N-type buried layer 6, the P-type epitaxial layer 3, and the P-type substrate 2 form a bidirectional TVS, denoted as T1; the P-type substrate 2, the P-type epitaxial layer 3, the N-type buried layer 6, the N-type epitaxial layer 4, the third N-type diffusion region, the second P-type diffusion region, and the fourth N-type diffusion region are short-circuited by the front metal 15 to form a third diode, denoted as T2.

[0055] As Figure 2 shown, connect D1, D2, T1, and T2 to form an equivalent circuit of an ultra-low capacitance device.

[0056] The present utility model also provides an ultra-low capacitance TVS tube array structure based on the aforementioned ultra-low capacitance device, including a TVS tube and a plurality of ultra-low capacitance devices connected in parallel; the VCC terminals of the plurality of ultra-low capacitance devices are all connected to the cathode of the TVS tube, and the GND terminals are connected to the anode of the TVS tube.

[0057] Denote the TVS tube as T3. As Figure 3 shown, connect the cathode of T3 to the VCC terminal of the equivalent circuit of the ultra-low capacitance device, and the anode to the GND terminal of the equivalent circuit of the ultra-low capacitance device, then an equivalent circuit of the ultra-low capacitance tube array structure with the required operating voltage (the operating voltage is determined by T3) can be formed.

[0058] As described above, the above is only the specific implementation manner of the present utility model, but the protection scope of the present utility model is not limited thereto. Any change or replacement within the technical scope disclosed by the present utility model should be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be subject to the protection scope of the claims.

Claims

1. An ultra-low container component, characterized in that: It includes a back metal layer (1), a P-type substrate layer (2), a P-type epitaxial layer (3), an N-type epitaxial layer (4), and an isolation layer (5) that are laminated in sequence from bottom to top; An N-type buried layer (6) is provided between the P-type epitaxial layer (3) and the N-type epitaxial layer (4); A first N-type diffusion region (7), a first P-type diffusion region (8), a second N-type diffusion region (9), a third N-type diffusion region (10), a second P-type diffusion region (11), and a fourth N-type diffusion region (12) are sequentially embedded between the N-type epitaxial layer (4) and the isolation layer (5) from left to right; Isolation grooves (13) are formed on the N-type epitaxial layer (4) on both sides of the first N-type diffusion region (7), on both sides of the first P-type diffusion region (8) and the second N-type diffusion region (9), on both sides of the third N-type diffusion region (10), the second P-type diffusion region (11), and the fourth N-type diffusion region (12), and the isolation grooves (13) extend downward into the P-type substrate layer (2); Contact holes for the first N-type diffusion region (7), contact holes for the first P-type diffusion region (8), and contact holes for the second N-type diffusion region (9) corresponding to the first N-type diffusion region (7), the first P-type diffusion region (8), and the second N-type diffusion region (9) respectively, and combined contact holes corresponding to the third N-type diffusion region (10), the second P-type diffusion region (11), and the fourth N-type diffusion region (12) are formed on the isolation layer (5); A first front metal layer (14) and a second front metal layer (15) are provided on the top of the isolation layer (5). The first front metal layer (14) is attached to the first N-type diffusion region (7) and the first P-type diffusion region (8) through the contact holes for the first N-type diffusion region (7) and the contact holes for the first P-type diffusion region (8); the second front metal layer (15) is attached to the second N-type diffusion region (9), the third N-type diffusion region (10), the second P-type diffusion region (11), and the fourth N-type diffusion region (12) through the contact holes for the second N-type diffusion region (9) and the combined contact holes; 2. The ultra-low container part according to claim 1, characterized in that: The material of the P-type substrate layer (2) is silicon with a <100> crystal orientation, and its resistivity is 0.002 - 0.006 Ω·cm.

3. The ultra-low container component according to claim 1, wherein: The thickness of the P-type epitaxial layer (3) is 5 - 10 μm, and its resistivity is 5 - 10 Ω·cm.

4. The ultra-low container component according to claim 1, characterized in that: The resistivity of the N-type epitaxial layer (4) is 60 - 150 Ω·cm, and its thickness is 5 μm - 10 μm.

5. The ultra-low container part according to claim 1, wherein: The depth of the isolation groove (13) is 19 μm.

6. The ultra-low container according to claim 1, characterized in that: The thickness of the first front metal layer (14) and the second front metal layer (15) is 4 μm, and the material is silicon-aluminum alloy.

7. The ultra-low container part according to claim 1, wherein: The material of the back metal layer (1) is titanium-nickel-silver.

8. The ultra-low container component according to claim 1, wherein: The doping materials of the first N-type diffusion region (7), the second N-type diffusion region (9), the third N-type diffusion region (10), and the fourth N-type diffusion region (12) are phosphorus; the doping materials of the first P-type diffusion region (8) and the second P-type diffusion region (11) are boron.

9. The ultra-low container component according to claim 1, characterized in that: The doping material of the N-type buried layer (6) is phosphorus.

10. An ultra-low capacitance TVS tube array structure based on the ultra-low capacitance device according to any one of claims 1-9, characterized in that: It includes a TVS tube and multiple ultra-low capacitance components connected in parallel; the VCC terminals of the multiple ultra-low capacitance components are all connected to the cathode of the TVS tube, and the GND terminals are connected to the anode of the TVS tube; The first front metal layer (14) of the ultra-low capacitor device is bonded to the first N-type diffusion region (7) and the first P-type diffusion region (8) to serve as the IO terminal of the ultra-low capacitor device; The second front metal layer (15) of the ultra-low capacitor device is bonded to the second N-type diffusion region (9), the third N-type diffusion region (10), the second P-type diffusion region (11) and the fourth N-type diffusion region (12) to serve as the VCC terminal of the ultra-low capacitor device; The P-type substrate layer (2) of the ultra-low capacitor device is bonded to the back metal layer (1) to serve as the GND terminal of the ultra-low capacitor device.

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