Semiconductor device

Abstract

The high voltage transistor may include a plurality of source / drain regions, a gate structure, and a gate oxide layer such that the gate structure can selectively control channel regions between the plurality of source / drain regions. The gate oxide layer may extend laterally outward toward one or more of the plurality of source / drain regions such that at least a portion of the gate oxide layer is not under the gate structure. A gate oxide layer extending laterally outward from below the gate structure enables the gate oxide layer to function as a self-aligned structure for forming a plurality of source / drain regions of the high voltage transistor. Specifically, a gate oxide layer extending laterally outward from below a gate structure enables the gate oxide layer to be used to form a plurality of source / drain regions at a larger spacing from the gate structure without the use of an additional implant mask when forming the plurality of source / drain regions.

Description

Technical Field

[0001] Embodiments of the present utility model relate to semiconductor devices. Background Art

[0002] High-voltage transistors include transistors configured to operate at high voltages (e.g., high gate voltages, high drain voltages) relative to other types of transistors. High-voltage transistors may be included in level shifter circuits, power generation circuits, and / or other types of high-voltage circuits. Summary of the Utility Model

[0003] Embodiments of the present utility model provide a semiconductor device, including a first doped region containing a first dopant type in a substrate of the semiconductor device; a second doped region containing a second dopant type in the substrate and adjacent to the first doped region; a first source / drain region of a high-voltage transistor structure included in the semiconductor device, including the second dopant type in the substrate; a second source / drain region of the high-voltage transistor structure, including the second dopant type in the second doped region on the substrate; a gate structure of the high-voltage transistor structure between the first source / drain region and the second source / drain region; and a gate oxide layer of the high-voltage transistor structure between the first source / drain region and the second source / drain region, wherein a first portion of the gate oxide layer is under the gate structure and between the gate structure and the substrate, and wherein a second portion of the gate oxide layer extends laterally outward beyond the gate structure and between the second source / drain region and the first portion of the gate oxide layer.

[0004] Embodiments of the present utility model provide a semiconductor device, comprising a substrate; a low-voltage device region; a high-voltage device region; and an isolation region between the low-voltage device region and the high-voltage device region, wherein the low-voltage device region comprises one or more low-voltage fin field-effect transistor (finFET) structures, wherein the high-voltage device region comprises a high-voltage transistor structure, and wherein the high-voltage transistor structure comprises: a first source / drain region; a second source / drain region; a gate structure between the first source / drain region and the second source / drain region; and a gate oxide layer between the first source / drain region and the second source / drain region, wherein a first portion of the gate oxide layer is under the gate structure and between the gate structure and the substrate, and wherein a second portion of the gate oxide layer extends laterally outward beyond the gate structure and between the first source / drain region and the first portion of the gate oxide layer, and wherein a third portion of the gate oxide layer extends laterally outward beyond the gate structure and between the second source / drain region and the first portion of the gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various aspects of the present utility model will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0007] Figure 2 is a diagram of an example semiconductor device described herein.

[0008] Figures 3A to 3C is a diagram of an example implementation of a high-voltage transistor described herein.

[0009] Figure 4A and Figure 4B is a diagram of an example tuning parameter for a high-voltage transistor described herein.

[0010] Figures 5A to 5M is a diagram of an example implementation described herein.

[0011] Figure 6 is a diagram of an example component of a device described herein.

[0012] Figure 7 is a flowchart of an example process related to forming a semiconductor device described herein.

[0013] [DESCRIPTION OF SYMBOLS]

[0014] 100: Environment

[0015] 102: Deposition Tool / Semiconductor Processing Tool

[0016] 104: Exposure Tool / Semiconductor Processing Tool

[0017] 106: Developer Tool / Semiconductor Processing Tool

[0018] 108: Etching Tool / Semiconductor Processing Tool

[0019] 110: Planarization Tool / Semiconductor Processing Tool

[0020] 112: Plating Tool / Semiconductor Processing Tool

[0021] 114: Ion Implantation Tool / Semiconductor Processing Tool

[0022] 116: Wafer / Die Transfer Tool

[0023] 200: Semiconductor Device

[0024] 202: Low - Voltage Device Region

[0025] 204: High - Voltage Device Region

[0026] 206: Isolation Region

[0027] 208: Substrate

[0028] 210: Low - Voltage Transistor Structure

[0029] 212: High - Voltage Transistor Structure / High - Voltage Semiconductor Device

[0030] 214: Semiconductor Fin Structure

[0031] 216, 222, 222a, 222b: Source / Drain Region

[0032] 218, 224: Gate Structure

[0033] 220, 228, 228a, 228b: Contact Structure

[0034] 226: Gate Oxide Layer

[0035] 226a, 226b, 226c: Portion

[0036] 230: Alignment Overlap

[0037] 232: Low - Voltage Shallow Trench Isolation Region

[0038] 234: STI Region

[0039] 236, 238: Isolation structure

[0040] 240: dummy gate structure

[0041] 242: dielectric region

[0042] 300, 500: Embodiment

[0043] 302: deep well

[0044] 304: P-well region

[0045] 306a, 306b: NLDD region

[0046] 308: sidewall spacer

[0047] 310: silicide layer

[0048] 312: depletion region

[0049] 400, 406: tuning parameter

[0050] 402: GIDL

[0051] 404: distance

[0052] 408: drain saturation current

[0053] 502: STI formation operation / semiconductor processing operation

[0054] 504: well implantation operation / semiconductor processing operation

[0055] 506: lightly doped implantation operation / semiconductor processing operation

[0056] 508: oxide formation operation / semiconductor processing operation

[0057] 510: gate formation operation / semiconductor processing operation

[0058] 512: spacer formation operation / semiconductor processing operation

[0059] 514: gate oxide etching operation / semiconductor processing operation

[0060] 516: source / drain implantation operation / semiconductor processing operation

[0061] 518: ILD formation operation / semiconductor processing operation

[0062] 520: MD formation operation / semiconductor processing operation

[0063] 522: oxide layer

[0064] 524: ion

[0065] 526: Depression

[0066] 600: Device

[0067] 610: Bus

[0068] 620: Processor

[0069] 630: Memory

[0070] 640: Input Component

[0071] 650: Output Component

[0072] 660: Communication Component

[0073] 700: Process

[0074] 710, 720, 730, 740, 750, 760: Blocks

[0075] D1, D2: Dimensions Detailed Implementation Manner

[0076] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming the first feature above or on the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0077] Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0078] A high-voltage transistor may include multiple source / drain regions, a gate structure, and a gate oxide layer (e.g., a high temperature oxide (HTO) and / or another type of gate oxide) such that the gate structure can selectively control a channel region between the multiple source / drain regions. The source / drain regions may refer to the source or the drain individually or collectively, depending on the context. Multiple sidewall spacers may be included on multiple sidewalls of the gate structure to electrically isolate the gate structure from other structures near the high-voltage transistor.

[0079] As the dimensions of multiple structures and / or multiple layers in a semiconductor decrease in the advancement of semiconductor processing nodes, the spacing between these structures and / or layers may also decrease. The reduced dimensions and / or spacing of these structures and / or layers may cause undesirable side effects such as parasitic capacitance and / or current leakage. In a high-voltage transistor, the reduced dimensions of the structures and / or layers may result in a reduced spacing between the gate structure of the high-voltage transistor and the source / drain regions of the high-voltage transistor. The reduced spacing may cause gate induced drain leakage (GIDL). GIDL occurs when carrier depletion in the high-voltage transistor channel causes the depletion region of the channel to encroach on the source / drain regions when the gate structure is activated. High-voltage transistors are particularly vulnerable to GIDL because the high source / drain voltage causes a large carrier depletion in the channel and a large encroachment of the depletion region on the source / drain regions. GIDL in high-voltage transistors can increase the standby power consumption of the high-voltage transistor (e.g., the power consumption when the high-voltage transistor is turned off) and / or can increase the heat dissipation in the high-voltage transistor, which can reduce the service life of operating the high-voltage transistor.

[0080] Figure 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. As Figure 1 shown, the environment 100 may include multiple semiconductor processing tools 102 - 114 and a wafer / die transfer tool 116. The multiple semiconductor processing tools 102 - 114 may include a deposition tool 102, an exposure tool 104, a developer tool 106, an etch tool 108, a planarization tool 110, a plating tool 112, an ion implantation tool 114, and / or another type of semiconductor processing tool. Among other examples, the tools included in the example environment 100 may be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility.

[0081] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0082] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., a deep ultraviolet light source, an extreme UV (EUV) light source, and / or the like), an X-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures of a semiconductor device, can include a pattern for etching various portions of a semiconductor device, and the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0083] The developer tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0084] The etch tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool 108 can include a wet etch tool, a dry etch tool, etc. In some embodiments, the etch tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etch tool 108 can use plasma etching or plasma-assisted etching to etch one or more portions in the substrate, which can involve using an ionized gas to etch one or more portions isotropically or directionally.

[0085] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing the layers of a wafer or semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited or coated material. The planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize the surface of the semiconductor device. The planarization tool 110 can incorporate a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device) to utilize an abrasive and corrosive chemical slurry. The polishing pad and the semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can rotate about different axes of rotation to remove material and flatten any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

[0086] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0087] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material such as a gas or a solid in an arc chamber. The source material can be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate such that the ions are implanted beneath the surface of the substrate.

[0088] The wafer / die transfer tool 116 can be included in a cluster tool or another type of tool including multiple processing chambers, and can be configured to transfer substrates and / or semiconductor devices between multiple processing chambers, transfer substrates and / or semiconductor devices between a processing chamber and a buffer, transfer substrates and / or semiconductor devices between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or transfer substrates and / or semiconductor devices between a processing chamber and a transfer carrier (e.g., a front opening unified pod (FOUP)), etc. In some embodiments, the wafer / die transfer tool 116 can be included in a multi-chamber (or cluster) deposition tool 102, and the multi-chamber (or cluster) deposition tool 102 can include a pre-cleaning processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or by-products from the substrate and / or semiconductor device), as well as multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations).

[0089] In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may perform one or more of the semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may dope a substrate with a first dopant type to form a first doped region of a semiconductor device; may dope the substrate with a second dopant type to form a second doped region of the semiconductor device adjacent to the first doped region; may form an oxide layer over the first doped region and over the second doped region; may form a gate structure of a high-voltage transistor structure of the semiconductor device over the oxide layer; may perform an etching operation to remove material from the oxide layer to form a gate oxide layer of the high-voltage transistor structure, wherein the etching operation causes a portion of the gate oxide layer to extend laterally outward from the gate structure; and / or may use the gate oxide layer as a self-aligned pattern to form a plurality of source / drain regions of the high-voltage transistor structure, and so on.

[0090] As another example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may form a plurality of source / drain regions by doping a substrate using the gate oxide layer as a self-aligned implantation mask. As another example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may perform an etching operation such that the gate oxide layer extends laterally outward from the gate structure by a distance that meets a threshold distance. As another example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may perform a single sidewall spacer formation process to form sidewall spacers on the sidewalls of the gate structure before performing the etching operation. As another example, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may perform a single sidewall spacer formation process to form sidewall spacers on the sidewalls of the gate structure and to form another sidewall spacer on another gate structure of a low-voltage fin field effect transistor (finFET) structure of the semiconductor device.

[0091] One or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may perform other semiconductor processing operations described herein, such as in combination with Figures 5A-5M and / or Figure 7 etc.

[0092] Figure 1 The number and arrangement of the devices shown in Figure 1Compared with the apparatus shown, there may be additional apparatus, fewer apparatus, different apparatus, or apparatus arranged in a different manner. Additionally, Figure 1 the two or more apparatus shown may be implemented within a single apparatus, or Figure 1 the single apparatus shown may be implemented as multiple distributed apparatus. Additionally or alternatively, a set of apparatus (e.g., one or more apparatus) of example environment 100 may perform one or more functions described as being performed by another set of apparatus of example environment 100.

[0093] Figure 2 is a diagram of an example semiconductor device 200 described herein. The semiconductor device 200 may include a logic device (e.g., a processor, a central processing unit (CPU), a graphics processing unit (GPU)), a memory device (e.g., a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device), a display panel device (e.g., a display panel driver including a driver integrated circuit (IC), a line driver IC, a level shifter IC), and / or another type of semiconductor device 200 including a high voltage transistor structure.

[0094] As Figure 2 shown, the semiconductor device 200 may include a low voltage device region 202, a high voltage device region 204, and an isolation region 206 between the low voltage device region 202 and the high voltage device region 204. Alternatively, the low voltage device region 202 and the isolation region 206 may be omitted, and the semiconductor device 200 may include only the high voltage device region 204. The low voltage device region 202, the high voltage device region 204, and the isolation region 206 may be formed in and / or on a substrate 208 of the semiconductor device 200.

[0095] The low voltage device region 202 may include one or more low voltage transistor structures 210 formed in and / or on the substrate 208. The low voltage transistor structures 210 may refer to transistor structures that operate based on a relatively low voltage (e.g., about 6 volts or less, etc.). The high voltage device region 204 may include one or more high voltage transistor structures (also referred to as high voltage semiconductor devices) 212. The high voltage transistor structures 212 may refer to transistor structures that operate based on a relatively high voltage (e.g., relative to the low voltage transistor structures 210) (e.g., about 8 volts or more, etc.).

[0096] The low-voltage transistor structure 210 may include one or more low-voltage planar transistor structures, one or more low-voltage fin field-effect transistor (finFET) structures, one or more low-voltage nanostructure transistors, and / or one or more other types of low-voltage transistor structures. The low-voltage finFET transistor structure may include a semiconductor fin structure 214, a plurality of source / drain regions 216 on the semiconductor fin structure 214, and a gate structure 218 surrounding at least three sides of the portion of the semiconductor fin structure 214 between the plurality of source / drain regions 216. The plurality of source / drain regions 216 may be physically and / or electrically coupled to one or more contact structures 220, which may also be referred to as source / drain contacts or MDs. The low-voltage nanostructure transistor generally may refer to a low-voltage transistor structure 210 including a nanostructure channel (such as a nanosheet channel, a nanoribbon channel, a nanotube channel, and / or a multi-bridge channel, etc.). The gate structure 218 may completely surround the nanostructure channel (e.g., on four sides, on all sides), and the plurality of source / drain regions 216 may be included on opposite sides of the nanostructure channel and on opposite sides of the gate structure 218. In some embodiments, the low-voltage nanostructure transistor may be referred to as a gate all around (GAA) transistor structure or a GAA field-effect transistor (GAAFET or GAAFET) structure, a low-voltage nanowire transistor structure, a low-voltage nanosheet transistor structure, a low-voltage multi-bridge channel transistor structure, a nanoribbon transistor structure, and / or another type of low-voltage nanostructure transistor structure.

[0097] The high-voltage transistor structure 212 may include a plurality of source / drain regions 222, a gate structure 224 between the plurality of source / drain regions 222, and a gate oxide layer 226 between the plurality of source / drain regions and between the gate structure 224 and the substrate 208. The plurality of source / drain regions 222 may be physically and / or electrically coupled to one or more contact structures 228 (source / drain contacts or MDs). The high-voltage transistor structure 212 may include a high-voltage planar transistor structure, a high-voltage finFET structure, a high-voltage nanostructure transistor, and / or another type of high-voltage transistor structure.

[0098] As described herein, for example, in connection with Figures 3A-3C , Figure 4A and / or Figure 4BFor example, the gate oxide layer 226 may include a first portion located under the gate structure 224 and between the gate structure 224 and the substrate 208, and a second portion extending laterally outward beyond the gate structure 224 and toward one or more of the plurality of source / drain regions 222. The gate oxide layer 226 extending laterally outward beyond the gate structure 224 enables the second portion of the gate oxide layer 226 to be used as a self-aligned implantation mask when forming the plurality of source / drain regions 222. This not only reduces the number of additional mask layers used to form the plurality of source / drain regions 222 (e.g., since the gate oxide layer 226 serves as a mask layer, meaning the process for forming the plurality of source / drain regions 222 is self-aligned), but also enables one or more tuning parameters of the high-voltage transistor structure 212 to be optimized, such that the GIDL and / or another performance parameter of the high-voltage transistor structure 212 can be improved.

[0099] As Figure 2 further shown therein, the gate oxide layer 226 is used as a self-aligned implantation mask and integrated into the semiconductor device 200 having an advanced semiconductor structure such as a finFET structure (e.g., the low-voltage transistor structure 210). For example, Figure 2 the alignment overlap 230 shown therein shows a portion of the gate structure 218 (e.g., the low-voltage gate structure) on the semiconductor fin structure 214 in the low-voltage transistor structure 210 and the gate structure 224 of the high-voltage transistor structure 212 located at approximately the same height in the semiconductor device 200. This enables one or more semiconductor processing operations of the semiconductor device to be performed such that portions of the low-voltage transistor structure 210 and portions of the high-voltage transistor structure 212 are formed in the same one or more processing operations. For example, the alignment of the gate structure 218 and the gate structure 224 enables sidewall spacers (or gate spacers) to be formed for the gate structure 218 and the gate structure 224 in the same set of one or more semiconductor processing operations. In this way, different spacer formation operations are not required to form the sidewall spacers of the gate structure 218 and the gate structure 224, which reduces the semiconductor processing cost, reduces the semiconductor processing time, and / or reduces the consumption of semiconductor processing resources (e.g., processing chemicals, semiconductor processing facility power) used to form the semiconductor device 200, etc.

[0100] As Figure 2As further shown, one or more isolation regions and / or one or more isolation structures may be included between the low-voltage device region 202 and the high-voltage device region 204 to provide electrical isolation and / or thermal isolation between the low-voltage device region 202 and the high-voltage device region 204. For example, a low-voltage shallow trench isolation (STI) region 232 may be included in the isolation region 206 and / or in the high-voltage device region 204, and so on. As another example, an STI region 234 (e.g., a high-voltage STI region) may be included in the high-voltage device region 204. As another example, an isolation structure 236 and / or an isolation structure 238 may be included in the isolation region 206 and / or in the high-voltage device region 204. The isolation structure 236 and / or the isolation structure 238 may include trenches, vias, and / or other types of structures. As another example, a dummy gate structure 240 (e.g., an inactive gate structure) may be included in the high-voltage device region 204.

[0101] As Figure 2 As further shown, a dielectric region 242 may be included over and / or on the low-voltage transistor structure 210 and the high-voltage transistor structure 212. The dielectric region 242 may be included to provide additional electrical isolation and / or additional thermal isolation, as well as to provide a substantially planar surface on which subsequent layers and / or structures of the semiconductor device 200 may be formed.

[0102] As described above, Figure 2 is provided as an example. Other examples may be different from Figure 2 those described.

[0103] Figures 3A to 3C is a diagram of an example embodiment 300 of the high-voltage transistor structure 212 described herein. The high-voltage transistor structure 212 may be included in the semiconductor device 200 described herein.

[0104] As Figure 3AAs shown, a high-voltage transistor structure 212 can be formed in a substrate 208. The substrate 208 can include a silicon (Si) substrate, a substrate formed of a material including silicon, a group III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. The substrate 208 can include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. The substrate 208 can include a compound semiconductor and / or an alloy semiconductor. The substrate 208 can include various doping configurations to meet one or more design parameters. For example, different doping profiles (e.g., n-well, p-well) can be formed on the substrate 208 in multiple regions designed for different device types (e.g., p-type metal-oxide semiconductor (PMOS) nanostructure transistors, n-type metal-oxide semiconductor (NMOS) nanostructure transistors). Suitable doping can include ion implantation and / or diffusion processes of dopants. Additionally, the substrate 208 can include an epitaxial layer (epi-layer), which can be strained for performance enhancement and / or can have other suitable enhancement features. The substrate 208 can include a portion of a semiconductor wafer on which other semiconductor devices are formed.

[0105] A plurality of STI regions 234 can be included in the substrate 208 and located on opposite sides of the high-voltage transistor structure 212. The plurality of STI regions 234 can electrically isolate the high-voltage transistor structure 212 from other layers, structures, and / or devices in the semiconductor device 200. The plurality of STI regions 234 can include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low dielectric constant (low-k) dielectric material, and / or other suitable insulating materials. The plurality of STI regions 234 can include a multi-layer structure, e.g., having one or more liner layers.

[0106] As Figure 3AAs further shown, the high-voltage transistor structure 212 may include a deep well 302 in the substrate. The deep well 302 may include a deep n-well, a deep p-well, and / or another type of deep well. The deep n-well may refer to a region of the substrate 208 that includes semiconductor material (e.g., silicon (Si) and / or another semiconductor material) doped with one or more n-type dopants. Examples of n-type dopants include phosphorus (P), arsenic (As), and / or antimony (Sb), among others. The deep p-well may refer to a region of the substrate 208 that includes semiconductor material (e.g., silicon (Si) and / or another semiconductor material) doped with one or more p-type dopants. Examples of p-type dopants include boron (B), gallium (Ga), and / or indium (In), among others.

[0107] As Figure 3A further shown, the high-voltage transistor structure 212 may include a P-well region 304 over and / or on the deep well 302. The P-well region 304 may include a region of the substrate 208 that includes semiconductor material (e.g., silicon (Si) and / or another semiconductor material) doped with one or more p-type dopants (e.g., boron (B), gallium (Ga), and / or indium (In), etc.).

[0108] As Figure 3A further shown, the high-voltage transistor structure 212 may include a plurality of n-type lightly-doped source / drain (NLDD) regions in the P-well region 304. The plurality of NLDD regions may include NLDD region 306a and NLDD region 306b that are electrically separated and / or physically separated by the P-well region 304. NLDD region 306a and NLDD region 306b may include regions of the substrate 208 that include semiconductor material (e.g., silicon (Si) and / or another semiconductor material) lightly doped with one or more n-type dopants (e.g., phosphorus (P), arsenic (As), and / or antimony (Sb), etc.). For example, NLDD region 306a and NLDD region 306b may be "lightly doped" because NLDD region 306a and NLDD region 306b may include a dopant concentration in the range of about 1E 11 n-type ions per cm 2 to about 1E 13 n-type ions per cm 2 . However, other values within this range are also within the scope of the present disclosure. The light doping in NLDD region 306a and NLDD region 306b enables the threshold voltage (V t ) of the high-voltage transistor structure 212 to be reduced while enabling mid-voltage to high-voltage operation at one or more source / drain regions 222a and / or source / drain regions 222b of the high-voltage transistor structure 212.

[0109] The high-voltage transistor structure 212 may include a source / drain region 222a and a source / drain region 222b. The source / drain region 222a and the source / drain region 222b may each include silicon (Si) having one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge), etc.), an n-type material (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. The source / drain region 222a may be contained in the NLDD region 306a in the substrate 208. The source / drain region 222b may be contained in the NLDD region 306b in the substrate 208.

[0110] The dopant concentration in the source / drain region 222a and the source / drain region 222b may be greater than the dopant concentration in the NLDD region 306a and the NLDD region 306b. For example, the NLDD region 306a and / or the NLDD region 306b may be "lightly doped" because the NLDD region 306a and / or the NLDD region 306b may include a dopant concentration contained in the range of about 1E 11 n-type ions per cm 2 to about 5E 13 n-type ions per cm 2 , while the source / drain region 222a and / or the source / drain region 222b may each include a dopant concentration contained in the range of about 1E 14 n-type ions per cm 2 to about 1E 16 n-type ions per cm 2 . However, other values of these ranges are also within the scope of the present disclosure.

[0111] The NLDD region 306a and / or the NLDD region 306b may include a dopant concentration contained in the range of about 1E 11 n-type ions per cm 2 to about 5E 13 n-type ions per cm 2 to achieve a sufficiently high on-mode current for the high-voltage semiconductor device 212, and / or to achieve a sufficiently low off-mode current leakage for the high-voltage semiconductor device 212. However, other values of this range are also within the scope of the present disclosure.

[0112] The high-voltage transistor structure 212 may include a gate structure 224 between the source / drain region 222a and the source / drain region 222b. The gate structure 224 may be formed of one or more layers and / or one or more materials. The gate structure 224 may include one or more metal materials, one or more high dielectric constant (high-k) materials, and / or one or more other types of materials. For example, the gate structure 224 may include a work function adjustment layer, an interface layer, and / or a metal electrode layer, etc.

[0113] The high-voltage transistor structure 212 may include a gate oxide layer 226. In some embodiments, the gate oxide layer 226 is included on the substrate 208. In some embodiments, the gate oxide layer 226 is recessed into the substrate 208 such that the top surface of the gate oxide layer 226 is at substantially the same height as the top surfaces of the plurality of STI regions 234. The gate oxide layer 226 may be included between the source / drain region 222a and the source / drain region 222b. In some embodiments, the top surfaces of the source / drain region 222a and the source / drain region 222b are at substantially the same height as the top surface of the gate oxide layer 226. In some embodiments, the top surfaces of the source / drain region 222a and the source / drain region 222b are lower than the top surface of the gate oxide layer 226. In some embodiments, the top surfaces of the source / drain region 222a and the source / drain region 222b are at substantially the same height as the top surfaces of the plurality of STI regions 234. In some embodiments, the top surfaces of the source / drain region 222a and the source / drain region 222b are lower than the top surfaces of the plurality of STI regions 234.

[0114] The gate oxide layer 226 may include an oxide material (e.g., HTO and / or another type of gate oxide) and / or another type of dielectric material. The gate oxide layer 226 may have a sufficient thickness to support the high voltage (e.g., 6 volts, 8 volts, and / or higher voltages) processed by the high-voltage transistor structure 212. For example, the thickness of the gate oxide layer 226 may be in the range of about 150 angstroms to about 300 angstroms to support medium to high voltages processed by the high-voltage transistor structure 212. However, other values within this range are also within the scope of the present disclosure.

[0115] The high-voltage transistor structure 212 includes a portion 226a of the gate oxide layer 226 under the gate structure 224. The portion 226a can be located between the gate structure 224 and the substrate 208 and can be within the perimeter of the gate structure 224. The portion 226a can at least partially cover portions of the P-well region 304, at least partially cover portions of the NLDD region 306a, and / or at least partially cover portions of the NLDD region 306b, and so on. The high-voltage transistor structure 212 also includes portions 226b and / or 226c of the gate oxide layer 226 that are not under the gate structure 224 but outside the perimeter of the gate structure 224. The inclusion of portions 226b and / or 226c of the gate oxide layer 226 causes the gate oxide layer 226 to extend laterally outward from the gate structure 224 (e.g., laterally outward from under the gate structure 224) such that portions 226b and / or 226c of the gate oxide layer 226 are not under the gate structure 224. The portion 226b can extend between the gate structure 224 and the source / drain region 222a and can at least partially cover portions of the NLDD region 306a and / or above. The portion 226c can extend between the gate structure 224 and the source / drain region 222b and can at least partially cover portions of the NLDD region 306b and / or above.

[0116] The gate oxide layer 226 can be formed such that portions 226b and / or 226c of the gate oxide layer 226 (e.g., portions that extend laterally outward from the gate structure 224) can be used to adjust the placement or position of the source / drain region 222a and / or portion 222b to prevent or reduce the likelihood of GIDL in the high-voltage transistor structure 212. Specifically, the gate oxide layer 226 can be formed such that portions 226b and / or 226c of the gate oxide layer 226 can be used to adjust the spacing or distance between the gate structure 224 and the source / drain region 222a and / or the source / drain region 222b. Adjusting the spacing or distance between the gate structure 224 and the source / drain region 222a and / or the source / drain region 222b enables a specific profile of the depletion region in the high-voltage semiconductor device 212, thereby preventing GIDL (or reducing the likelihood of GIDL) in the high-voltage transistor structure 212. In combination Figure 3C Example profiles of the depletion region are shown and described.

[0117] As Figure 3A further shown, one or more sidewall spacers 308 can be included over and / or on the multiple sidewalls of the gate structure 224. One or more sidewall spacers 308 can include one or more low dielectric constant (low-k) materials (whose dielectric constant is less than that of silicon oxide (e.g., less than about 3.9)), silicon oxide (SiO x) Silicon oxynitride (SiON), silicon nitride (Si x N y ), silicon oxycarbonitride (SiOCN) and / or other suitable dielectric materials.

[0118] The high-voltage transistor structure 212 may include a first sidewall spacer 308 on a first sidewall of the gate structure 224 facing the source / drain region 222a and a second sidewall spacer 308 on a second sidewall of the gate structure 224 facing the source / drain region 222b. A portion 226b of the gate oxide layer 226 may extend laterally outward beyond the first sidewall spacer 308, and a portion 226c of the gate oxide layer 226 may extend laterally outward beyond the second sidewall spacer 308. The sidewall spacer 308 may include inclined and / or rounded outer sidewalls generated by one or more semiconductor processing operations performed after forming the sidewall spacer 308.

[0119] In some embodiments, the sidewall spacer 308 includes a single-layer sidewall spacer formed during a single sidewall spacer formation process. In some embodiments, the sidewall spacer 308 includes a multi-layer structure. In some embodiments, a single set of one or more sidewall spacer formation operations is performed to form the sidewall spacer 308 of the high-voltage transistor structure 212 and the sidewall spacers of the low-voltage transistor structures 210 included in the semiconductor device 200. Thus, the formation of the sidewall spacer 308 of the high-voltage transistor structure 212 and the formation of the sidewall spacers of the low-voltage transistor structures 210 are integrated into the same process, which reduces the semiconductor processing cost, reduces the semiconductor processing time, and / or reduces the consumption of semiconductor processing resources (e.g., processing chemicals, semiconductor processing facility power) used to form the semiconductor device 200, etc.

[0120] A contact structure 228a (e.g., a source / drain contact or MD) may be included above and / or on the source / drain region 222a. A contact structure 228b (e.g., a source / drain contact or MD) may be included above and / or on the source / drain region 222b. The contact structure 228a and the contact structure 228b may each include a via, an interconnect, a trench, a contact plug, and / or another type of conductive structure. The contact structure 228a and the contact structure 228b may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au) and other examples of conductive materials.

[0121] The contact structures 228a and 228b may be included in the dielectric region 242 of the semiconductor device 200. The dielectric region 242 may include an interlayer dielectric (ILD) layer or another type of dielectric region. The dielectric region 242 may be included above the source / drain regions 222a and 222b, above and / or on the gate structure 224, and / or above and / or on portions 226b and / or 226c of the gate oxide layer 226, etc. The dielectric region 242 may be included to provide electrical isolation and / or insulation, etc., between the gate structure 224 of the high-voltage transistor structure 212 and / or the source / drain regions 222a and 222b. The dielectric region 242 may include silicon nitride (SiN x ), oxide (e.g., silicon oxide (SiO x ), and / or another oxide material), and / or another type of dielectric material.

[0122] Combined Figure 3A The dopant types of the various regions and / or layers shown and described are examples, and the high-voltage transistor structure 212 may include another configuration of dopant types for the various regions and / or layers. For example, the P-well region 304 may alternatively include an n-well region, the NLDD regions 306a and 306b may alternatively include p-well lightly-doped (PLDD) regions, and / or the source / drain regions 222a and 222b may include p-type doped source / drain regions.

[0123] Generally, a high-voltage transistor structure 212 may include a first doped region (e.g., a P-well region 304) in a substrate 208 of a semiconductor device 200, which includes a first dopant type. The high-voltage transistor structure 212 may include a second doped region (e.g., an NLDD region 306b) located in the substrate 208 and adjacent to the first doped region, which includes a second dopant type. The high-voltage transistor structure 212 may include a first source / drain region 222a in the substrate 208, which includes the second dopant type. The high-voltage transistor structure 212 may include a second source / drain region 222b in the substrate 208 and on and / or adjacent to the second doped region, which includes the second dopant type. The high-voltage transistor structure 212 may include a gate structure 224 between the first source / drain region 222a and the second source / drain region 222b. The high-voltage transistor structure 212 may include a gate oxide layer 226 between the first source / drain region 222a and the second source / drain region 222b, wherein a first portion 226a of the gate oxide layer 226 is under the gate structure 224 and between the gate structure 224 and the substrate 208, and at least a second portion (e.g., portion 226b, portion 226b) of the gate oxide layer extends laterally outward from the first portion 226a beyond the gate structure 224.

[0124] Figure 3B A close-up view of a portion of the high-voltage transistor structure 212 is shown. As Figure 3B shown, in some embodiments, one or more silicide layers (e.g., a metal silicide layer such as a titanium silicide layer) 310 are included on the source / drain region 222b to reduce the contact resistance of the source / drain region 222b. In some embodiments, one or more silicide layers 310 are also included on the source / drain region 222a to reduce the contact resistance of the source / drain region 222a.

[0125] Figure 3B One or more dimensions of the high-voltage transistor structure 212 are further shown. As Figure 3BAs shown, the high-voltage transistor structure 212 may include an exemplary dimension D1. The exemplary dimension D1 may correspond to the thickness of the sidewall spacer 308 on the sidewalls of the gate structure 224 of the high-voltage transistor structure 212. In some embodiments, the exemplary dimension D1 includes a range from about 8 nanometers to about 10 nanometers. However, other values within this range are also within the scope of the present disclosure. In some embodiments, the thickness of the sidewall spacer 308 (e.g., the exemplary dimension D1) and the thickness of the sidewall spacer of the low-voltage transistor structure 210 included in the semiconductor device 200 may be approximately the same thickness. The approximately the same thickness of the sidewall spacer 308 and the sidewall spacer of the low-voltage transistor structure 210 included in the semiconductor device 200 may be obtained by process integration of forming the sidewall spacer 308 and the sidewall spacer of the low-voltage transistor structure 210 in the same set of one or more semiconductor processing operations.

[0126] As Figure 3B As further shown, the high-voltage transistor structure 212 may include another exemplary dimension D2. The exemplary dimension D2 may correspond to the width of the portion 226c (or portion 226b) of the gate oxide layer 226 that extends laterally outward from the gate structure 224 of the high-voltage transistor structure 212. The exemplary dimension D2 may also correspond to the distance between the sidewall of the gate structure 224 and the source / drain region 222b (or source / drain region 222a). The exemplary dimension D2 (e.g., the width of portion 226b and / or portion 226c) may be greater than the exemplary dimension D1 (e.g., the thickness of the sidewall spacer 308) such that portion 226b and / or portion 226c extends laterally outward from the sidewall spacer 308. In some embodiments, the exemplary dimension D2 includes a range from about 0.014 micrometers to about 0.05 micrometers. If the exemplary dimension D2 is less than about 0.014 micrometers, the high-voltage transistor structure 212 may experience relatively high GIDL. If the exemplary dimension D2 is greater than about 0.05 micrometers, the drive current of the high-voltage transistor structure 212 may be too low for the high-voltage operation of the high-voltage transistor structure 212. If the exemplary dimension D2 includes a range from about 0.014 micrometers to about 0.05 micrometers, a relatively high device density may be achieved for the semiconductor device 200 while achieving a sufficiently high drive current and a sufficiently low GIDL for the high-voltage transistor structure 212. However, other values within this range are also within the scope of the present disclosure.

[0127] In some embodiments, the exemplary dimension D2 may be selected based on one or more parameters or attributes associated with the high-voltage transistor structure 212. For example, the exemplary dimension D2 may be selected to adjust the spacing or distance between the gate structure 224 and the source / drain region 222b and / or the source / drain region 222a based on parameters and / or attributes of the high-voltage transistor structure 212, such as the thickness of the gate oxide layer 226, the thickness of the sidewall spacer 308 (e.g., the exemplary dimension D1), the gate length, the drain voltage of the high-voltage transistor structure 212, the gate voltage of the high-voltage transistor structure 212, and / or another parameter or attribute of the high-voltage transistor structure 212. As an example, for a larger drain voltage and / or a larger gate voltage, the exemplary dimension D2 may be increased. As an example, for a smaller drain voltage and / or a smaller gate voltage, the exemplary dimension D2 may be decreased. The exemplary dimension D2 may be selected to adjust the spacing or distance between the gate structure 224 and the source / drain region 222b and / or the source / drain region 222a to achieve a relatively low GIDL (e.g., GIDL that meets a threshold) based on these parameters and / or attributes of the high-voltage transistor structure 212.

[0128] Figure 3C An exemplary profile of the depletion region 312 of the high-voltage transistor structure 212 is shown. The exemplary profile of the depletion region 312 is due to the spacing provided by the gate oxide layer 226 between the gate structure 224 and the source / drain region 222b. As Figure 3C shown, the depletion region 312 appears in the P-well region 304 and the NLDD region 306b. Due to the spacing provided by the gate oxide layer 226 between the gate structure 224 and the source / drain region 222b, the depletion region 312 curves around the source / drain region 222b and does not encroach on the source / drain region 222b. If the gate oxide layer 226 extends laterally outward from the gate structure 224 towards the source / drain region 222a, the depletion region 312 may conform to a similar profile around the source / drain region 222a.

[0129] As described above, provide Figures 3A to 3C as an example. Other examples may be different from those described with respect to Figures 3A to 3C description.

[0130] Figure 4A and Figure 4B are graphs of exemplary tuning parameters of the high-voltage transistor structure 212 described herein. Figure 4AIllustrated is an example tuning parameter 400 corresponding to GIDL 402 of the high-voltage transistor structure 212 as a function of the distance 404 (or pitch) between the gate structure 224 and the source / drain regions 222a and / or 222b of the high-voltage transistor structure 212 (corresponding to example dimension D2). Figure 4B Illustrated is an example tuning parameter 406 corresponding to the drain saturation current 408 of the high-voltage transistor structure 212 as a function of the distance 404 (or pitch) between the gate structure 224 and the source / drain regions 222a and / or 222b of the high-voltage transistor structure 212.

[0131] Portions 226b and / or 226c of the gate oxide layer 226 can enable the distance 404 (or pitch) between the gate structure 224 and the source / drain regions 222a and / or 222b of the high-voltage transistor structure 212 to be within the range described above for example dimension D2. As Figure 4A and Figure 4B shown, forming the gate structure 224 and the source / drain regions 222a and / or 222b such that the distance 404 is within the above example dimension D2 can achieve a relatively low GIDL 402 for the high-voltage transistor structure 212 and have a minimal or even no impact on the drain saturation current 408 of the high-voltage transistor structure 212.

[0132] As described above, providing Figure 4A and Figure 4B as examples. Other examples may be different from those described with respect to Figure 4A and Figure 4B described.

[0133] Figures 5A to 5M is a diagram of an example implementation 500 described herein. The example implementation 500 includes an example of forming the high-voltage transistor structure 212 of the semiconductor device 200 described herein.

[0134] As Figure 5AAs shown, an exemplary embodiment 500 of forming a high-voltage transistor structure 212 may include a plurality of semiconductor processing operations. For example, an STI formation operation 502 may be performed to form STI regions 234 in a substrate 208 of a semiconductor device. As another example, a well implantation operation 504 may be performed to form a deep well 302 and a P-well region 304 in the substrate 208. As another example, a lightly doped implantation operation 506 may be performed to form an NLDD region 306a and an NLDD region 306b in the substrate 208. As another example, an oxide formation operation 508 may be performed to form an oxide layer on and / or over the substrate 208. As another example, a gate formation operation 510 may be performed to form a gate structure 224 of the high-voltage transistor structure 212. As another example, a spacer formation operation 512 may be performed to form a plurality of sidewall spacers 308 on a plurality of sidewalls of the gate structure 224. As another example, a gate oxide etch operation 514 (also referred to as a source / drain opening operation) may be performed to etch the oxide layer to form a gate oxide layer 226 of the high-voltage transistor structure 212. As another example, a source / drain implantation operation 516 may be performed to form source / drain regions 222a and source / drain regions 222b of the high-voltage transistor structure 212 using the gate oxide layer 226 as a self-aligned implantation mask. As another example, an ILD formation operation 518 may be performed to form a dielectric region 242 of the semiconductor device 200. As another example, an MD formation operation 520 may be performed to form contact structures 228a and contact structures 228b.

[0135] In some embodiments, one or more of the semiconductor processing operations 502-520 described in connection with exemplary embodiment 500 may be performed by one or more of the semiconductor processing tools 102-114 and / or by the wafer / die transfer tool 116. In some embodiments, one or more of the semiconductor processing operations 502-520 described in connection with exemplary embodiment 500 may be performed by another semiconductor processing tool. In some embodiments, one or more of the semiconductor processing operations 502-520 may be performed to form one or more low-voltage transistor structures 210 (e.g., one or more low-voltage finFET structures) in the semiconductor device 200 such that the processing of the high-voltage transistor structure 212 and the processing of one or more low-voltage transistor structures 210 are integrated into the same set of processing operations. For example, a single sidewall spacer formation process (e.g., a single spacer formation operation 512) may be performed to form a plurality of sidewall spacers 308 on a plurality of sidewalls of the gate structure 224 of the high-voltage transistor structure 212 and a plurality of sidewall spacers on the gate structures of one or more low-voltage transistor structures 210.

[0136] Turning to Figure 5B, a substrate 208 can be provided. The substrate 208 can be provided as a semiconductor wafer, a semiconductor die, and / or another type of semiconductor substrate. In some embodiments, the substrate 208 can be a doped substrate, such as a semiconductor substrate doped with one or more p-type dopants, a semiconductor substrate doped with one or more n-type dopants, and / or another type of doped substrate. In some embodiments, the substrate 208 has a bulk resistivity (or volumetric resistivity) that includes a value in the range of from about 1 ohm-centimeter to about 100 ohm-centimeters. However, other values within this range are also within the scope of the present disclosure.

[0137] As Figure 5C shown, an STI formation operation 502 can be performed to form a plurality of STI regions 234 in the substrate 208. To form the plurality of STI regions 234, a plurality of recesses can be formed in the substrate 208, and a material for the plurality of STI regions 234 can be deposited in the plurality of recesses.

[0138] In some embodiments, a pattern in a photoresist layer is used to etch the substrate 208 to form the plurality of recesses. In these embodiments, a deposition tool 102 forms a photoresist layer on the substrate 208. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etch tool 108 etches the substrate 208 based on the pattern to form the plurality of recesses in the substrate 208. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etch the substrate 208 based on the pattern.

[0139] The deposition tool 102 can deposit the material for the plurality of STI regions 234 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination Figure 1 with another type of deposition operation described, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 planarizes the plurality of STI regions 234 after the deposition tool 102 deposits the plurality of STI regions 234.

[0140] As Figure 5DAs shown, well implant operation 504 can be performed to form deep well 302 and P-well region 304 in substrate 208. For example, deep well 302 can be formed in and / or on substrate 208. As another example, P-well region 304 can be formed in substrate 208 and / or on deep well 302.

[0141] In some embodiments, ion implantation tool 114 forms deep well 302 by performing an ion implantation operation to implant ions (e.g., p-type ions, n-type ions) into substrate 208 to form deep well 302. Ion implantation tool 114 can direct an ion beam towards substrate 208 such that the ions are implanted beneath the surface of substrate 208 to dope substrate 208. Additionally and / or alternatively, deposition tool 102 can deposit deep well 302 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, another type of deposition operation described in conjunction Figure 1 with and / or other suitable deposition operations. In some embodiments, planarization tool 110 planarizes deep well 302 after deposition tool 102 deposits deep well 302.

[0142] In some embodiments, ion implantation tool 114 forms P-well region 304 by performing an ion implantation operation to implant ions (e.g., p-type ions, n-type ions) into substrate 208 to form P-well region 304. Ion implantation tool 114 can direct an ion beam towards substrate 208 such that the ions are implanted beneath the surface of substrate 208 to dope substrate 208. Additionally and / or alternatively, deposition tool 102 can deposit P-well region 304 in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, another type of deposition operation described in conjunction Figure 1 with, and / or another suitable deposition operation. In some embodiments, planarization tool 110 planarizes P-well region 304 after deposition tool 102 deposits P-well region 304. In some embodiments, P-well region 304 can be formed such that the dopant concentration in P-well region 304 can include from about 1E 11 p-type ions per cm 2 to about 5E 13 p-type ions per cm 2 within the range. However, other values of this range are also within the scope of the present disclosure.

[0143] As Figure 5EAs shown, a lightly doped implantation operation 506 can be performed to form NLDD regions 306a and 306b in the substrate 208. NLDD region 306a can be formed in and / or on a portion of the P-well region 304. NLDD region 306b can be formed in and / or on another portion of the P-well region 304. In some embodiments, an implantation mask is used to mask off other portions of the P-well region 304 such that the NLDD regions 306a and 306b are formed only in those portions of the P-well region 304. In some embodiments, the ion implantation tool 114 forms the NLDD regions 306a and 306b by performing an ion implantation operation to implant ions (e.g., p-type ions, n-type ions) into the substrate 208 to form the NLDD regions 306a and 306b in the P-well region 304. The ion implantation tool 114 can direct an ion beam toward the P-well region 304 such that ions are implanted into the P-well region 304 to form the NLDD regions 306a and 306b. The NLDD regions 306a and 306b can be formed to include a dopant concentration in the range of from about 1E 11 n-type ions per cm 2 to about 5E 13 n-type ions per cm 2 to achieve a high enough on-mode current for the high-voltage transistor structure 212, and / or to achieve a low enough off-mode current leakage for the high-voltage transistor structure, etc. However, other values within this range are also within the scope of the present disclosure.

[0144] As Figure 5F shown, an oxide formation operation 508 can be performed to form an oxide layer 522 over and / or on the substrate 208. In some embodiments, the oxide layer 522 can be formed over and / or on the top surface of the P-well region 304, and over and / or on the top surfaces of the NLDD regions 306a and 306b. In some embodiments, the oxide formation operation 508 can include a high-temperature thermal oxidation operation to oxidize the NLDD regions 306a and 306b and multiple portions of the P-well region 304 to form the oxide layer 522 in the substrate 208 (e.g., multiple portions in the substrate 208 corresponding to the NLDD regions 306a and 306b and those portions of the P-well region 304). In these embodiments, the oxide layer 522 can be recessed in the substrate 208 such that the top surface of the oxide layer 522 is at approximately the same height as the top surfaces of the multiple STI regions 234. Alternatively, the NLDD regions 306a and 306b and the P-well region 304 can be removed by etching to form a recess, in which the oxide layer 522 is deposited and recessed in the substrate 208.

[0145] The deposition tool 102 can deposit the oxide layer 522 in PVD operations, ALD operations, CVD operations, spin coating operations, epitaxial operations, oxidation operations (e.g., high-temperature thermal oxidation operations), combined with Figure 1 another type of deposition operation described, and / or another suitable deposition operation. In some embodiments, the planarization tool 110 planarizes the oxide layer 522 after the deposition tool 102 deposits the oxide layer 522.

[0146] As Figure 5G shown, a gate formation operation 510 can be performed to form a gate structure 224 over and / or on the oxide layer 522. The deposition tool 102 and / or the plating tool 112 can deposit the gate structure 224 in CVD operations, PVD operations, ALD operations, electroplating operations, another deposition operation combined with Figure 1 described above and / or another suitable deposition operation. In some embodiments, a seed layer is first deposited, and the gate structure 224 is deposited on the seed layer.

[0147] As Figure 5H shown, a spacer formation operation 512 can be performed to form a plurality of sidewall spacers 308 on multiple sidewalls of the gate structure 224. The deposition tool 102 can deposit the plurality of sidewall spacers 308 in PVD operations, ALD operations, CVD operations, epitaxial operations, oxidation operations, combined with Figure 1 another type of deposition operation described and / or another suitable deposition operation. In some embodiments, the deposition tool 102 conformally deposits the material of the plurality of sidewall spacers 308 on the multiple sidewalls and the top surface of the gate structure 224 and on the top surface of the oxide layer 522. The etch tool 108 can then perform an etch-back operation to remove the material of the plurality of sidewall spacers 308 from the top surface of the oxide layer 522 and the top surface of the gate structure 224. Thus, the plurality of sidewall spacers 308 can remain on the multiple sidewalls of the gate structure 224.

[0148] As Figure 5I shown, a gate oxide etch operation 514 can be performed to remove multiple portions in the oxide layer 522 to form a gate oxide layer 226 from the oxide layer 522. The etch tool 108 can perform an etch operation to remove multiple portions of the oxide layer 522 such that portions 226b and / or 226c of the gate oxide layer 226 extend laterally outward from under the gate structure 224 (and laterally outward from the plurality of sidewall spacers 308), while portion 226a of the gate oxide layer 226 is included under the gate structure 224. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. The etch operation causes the outer sidewalls of the plurality of sidewall spacers 308 to become rounded or slanted, as Figure 5Ias shown in the example in

[0149] As Figure 5J shown in, a source / drain implantation operation 516 can be performed to form a source / drain region 222a and a source / drain region 222b. The source / drain region 222a can be formed on and / or in the NLDD region 306a. The source / drain region 222a can be formed at a first side of the gate structure 224 between the STI region 234 and a portion 226b of the gate oxide layer 226. The source / drain region 222b can be formed on and / or in the NLDD region 306b. The source / drain region 222b can be formed at a second side of the gate structure 224 between the STI region 234 and a portion 226c of the gate oxide layer 226.

[0150] In some embodiments, the ion implantation tool 114 forms the source / drain regions 222a and 222b by performing one or more ion implantation operations to implant ions 524 (e.g., p-type ions, n-type ions) into the substrate 208 (e.g., into the NLDD regions 306a and 306b in the substrate 208). The ion implantation tool 114 can direct an ion beam toward the substrate 208 such that the ions 524 are implanted beneath the top surface of the substrate 208 to form the source / drain regions 222a and 222b. Additionally and / or alternatively, since the oxide layer 522 is recessed in the substrate 208, etching the oxide layer 522 can leave a plurality of depressions in the substrate 208 (e.g., in the NLDD regions 306a and / or 306b in the substrate 208), and a silicon region can be formed in the plurality of depressions using the deposition tool 102, which can then be doped using the ion implantation tool 114 to form the source / drain regions 222a and 222b. Or, without additional epitaxial growth, the NLDD regions 306a and / or 306b are doped in a plurality of regions below the oxide layer 522 to form the source / drain regions 222a and 222b, as Figure 5J shown in the example in

[0151] The source / drain region 222a and the source / drain region 222b can each be formed to include containing approximately 1E 14 n-type ions per cm 2 to about 1E 16 n-type ions per cm 2a dopant concentration within a range to achieve a sufficiently high on-mode current for the high-voltage transistor structure 212 and / or to achieve a sufficiently low off-mode current leakage for the high-voltage transistor structure 212. However, other values within these ranges are also within the scope of the present disclosure.

[0152] A source / drain implantation operation 516 can be performed to dope the substrate 208 (or multiple epitaxially grown silicon regions) using the gate oxide layer 226 as a self-aligned implantation mask to form source / drain regions 222a and source / drain regions 222b. Specifically, portions 226b and / or 226c of the gate oxide layer 226 that extend laterally outward from a portion 226a of the gate oxide layer 226 and that extend laterally outward from under the gate structure 224 can be used as a self-aligned implantation mask to define the locations in the substrate 208 (or multiple epitaxially grown silicon regions) where the source / drain regions 222a and source / drain regions 222b are implanted. At positions of the substrate 208 covered by the gate oxide layer 226, implantation of ions 524 into the substrate 208 is blocked, while at positions of the exposed substrate 208 (e.g., positions not covered by the gate oxide layer 226), implantation of ions 524 into the substrate 208 is allowed.

[0153] The gate oxide etch operation 514 described above in connection with Figure 5I can be performed to achieve a specific distance or threshold distance (e.g., example dimension D2) between the sidewalls of the gate structure 224 and the source / drain regions 222a and / or source / drain regions 222b. This enables the source / drain regions 222a and / or source / drain regions 222b to be formed in a self-aligned manner, where the distance between the gate structure 224 and the source / drain regions 222a and / or source / drain regions 222b is adjusted or optimized to reduce, minimize, and / or prevent GIDL in the high-voltage transistor structure 212. For example, the threshold distance (e.g., example dimension D2) can include a range from about 0.014 micrometers to about 0.05 micrometers, as described above in connection with Figure 3B However, other values within this range are also within the scope of the present disclosure. In some embodiments, the threshold distance can be selected based on and / or to achieve or satisfy the GIDL parameters (or GIDL threshold) of the high-voltage transistor structure 212. In some embodiments, the threshold distance can be selected based on the gate-to-drain spacing parameter of the high-voltage transistor structure 212, the drain voltage of the high-voltage transistor structure 212, the gate voltage of the high-voltage transistor structure 212, and / or based on another parameter or property of the high-voltage transistor structure 212.

[0154] As Figure 5KAs shown, an ILD formation operation 518 can be performed to form the dielectric region 242. The dielectric region 242 can be formed over and / or on the source / drain regions 222a and / or 222b, over and / or on the gate structure 224, over and / or on the exposed portions 226b and 226c of the gate oxide layer 226, and / or over and / or on the plurality of STI regions 234. The deposition tool 102 can deposit the dielectric region 242 in one or more PVD operations, one or more ALD operations, one or more CVD operations, one or more epitaxial operations, one or more oxidation operations, one or more combination Figure 1 with another type of deposition operation described herein, and / or one or more other suitable deposition operations. In some embodiments, the planarization tool 110 planarizes the dielectric region 242 after the deposition tool 102 deposits the dielectric region 242.

[0155] As Figure 5L and Figure 5M shown, an MD formation operation 520 can be performed to form the contact structures 228a and 228b over and / or on the source / drain region 222a and the source / drain region 222b, respectively. As shown in 5L in the figure, in the MD formation operation 520, a plurality of recesses 526 can be formed in the dielectric region 242 and / or through the dielectric region 242 to reach the top surfaces of the source / drain region 222a and the source / drain region 222b. The top surfaces of the source / drain region 222a and the source / drain region 222b are exposed through the plurality of recesses 526.

[0156] In some embodiments, a pattern in a photoresist layer is used to etch the dielectric region 242 to form the plurality of recesses 526. In these embodiments, the deposition tool 102 forms a photoresist layer on the dielectric region 242. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches the dielectric region 242 based on the pattern to form the plurality of recesses 526 in the dielectric region 242. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric region 242 based on the pattern.

[0157] As Figure 5MAs shown, as part of the MD formation operation 520, contact structures 228a and 228b can be formed in a plurality of recesses 526. The contact structure 228a can be formed such that the contact structure 228a lands on the source / drain region 222a. The contact structure 228b can be formed such that the contact structure 228b lands on the source / drain region 222b. The deposition tool 102 and / or the plating tool 112 can deposit the contact structures 228a and 228b in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, another deposition operation described above in connection with Figure 1 and / or another suitable deposition operation. In some embodiments, a seed layer is deposited first, and the contact structures 228a and / or 228b are deposited on the seed layer. In some embodiments, after the deposition tool 102 and / or the plating tool 112 deposit the contact structures 228a and / or 228b, the planarization tool 110 planarizes the contact structures 228a and / or 228b.

[0158] In some embodiments, one or more silicide layers 310 (e.g., a metal silicide layer such as a titanium silicide layer) can be formed on the source / drain region 222a and the source / drain region 222b to reduce the contact resistance of the source / drain region 222a and the source / drain region 222b. The silicide layer 310 can be formed on the source / drain region 222a and the source / drain region 222b through the plurality of recesses 526 before the contact structures 228a and 228b are formed. Thus, the contact structures 228a and 228b can be formed on the silicide layers 310 respectively formed on the source / drain region 222a and the source / drain region 222b.

[0159] As described above, provide Figures 5A to 5M as an example. Other examples may be different from those described in connection with Figures 5A to 5M description.

[0160] Figure 6 is a diagram of an example component of the device 600 described herein. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may include one or more devices 600 and / or one or more components of the device 600. As Figure 6 shown, the device 600 can include a bus 610, a processor 620, a memory 630, an input component 640, an output component 650, and / or a communication component 660.

[0161] The bus 610 can include one or more components capable of wired and / or wireless communication between a plurality of components of the device 600. The bus 610 can couple Figure 6Two or more than two components are coupled together, such as via operational coupling, communication coupling, electrical coupling, and / or electro-coupling. For example, bus 610 may include electrical connections (e.g., wires, traces, and / or leads) and / or a wireless bus. Processor 620 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 620 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 620 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0162] Memory 630 may include volatile and / or non-volatile memory. For example, memory 630 may include random access memory (RAM), read-only memory (ROM), a hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 630 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 630 may be a non-transitory computer-readable medium. Memory 630 may store information related to the operation of device 600, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 630 may include one or more memories such as being coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620) via bus 610. The communication coupling between processor 620 and memory 630 may enable processor 620 to read and / or process information stored in memory 630 and / or store messages in memory 630.

[0163] The input component 640 can enable the device 600 to receive inputs, such as user inputs and / or sensed inputs. For example, the input component 640 can include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, switches, sensors, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. The output component 650 can enable the device 600 to provide outputs, such as via a display, a speaker, and / or a light-emitting diode. The communication component 660 can enable the device 600 to communicate with other devices via a wired connection and / or a wireless connection. For example, the communication component 660 can include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0164] The device 600 can perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., the memory 630) can store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 620. The processor 620 can execute the set of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the set of instructions by one or more processors 620 causes the one or more processors 620 and / or the device 600 to perform one or more operations or processes described herein. In some embodiments, one or more operations or processes described herein can be performed using hardwired circuitry instead of or in combination with the instructions. Additionally or alternatively, the processor 620 can be configured to perform one or more operations or processes described herein. Thus, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0165] Figure 6 The number and arrangement of the components shown are provided only as an example. Compared to the components shown in Figure 6 , the device 600 can include additional components, fewer components, different components, or components arranged in a different manner. Additionally or alternatively, a set of components (e.g., one or more components) of the device 600 can perform one or more functions described as being performed by another set of components of the device 600.

[0166] Figure 7 is a flowchart of an example process 700 related to forming a semiconductor device described herein. In some embodiments, Figure 7 one or more of the process blocks of Figure 7One or more process blocks of can be performed by one or more components of apparatus 600, such as processor 620, memory 630, input component 640, output component 650, and / or communication component 660.

[0167] As Figure 7 shown, process 700 can include doping a substrate with a first dopant type to form a first doped region of a semiconductor device (block 710). For example, one or more of semiconductor processing tools 102-114 can dope substrate 208 with the first dopant type to form a first doped region of semiconductor device 200 (e.g., P-well region 304), as described herein.

[0168] As Figure 7 further shown, process 700 can include doping the substrate with a second dopant type to form a second doped region of the semiconductor device adjacent to the first doped region (block 720). For example, one or more of semiconductor processing tools 102-114 can dope substrate 208 with the second dopant type to form a second doped region of semiconductor device 200 adjacent to the first doped region (e.g., NLDD regions 306a, 306b), as described herein.

[0169] As Figure 7 further shown, process 700 can include forming an oxide layer over the first doped region and over the second doped region (block 730). For example, one or more of semiconductor processing tools 102-114 can form an oxide layer 522 over the first doped region and over the second doped region, as described herein.

[0170] As Figure 7 further shown, process 700 can include forming a gate structure of a high-voltage transistor structure of the semiconductor device over the oxide layer (block 740). For example, one or more of semiconductor processing tools 102-114 can form a gate structure 224 of high-voltage transistor structure 212 of semiconductor device 200 over oxide layer 522, as described herein.

[0171] As Figure 7 further shown, process 700 can include performing an etching operation to remove material from the oxide layer to form a gate oxide layer of the high-voltage transistor structure (block 750). For example, one or more of semiconductor processing tools 102-114 can perform an etching operation to remove material from oxide layer 522 to form a gate oxide layer 226 of high-voltage transistor structure 212, as described herein. In some embodiments, the etching operation causes portions (e.g., portions 226b, 226c) of the gate oxide layer 226 to extend laterally outward from the gate structure 224.

[0172] As Figure 7 Further shown in Figure 7 , process 700 may include forming multiple source / drain regions (block 760) of a high-voltage transistor structure using a gate oxide layer as a self-alignment pattern. For example, one or more of semiconductor processing tools 102-114 may use gate oxide layer 226 as a self-alignment pattern to form multiple source / drain regions (e.g., source / drain region 222a, source / drain region 222b) of high-voltage transistor structure 212, as described herein.

[0173] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0174] In a first embodiment, forming multiple source / drain regions includes doping substrate 208 using gate oxide layer 226 as a self-alignment implantation mask.

[0175] In a second embodiment, separately or in combination with the first embodiment, performing an etching operation to remove material from oxide layer 522 includes performing an etching operation such that gate oxide layer 226 extends laterally outward from gate structure 224 by a distance that meets a threshold distance (e.g., dimension D2).

[0176] In a third embodiment, separately or in combination with one or more of the first embodiment and the second embodiment, the threshold distance is included in a range from about 0.014 micrometers to about 0.05 micrometers.

[0177] In a fourth embodiment, separately or in combination with one or more of the first embodiment to the third embodiment, the threshold distance is based on at least one of a gate-to-drain spacing parameter of high-voltage transistor structure 212, a drain voltage of high-voltage transistor structure 212, or a gate voltage of high-voltage transistor structure 212.

[0178] In a fifth embodiment, separately or in combination with one or more of the first embodiment to the fourth embodiment, the threshold distance is based on a gate-induced drain leakage current parameter of high-voltage transistor structure 212.

[0179] In a sixth embodiment, separately or in combination with one or more of the first embodiment to the fifth embodiment, process 700 includes performing a single sidewall spacer formation process to form sidewall spacers 308 on the sidewalls of gate structure 224 before performing the etching operation.

[0180] In a seventh embodiment, separately or in combination with one or more of the first embodiment to the sixth embodiment, the etching operation causes a portion of gate oxide layer 226 to extend laterally outward from sidewall spacers 308.

[0181] In the eighth embodiment, individually or in combination with one or more of the first to seventh embodiments, performing a single sidewall spacer formation process includes performing a single sidewall spacer formation process to form sidewall spacers on the sidewalls of a gate structure and to form another sidewall spacer on another gate structure of a low-voltage finFET structure (e.g., low-voltage transistor structure 210) of the semiconductor device 200.

[0182] Although Figure 7 multiple example blocks of process 700 are shown, in some embodiments, process 700 includes additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner compared to the blocks depicted in Figure 7 In addition or alternatively, two or more blocks in process 700 may be performed in parallel.

[0183] Thus, a high-voltage transistor may include multiple source / drain regions, a gate structure, and a gate oxide layer such that the gate structure can selectively control a channel region between the multiple source / drain regions. The gate oxide layer may extend laterally outwardly toward one or more of the multiple source / drain regions such that at least a portion of the gate oxide layer is not under the gate structure. The gate oxide layer extending laterally outwardly from under the gate structure enables the gate oxide layer to be used as a self-alignment structure for forming the multiple source / drain regions of the high-voltage transistor. Specifically, compared to if the extended gate oxide layer were completely contained within the perimeter of the gate structure, the gate oxide layer extending laterally outwardly from under the gate structure enables the gate oxide layer to be used to form the multiple source / drain regions at a greater spacing from the gate structure. This results in less depletion region encroachment on the multiple source / drain regions compared to if the extended gate oxide layer were completely contained within the perimeter of the gate structure, and thus reduces (or eliminates) GIDL in the high-voltage transistor. Reduced GIDL in the high-voltage transistor can reduce the standby power consumption of the high-voltage transistor and / or can reduce the heat dissipation in the high-voltage transistor, which can increase the service life of the high-voltage transistor.

[0184] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first doped region in a substrate of the semiconductor device, which includes a first dopant type. The semiconductor device includes a second doped region located in the substrate and adjacent to the first doped region, which contains a second dopant type. The semiconductor device includes a first source / drain region of a high-voltage transistor structure included in the semiconductor device, which is in the substrate and includes the second dopant type. The semiconductor device includes a second source / drain region of the high-voltage transistor structure in the substrate and on the second doped region, which includes the second dopant type. The semiconductor device includes a gate structure of the high-voltage transistor structure located between the first source / drain region and the second source / drain region. The semiconductor device includes a gate oxide layer of the high-voltage transistor structure located between the first source / drain region and the second source / drain region, wherein a first portion of the gate oxide layer is under the gate structure and between the gate structure and the substrate, and wherein a second portion of the gate oxide layer extends laterally outward beyond the gate structure and is located between the second source / drain region and the first portion of the gate oxide layer. In some embodiments, the semiconductor device further includes: sidewall spacers on a sidewall of the gate structure facing the second source / drain region, wherein the second portion of the gate oxide layer extends laterally outward beyond the sidewall spacers. In some embodiments, the sidewall spacers include a single-layer sidewall spacer. In some embodiments, the second portion of the gate oxide layer at least partially includes on a portion of the second doped region. In some embodiments, the first portion of the gate oxide layer is at least partially on the second doped region. In some embodiments, the gate oxide layer includes a third portion that extends laterally outward beyond the gate structure and is between the first source / drain region and the first portion of the gate oxide layer. In some embodiments, the semiconductor device further includes: a third doped region containing the second dopant type in the substrate, wherein the first source / drain region is included on the third doped region, and wherein the third portion of the gate oxide layer includes on a portion of the third doped region.

[0185] As described in more detail above, some embodiments described herein provide a method. The method includes doping a substrate with a first dopant type to form a first doped region of a semiconductor device. The method includes doping the substrate with a second dopant type to form a second doped region of the semiconductor device adjacent to the first doped region. The method includes forming an oxide layer over the first doped region and over the second doped region. The method includes forming a gate structure of a high-voltage transistor structure of the semiconductor device over the oxide layer. The method includes performing an etching operation to remove material from the oxide layer to form a gate oxide layer of the high-voltage transistor structure, wherein the etching operation causes a portion of the gate oxide layer to extend laterally outward from the gate structure. The method includes using the gate oxide layer as a self-aligned pattern to form a plurality of source / drain regions of the high-voltage transistor structure. In some embodiments, forming the plurality of source / drain regions includes doping the substrate using the gate oxide layer as a self-aligned implantation mask. In some embodiments, performing the etching operation to remove the material from the oxide layer includes performing the etching operation such that the gate oxide layer extends laterally outward from the gate structure a distance that meets a threshold distance. In some embodiments, the threshold distance includes a range from about 0.014 micrometers to about 0.05 micrometers. In some embodiments, the threshold distance is based on at least one of: a gate-to-drain spacing parameter of the high-voltage transistor structure, a drain voltage of the high-voltage transistor structure, or a gate voltage of the high-voltage transistor structure. In some embodiments, the threshold distance is based on a gate-induced drain leakage current parameter of the high-voltage transistor structure. In some embodiments, the method further includes: prior to performing the etching operation, performing a single sidewall spacer formation process to form sidewall spacers on sidewalls of the gate structure. In some embodiments, the etching operation causes the portion of the gate oxide layer to extend laterally outward from the sidewall spacers. In some embodiments, performing the single sidewall spacer formation process includes: performing the single sidewall spacer formation process to form the sidewall spacers on the sidewalls of the gate structure and to form another sidewall spacer on another gate structure of a low-voltage fin field-effect transistor (finFET) structure of the semiconductor device.

[0186] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes a low-voltage device region. The semiconductor device includes a high-voltage device region. The semiconductor device includes an isolation region between the low-voltage device region and the high-voltage device region, wherein the low-voltage device region includes one or more low-voltage finFET structures, wherein the high-voltage device region includes a high-voltage transistor structure, and wherein the high-voltage transistor structure includes a first source / drain region, a second source / drain region, a gate structure between the first source / drain region and the second source / drain region, and a gate oxide layer between the first source / drain region and the second source / drain region, wherein a first portion of the gate oxide layer is under the gate structure and between the gate structure and the substrate, and wherein a second portion of the gate oxide layer extends laterally outward beyond the gate structure and is located between the first source / drain region and the first portion of the gate oxide layer, and wherein a third portion of the gate oxide layer extends laterally outward beyond the gate structure and is located between the second source / drain region and the first portion of the gate oxide layer. In some embodiments, the low-voltage finFET structure of the one or more low-voltage finFET structures includes: a fin structure; and a low-voltage gate structure surrounding three sides of the fin structure, wherein a portion of the low-voltage transistor structure on the fin structure and the gate structure of the high-voltage transistor structure are at substantially the same height in the semiconductor device. In some embodiments, the high-voltage transistor structure further includes: a first single-layer sidewall spacer on a first sidewall of the gate structure facing the first source / drain region, wherein the second portion of the gate oxide layer extends laterally outward beyond the first single-layer sidewall spacer; and a second single-layer sidewall spacer on a second sidewall of the gate structure facing the second source / drain region, wherein the third portion of the gate oxide layer extends laterally outward beyond the second single-layer sidewall spacer. In some embodiments, the high-voltage transistor structure further includes: a sidewall spacer on a sidewall of the gate structure, wherein a width of the second portion of the gate oxide layer is greater than a thickness of the sidewall spacer.

[0187] As used herein, "meeting a threshold" can refer, depending on the context, to a value that is greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc.

[0188] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present utility model. Those skilled in the art should understand that they can easily use the present utility model as a basis for designing or modifying other processes and structures to achieve the same purposes as the embodiments described herein and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present utility model, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present utility model.

Claims

1. A semiconductor device, characterized in that, Comprising: A first doped region, containing a first dopant type, in the substrate of the semiconductor device; A second doped region, containing a second dopant type, in the substrate and adjacent to the first doped region; A first source / drain region of a high-voltage transistor structure included in the semiconductor device, including the second dopant type in the substrate; A second source / drain region of the high-voltage transistor structure, including the second dopant type in the second doped region on the substrate; A gate structure of the high-voltage transistor structure, between the first source / drain region and the second source / drain region; And A gate oxide layer of the high-voltage transistor structure, between the first source / drain region and the second source / drain region, wherein a first portion of the gate oxide layer is under the gate structure and between the gate structure and the substrate, and wherein a second portion of the gate oxide layer extends laterally outward beyond the gate structure and between the second source / drain region and the first portion of the gate oxide layer.

2. The semiconductor device according to claim 1, wherein Further comprising: Sidewall spacers, on sidewalls of the gate structure facing the second source / drain region, wherein the second portion of the gate oxide layer extends laterally outward beyond the sidewall spacers.

3. The semiconductor device according to claim 1, wherein The second portion of the gate oxide layer at least partially covers a portion of the second doped region.

4. The semiconductor device according to claim 3, wherein The first portion of the gate oxide layer is at least partially on the second doped region.

5. The semiconductor device according to claim 1, wherein The gate oxide layer includes a third portion that extends laterally outward beyond the gate structure and between the first source / drain region and the first portion of the gate oxide layer.

6. The semiconductor device according to claim 5, wherein, Further comprising: A third doped region, containing the second dopant type, in the substrate, wherein the first source / drain region is on the third doped region, and wherein the third portion of the gate oxide layer is on a portion of the third doped region.

7. A semiconductor device, characterized in that, Comprising: A substrate; A low-voltage device region; A high-voltage device region; and An isolation region between the low-voltage device region and the high-voltage device region, wherein the low-voltage device region includes one or more low-voltage fin field-effect transistor structures, wherein the high-voltage device region includes a high-voltage transistor structure, and wherein the high-voltage transistor structure includes: A first source / drain region; A second source / drain region; A gate structure between the first source / drain region and the second source / drain region; and A gate oxide layer between the first source / drain region and the second source / drain region, wherein a first portion of the gate oxide layer is under the gate structure and between the gate structure and the substrate, and wherein a second portion of the gate oxide layer extends laterally outward beyond the gate structure and between the first source / drain region and the first portion of the gate oxide layer, and wherein a third portion of the gate oxide layer extends laterally outward beyond the gate structure and between the second source / drain region and the first portion of the gate oxide layer.

8. The semiconductor device according to claim 7, wherein One of the one or more low-voltage fin field-effect transistor structures includes: A fin structure; and A low-voltage gate structure surrounding three sides of the fin structure, wherein a portion of the low-voltage gate structure on the fin structure and the gate structure of the high-voltage transistor structure are at substantially the same height in the semiconductor device.

9. The semiconductor device according to claim 7, wherein The high-voltage transistor structure further includes: A first single-layer sidewall spacer on a first sidewall of the gate structure facing the first source / drain region, wherein the second portion of the gate oxide layer extends laterally outward beyond the first single-layer sidewall spacer; and A second single-layer sidewall spacer on a second sidewall of the gate structure facing the second source / drain region, wherein the third portion of the gate oxide layer extends laterally outward beyond the second single-layer sidewall spacer.

10. The semiconductor device according to claim 7, wherein, The high-voltage transistor structure further includes: A sidewall spacer on the sidewall of the gate structure, wherein the width of the second portion of the gate oxide layer is greater than the thickness of the sidewall spacer.

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