Package structure

Abstract

The utility model discloses a packaging structure. The packaging structure provided by the embodiment of the utility model comprises a packaging substrate, the packaging substrate is provided with a first through hole, a first surface and a second surface opposite to the first surface, and the first surface is used for electric connection; the first packaging object is arranged in the first through hole, and the electric connection surface of the first packaging object is flush with the first surface; and the connecting layer is used for electrically connecting the electric connecting surface of the first packaging object with the first surface. According to the embodiment of the utility model, the packaging process can be simplified, and the packaging cost is reduced.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor packaging, in particular to a packaging structure. Background Art

[0002] Currently, through advanced packaging, the integration degree of electronic components can be improved, and the geometric size and packaging weight of the package can be reduced.

[0003] TSV (Through Silicon Via) refers to the fabrication of vertical conduction between chips and between wafers. Realizing vertical electrical interconnection of silicon vias is one of the key technologies for 3D advanced packaging. However, the TSV fabrication process is complex and the cost is relatively high. Therefore, how to provide a packaging structure with a simple fabrication process and low fabrication cost has become an urgent technical problem to be solved. Summary of the Utility Model

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. For this purpose, the utility model provides a packaging structure, which can simplify the packaging process and reduce the packaging cost.

[0005] According to the packaging structure of the embodiment of the utility model, the packaging structure includes:

[0006] A packaging substrate, which is provided with a first through hole, a first surface and a second surface opposite to the first surface, and the first surface is used for electrical connection;

[0007] A first packaging object, which is arranged in the first through hole, and the electrical connection surface of the first packaging object is flush with the first surface;

[0008] A connection layer, which is used to electrically connect the electrical connection surface of the first packaging object with the first surface.

[0009] According to some embodiments of the utility model, the first packaging object is provided with a heat dissipation surface opposite to the electrical connection surface;

[0010] The packaging structure further includes: a heat dissipation layer, which is arranged in the first through hole and between the heat dissipation surface and the second surface.

[0011] According to some embodiments of the utility model, the heat dissipation layer includes:

[0012] A heat conduction layer, which is arranged in the first through hole, is connected with the heat dissipation surface, and is used for heat conduction of the first packaging object;

[0013] A diffusion layer is disposed within the first through hole. The diffusion layer is disposed between the heat-conducting layer and the second surface, and a side of the diffusion layer away from the heat-conducting layer is flush with the second surface. The diffusion layer is configured to diffuse heat to the encapsulation substrate.

[0014] According to some embodiments of the present invention, the encapsulation structure further includes:

[0015] An electronic component electrically connected to the first surface.

[0016] According to some embodiments of the present invention, the encapsulation structure further includes:

[0017] A second encapsulation object configured to be electrically connected to a side of the connection layer away from the first surface.

[0018] According to some embodiments of the present invention, the encapsulation structure further includes:

[0019] An intermediate layer disposed on the connection layer. The intermediate layer is provided with a second through hole, and one end of the second through hole is electrically connected to the connection layer;

[0020] A third encapsulation object configured to be electrically connected to the other end of the second through hole.

[0021] According to some embodiments of the present invention, the encapsulation structure further includes:

[0022] A spacer layer disposed on the connection layer;

[0023] A light-transmitting layer disposed on the spacer layer. The light-transmitting layer is configured to connect different spacer layers, so as to form a cavity between the light-transmitting layer and the first encapsulation object.

[0024] According to some embodiments of the present invention, the encapsulation structure further includes:

[0025] A microchannel layer disposed on the encapsulation substrate, and the microchannel layer covers the connection layer and the first encapsulation object.

[0026] According to the packaging structure provided by the embodiments of the present utility model, it has at least the following beneficial effects: by embedding the first packaging object in the first through-hole of the packaging substrate, the electrical signal of the first packaging object can be guided from the first surface to the second surface via the via hole 105, so that both the first surface and the second surface of the packaging substrate can be used as the electrical signal transmission paths of the first packaging object. Furthermore, three-dimensional stacking of semiconductor chips can be performed on the packaging substrate, that is, vertical interconnection of semiconductor chips can be achieved, reducing the complex manufacturing process and high manufacturing cost of the TSV technology in the related art.

[0027] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following further describes the present utility model in conjunction with the drawings and embodiments, where:

[0029] Figure 1 is a schematic structural diagram of the packaging structure according to the embodiment of the present utility model;

[0030] Figure 2 is a schematic flowchart of the packaging method according to the embodiment of the present utility model;

[0031] Figure 3 is another schematic structural diagram of the packaging structure according to the embodiment of the present utility model;

[0032] Figure 4 is another schematic structural diagram of the packaging structure according to the embodiment of the present utility model;

[0033] Figure 5 is another schematic structural diagram of the packaging structure according to the embodiment of the present utility model;

[0034] Figure 6 is another schematic structural diagram of the packaging structure according to the embodiment of the present utility model;

[0035] Figure 7 is another schematic structural diagram of the packaging structure according to the embodiment of the present utility model.

[0036] Reference numerals: packaging substrate 101, first through-hole 102, first surface 103, second surface 104, via hole 105, pad 106, fixing member 107, fixing material 108, first packaging object 201, second packaging object 202, third packaging object 203, connection layer 301, intermediate layer 302, second through-hole 303, interconnection layer 304, heat dissipation layer 401, heat conduction layer 402, diffusion layer 403, spacer layer 501, light-transmitting layer 502, cavity 503, microchannel layer 601, microchannel 602, curing layer 603 DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] Embodiments of the present utility model will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present utility model and should not be construed as a limitation of the present utility model.

[0038] In the description of the present utility model, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present utility model.

[0039] In the description of the present utility model, the meaning of several is more than one, and the meaning of multiple is more than two. Understandings such as greater than, less than, exceeding, etc. do not include the present number, and understandings such as above, below, within, etc. include the present number. If there is a description of first and second, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or the sequence relationship of the indicated technical features.

[0040] In the description of the present utility model, unless otherwise clearly defined, words such as setting, installing, connecting, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the above words in the present utility model in combination with the specific content of the technical solution.

[0041] In the description of the present utility model, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0042] Currently, through advanced packaging, the integration degree of electronic components can be improved, and the geometric size and packaging weight of the package can be reduced.

[0043] TSV (Through Silicon Via) is a technology that enables vertical conduction between chips and between wafers. Enabling vertical electrical interconnection through silicon vias is one of the key technologies for 3D advanced packaging. However, the manufacturing process of TSV is relatively complex and requires high-precision drilling and conductive filling processes, which may result in relatively high manufacturing costs.

[0044] Based on this, embodiments of the present application provide a packaging structure and a packaging method to simplify the manufacturing process and reduce the manufacturing cost.

[0045] First, the packaging structure will be described.

[0046] Referring to Figure 1 , the packaging structure provided by the embodiments of the present application includes a packaging substrate 101, a first packaging object 201, and a connection layer 301. The packaging substrate 101 is provided with a first through hole 102, a first surface 103, and a second surface 104 opposite to the first surface 103, and the first surface 103 is used for electrical connection. The first packaging object 201 is disposed in the first through hole 102, and the electrical connection surface of the first packaging object 201 is flush with the first surface 103. The connection layer 301 is used to electrically connect the electrical connection surface of the first packaging object 201 to the first surface 103.

[0047] It can be understood that referring to Figure 1 Part C in, the packaging substrate 101 may refer to a component in semiconductor packaging that is used to support and connect semiconductor chips and connect to external circuits. The packaging substrate 101 can provide mechanical support and protection for the semiconductor chip, and the semiconductor chip can be electrically connected to external components through being disposed on the packaging substrate 101. The packaging substrate 101 can be any one of an organic substrate, a silicon substrate, a composite substrate, a flexible substrate, etc. Specifically, the packaging substrate can be any one of a PCB (Printed Circuit Board), an FPCB (Flexible Printed Circuit Board), a BT (resin substrate), glass, etc. Embodiments of the present application take the packaging substrate 101 as a PCB in the organic substrate as an example for illustration. The packaging substrate 101 is provided with a first surface 103 and a second surface 104, and a first through hole 102 penetrating the first surface 103 and the second surface 104. The first surface 103 may refer to the front surface of the packaging substrate 101, that is, it can refer to the side for electrical connection, or it can refer to the side for mounting electronic components. There can be multiple first through holes 102, and the embodiments of the present application do not make specific limitations on the number of the first through holes 102 opened.

[0048] The first encapsulation object 201 may refer to an object for encapsulation. For example, the first encapsulation object 201 may be a semiconductor chip. The number of the first encapsulation objects 201 may be multiple, and the types or functions of the multiple first encapsulation objects 201 may be the same or different. The embodiments of the present application do not make specific limitations thereto. Place the multiple first encapsulation objects 201 in different first through holes 102 respectively, that is, one first through hole 102 is used to place one first encapsulation object 201. Set the electrical connection surface of the first encapsulation object 201 flush with the first surface 103 of the encapsulation substrate 101, so as to facilitate subsequent electrical connection between the first encapsulation object 201 and the first surface 103 of the encapsulation substrate 101 and reduce the connection path. It can be understood that the first encapsulation object 201 may be electrically connected to the first surface 103 of the encapsulation substrate 101 in a flip-chip bonding manner. At this time, the electrical connection surface of the first encapsulation object 201 may be understood as the front surface of the first encapsulation object 201.

[0049] The connection layer 301 may refer to a component for re-wiring the first encapsulation object 201. The connection layer 301 may electrically connect the I / O (Input / Output) on the electrical connection surface of the first encapsulation object 201 to the encapsulation substrate 101, so as to improve the I / O density of the encapsulation structure and achieve a smaller encapsulation size, etc. Specifically, the connection layer 301 may be formed based on RDL (Redistribution Layer). The connection layer 301 may include lines and pads for connecting the I / O of the first encapsulation object 201, and the pads of the connection layer 301 are used to be electrically connected to the pads 106 of the encapsulation substrate 101.

[0050] It can be understood that via holes 105 may be provided on the encapsulation substrate 101. The via holes 105 may electrically connect different layers of the encapsulation substrate 101, that is, the via holes 105 may serve as signal transmission paths to connect different circuit layers of the encapsulation substrate 101. Based on this, the encapsulation structure provided by the embodiments of the present application can realize guiding the electrical signals of the first encapsulation object 201 from the first surface 103 to the second surface 104 via the via holes 105, so that both the first surface 103 and the second surface 104 of the encapsulation substrate 101 can serve as electrical signal transmission paths of the first encapsulation object 201. Furthermore, three-dimensional stacking of semiconductor chips can be performed on the encapsulation substrate 101, that is, vertical interconnection of semiconductor chips is realized, reducing the complex manufacturing process and high manufacturing cost of the TSV technology in the related art.

[0051] In addition, the via holes 105 are basic structures of the encapsulation substrate 101, and the performance of the via holes 105 can be detected by visual inspection, resistance testing, ultrasonic scanning, etc., thereby improving the yield rate of the encapsulation structure.

[0052] Refer to Figure 2, in some embodiments, Figure 1 The encapsulation structure shown can be obtained by the encapsulation method shown in the following steps S201 to S205.

[0053] Step S201: Set the encapsulation substrate and form a first through-hole on the encapsulation substrate for penetrating the first surface and the second surface.

[0054] Step S202: Set the second surface in the first direction, adhere a fixing member on the first surface of the encapsulation substrate, place the first encapsulation object in the first through-hole, and inject a fixing material into the first through-hole so that the electrical connection surface of the first encapsulation object is flush with the first surface.

[0055] Step S203: Flip the encapsulation substrate so that the first surface faces the first direction.

[0056] Step S204: Remove the fixing member.

[0057] Step S205: Perform a re-wiring operation on the first surface to form a connection layer on the first surface.

[0058] In step S201 of some embodiments, referring to Figure 1 part A in, set the encapsulation substrate 101. The encapsulation substrate 101 has a first surface 103 and a second surface 104 which are oppositely arranged. Form a first through-hole 102 on the encapsulation substrate 101 that penetrates the first surface 103 and the second surface 104. The size of the first through-hole 102 can be adaptively set according to the size of the first encapsulation object 201. It can be understood that according to the characteristics of the encapsulation substrate 101, via holes 105 and pads 106 can also be provided on the encapsulation substrate 101.

[0059] In step S202 of some embodiments, referring to Figure 1 part B in, set the second surface 104 of the encapsulation substrate 101 in the first direction. The first direction can refer to the upper direction as shown in Figure 1 , then the first surface 103 faces downward. Adhere a fixing member 107 on the first surface 103 of the encapsulation substrate 101. The fixing member 107 can be made of a material with temporary adhesiveness. For example, the fixing member 107 can be a CARRER TAPE (carrier tape), etc. Place the first encapsulation object 201 in the first through-hole 102. The electrical connection surface of the first encapsulation object 201 adheres to the fixing member 107. At this time, the electrical connection surface of the first encapsulation object 201 is flush with the first surface 103 of the encapsulation substrate 101. It can be understood that in order to ensure the flush effect and reduce the loosening of the first encapsulation object 201, a fixing material 108 can also be injected into the first through-hole 102 from the second surface 104, such as injecting fixing glue. The fixing glue can be used to fill the gap between the inner wall of the first through-hole 102 and the first encapsulation object 201.

[0060] It can be understood that by flush - setting the electrical connection surface of the first encapsulation object 201 with the first surface 103 of the encapsulation substrate 101, the size of the encapsulation structure can be reduced, facilitating subsequent integrated design. In addition, the thickness of the first encapsulation object 201 can be ground to match the thickness of the encapsulation substrate 101, thereby achieving the purpose of reducing the overall thickness of the encapsulation structure.

[0061] In steps S203 to S204 of some embodiments, referring to Figure 1 part C in, the encapsulation substrate 101 is flipped, that is, the first surface 103 is set in the first direction and the second surface 104 is set in the second direction. After flipping, the fixing member 107 is removed.

[0062] In step S205 of some embodiments, referring to Figure 1 part C in, an RDL operation is performed on the first surface 103 to form a connection layer 301 on the first surface 103. The connection layer 301 is used to electrically connect the pads 106 on the first surface 103 with the first encapsulation object 201. It can be understood that based on the characteristic that the encapsulation substrate 101 has vias 105, the following electrical signal transmission path can be realized: the first encapsulation object 201 I / O - connection layer 301 - pad 106 on the first surface 103 of the encapsulation substrate 101 - via 105 of the encapsulation substrate 101 - pad 106 on the second surface 104 of the encapsulation substrate 101, that is, the electrical signal can be guided from the first surface 103 of the encapsulation substrate 101 to the second surface 104 of the encapsulation substrate 101, thus facilitating subsequent three - dimensional stacking operations.

[0063] The advantages of steps S201 to S205 are that by encapsulating the first encapsulation object 201 in the encapsulation substrate 101, the same technical effect as that of using TSV is achieved by using the vias 105 of the encapsulation substrate 101, reducing the complex process and high cost caused by using TSV technology in related technologies.

[0064] It can be understood that in some embodiments, referring to Figure 1 part D in, the encapsulation substrate 101 can be cut and tested to ensure the yield and performance of the encapsulation substrate 101.

[0065] The following describes the three - dimensional stacking operation.

[0066] Referring to Figure 3 , in some embodiments, the encapsulation structure includes a second encapsulation object 202, and the second encapsulation object 202 is used to electrically connect to the side of the connection layer 301 away from the first surface 103. It can be understood that referring to Figure 3In part B thereof, the second encapsulation object 202 may refer to a semiconductor chip. The second encapsulation object 202 can be electrically connected to a surface of the connection layer 301 away from the first surface 103 through flip-chip bonding, that is, electrically connected to the upper surface of the connection layer 301. Through this three-dimensional stacking method, the connection distance between the first encapsulation object 201 and the second encapsulation object 202 can be reduced, thereby reducing signal loss and energy consumption.

[0067] It can be understood that with reference to Figure 3 , in some embodiments, when the number of pads of the second encapsulation object 202 is small, and / or the number of the second encapsulation objects 202 is small, and / or the surface area of the second encapsulation object 202 is smaller than the surface area of the first encapsulation object 201, connection layers 301 can be provided on both the left and right sides of the first encapsulation object 201. At this time, the second encapsulation object 202 can be electrically connected to the connection layers 301 on the left and right sides respectively.

[0068] With reference to Figure 4 , in some embodiments, when the number of pads of the second encapsulation object 202 is large, and / or the number of the second encapsulation objects 202 is large, the second encapsulation object 202 can be electrically connected to the pads 106 and the connection layer 301 on the encapsulation substrate 101 (such as Figure 4 the F1 case shown in part B thereof). It can be understood that the first surface 103 of the encapsulation substrate 101 can be preset with a connection path between different pads 106, so a signal loop can also be formed through the electrical connection method shown in F1. Alternatively, the second encapsulation object 202 can be electrically connected to the pads and the connection layer 301 of the first encapsulation object 201 (such as Figure 4 the F2 case shown in part B thereof). Thus, it can be seen that Figure 4 the connection method of the second encapsulation object 202 shown can integrate the pads 106 of the encapsulation substrate 101 for bonding, thereby improving the applicable scenarios of the encapsulation structure.

[0069] It can be understood that in addition to Figure 3 and Figure 4 the structures exemplified, the second encapsulation object 202 can also be three-dimensionally stacked with the first encapsulation object 201 in other ways, and the embodiments of the present application do not make specific limitations thereto. For example, the second encapsulation object 202 can be only electrically connected to the pads on the encapsulation substrate 101, and a signal loop between the second encapsulation object 202 and the first encapsulation object 201 can be formed through the connection path between different pads 106 on the encapsulation substrate 101.

[0070] In the embodiment of the present application, by electrically connecting the connection layer 301 to the second packaged object 202, not only the three-dimensional stacking of the first packaged object 201 and the second packaged object 202 is realized, but also the connection path between the first packaged object 201 and the second packaged object 202 is shortened, thereby reducing signal loss and lowering heat generation and energy consumption.

[0071] It can be understood that, in combination with Figure 3 (or Figure 4 ), as shown in parts A to C of Figure 3 , after step S205, a flip-chip bonding operation can be performed on the second packaged object 202, and then a dicing test is carried out. The dicing test is as shown in part C of Figure 4 or as shown in part C of

[0072] In some embodiments, in order to adapt to richer three-dimensional stacking scenarios, the F3 method shown in part B of Figure 4 can also be used for three-dimensional stacking. Specifically, the packaging structure may further include an interposer 302 and a third packaged object 203. The interposer 302 is disposed on the connection layer 301, and the interposer 302 is provided with a second through hole 303, and one end of the second through hole 303 is electrically connected to the connection layer 301. The third packaged object 203 is used to be electrically connected to the other end of the second through hole 303. It can be understood that the interposer 302 can be used to connect different semiconductor chips or circuit layers, thereby achieving higher integration and more complex system-level packaging. The interposer 302 can be made of a silicon-based or organic-based material, and the embodiment of the present application does not make specific limitations thereto. One end of the second through hole 303 of the interposer 302 is connected to the pad 106 of the packaging substrate 101 or the connection layer 301, and the other end of the second through hole 303 is connected to the third packaged object 203, thereby enriching the connection path between the third packaged object 203 and the second packaged object 202. It can be understood that the third packaged object 203 can be electrically connected to the second through hole 303 by means of flip-chip bonding.

[0073] It can be understood that, in some embodiments, in order to enable the packaging structure to achieve corresponding functions, the packaging structure body may further be connected to electronic components. The electronic components may refer to passive components, and the passive components may include resistors, capacitors, transformers, filters, etc. The electronic components can be electrically connected to the first surface of the packaging substrate 101.

[0074] It can be understood that thermal management can be performed on the packaging structure described in any of the above embodiments. The thermal management will be described below.

[0075] Referring to Figure 5, in some embodiments, the first encapsulation object 201 is provided with a heat dissipation surface opposite to the electrical connection surface. The encapsulation structure further includes a heat dissipation layer 401, which is disposed in the first through hole 102 and between the heat dissipation surface and the second surface 104. Specifically, the heat dissipation surface may refer to the surface opposite to the electrical connection surface of the first encapsulation object 201, that is, the surface of the first encapsulation object 201 close to the second surface 104 of the encapsulation substrate 101. For example, in Figure 5 part D, the heat dissipation surface may refer to the lower surface of the first encapsulation object 201. The heat dissipation layer 401 may refer to a component disposed between the second surface 104 of the encapsulation substrate 101 and the heat dissipation surface of the first encapsulation object 201, and the heat dissipation layer 401 is used for heat dissipation operation. It can be understood that the surface of the heat dissipation layer 401 close to the second surface 104 may be flush with the second surface 104 or not flush with the second surface 104, and the embodiments of the present application do not make specific limitations thereto.

[0076] It can be understood that when one surface of the heat dissipation layer 401 is flush with the heat dissipation surface and the other surface of the heat dissipation layer 401 is in contact with the heat dissipation surface, the heat dissipation layer 401 can conduct the heat of the first encapsulation object 201 to the encapsulation substrate 101, thereby expanding the heat dissipation area and improving the heat dissipation efficiency.

[0077] In some embodiments, the heat dissipation layer 401 may include a heat conduction layer 402 and a diffusion layer 403, and both the heat conduction layer 402 and the heat dissipation layer 401 are disposed in the first through hole 102. The heat conduction layer 402 is connected to the heat dissipation surface, and the heat conduction layer 402 is used for heat conduction of the first encapsulation object 201. The diffusion layer 403 is disposed between the heat conduction layer 402 and the second surface 104, and the surface of the diffusion layer 403 away from the heat conduction layer 402 is flush with the second surface 104 of the encapsulation substrate 101. The diffusion layer 403 is used for diffusing heat to the encapsulation substrate 101. It can be understood that the heat dissipation layer 401 can be made of heat dissipation glue, and the diffusion layer 403 can be made of a heat sink.

[0078] Correspondingly, referring to Figure 5 shown in parts A to E of

[0079] injecting a heat conductive material between the first encapsulation object 201 and the second surface 104 to form the heat conduction layer 402;

[0080] injecting a diffusion material between the heat conduction layer 402 and the second surface 104 to form the diffusion layer 403.

[0081] It can be understood that the heat conductive material and the diffusion material can be adaptively set according to actual needs, and the embodiments of the present application do not make specific limitations thereto.

[0082] It can be understood that when the embodiments of the present application are applied to different scenarios, the encapsulation structure can also be adaptively set.

[0083] First, the optical scenario is described.

[0084] Referring to Figure 6 , in some embodiments, the encapsulation structure may further include a spacer layer 501 and a light-transmitting layer 502. The spacer layer 501 is disposed on the connection layer 301. The light-transmitting layer 502 is disposed on the spacer layer 501. The light-transmitting layer 502 is used to connect different spacer layers 501 so that a cavity 503 is formed between the light-transmitting layer 502 and the first encapsulation object 201.

[0085] It can be understood that when the first semiconductor object is an optical chip, the spacer layer 501 and the light-transmitting layer 502 can be sequentially disposed on the side of the connection layer 301 away from the first encapsulation object 201. As Figure 6 shown, the spacer layer 501 and the light-transmitting layer 502 can be sequentially disposed on the upper surface of the connection layer 301. The light-transmitting layer 502 can refer to a component with light-transmitting characteristics, and the spacer layer 501 can refer to a component for spacing the light-transmitting layer 502 and the connection layer 301. The length of the light-transmitting layer 502 can be greater than the length of the spacer layer 501. Therefore, when the light-transmitting layer 502 connects different spacer layers 501, for example, when connecting the spacer layers 501 disposed on the left and right sides of the first encapsulation object 201, the light-transmitting layer 502 can form a cavity 503 with the first encapsulation object 201. The cavity 503 can refer to an enclosed space surrounded by the side of the light-transmitting layer 502 close to the first encapsulation object 201 (such as the lower surface of the light-transmitting layer 502), the side of the spacer layer 501 close to the first encapsulation object 201 (such as the right surface or the left surface of the spacer layer 501), the side of the connection layer 301 close to the first encapsulation object 201 (such as the right surface or the left surface of the connection layer 301), and the side of the first encapsulation object 201 close to the light-transmitting layer 502 (such as the upper surface of the first encapsulation object 201). The cavity 503 can reduce the intrusion of other materials, thereby reducing the loss when light irradiates the first encapsulation object 201 from the light-transmitting layer 502.

[0086] It can be understood that in order to increase the light transmittance of the cavity 503, the side of the spacer layer 501 close to the first encapsulation object 201 can be flush with the side of the connection layer 301 close to the first encapsulation object 201. As Figure 6 shown, the right surface of the spacer layer 501 can be flush with the right surface of the connection layer 301 in the vertical direction, and the left surface of the spacer layer 501 can be flush with the left surface of the connection layer 301 in the vertical direction.

[0087] Correspondingly, as shown in parts A to C of Figure 6 , after step S205, the encapsulation method may further include the steps of:

[0088] A spacer layer 501 is formed on the connection layer 301 through a yellow light process;

[0089] A light-transmitting layer 502 for connecting different spacer layers 501 is provided on the spacer layer 501.

[0090] It can be understood that the light-transmitting layer 502 can be glass or other light-transmitting materials. The yellow light process can refer to operations such as exposure and development using a photoresist material.

[0091] Secondly, the biochemical scenario is described.

[0092] Referring to Figure 7 , in some embodiments, the encapsulation structure may further include a microchannel layer 601. The microchannel layer 601 is disposed on the encapsulation substrate 101, and the microchannel layer 601 covers the connection layer 301 and the first encapsulated object 201. It can be understood that the microchannel layer 601 can refer to a component having a microchannel 602 structure. The microchannel 602 can refer to a fluid channel designed on a microscale. The microchannel layer 601 is disposed above the encapsulation substrate 101, and the microchannel layer 601 simultaneously covers the connection layer 301 and the surface of the first encapsulated object 201 close to the connection layer 301, even if the microchannel layer 601 covers the electrical signal transmission path of the first encapsulated object 201. Thus, when a fluid is injected into the microchannel 602, the first encapsulated object 201 and / or the system corresponding to the first encapsulated object 201 can perform operations such as biochemical analysis, flow control, and substance analysis on the fluid.

[0093] Correspondingly, referring to Figure 7 from part A to part C in, after step S205, the encapsulation method may further include the step of forming a microchannel layer 601 on the encapsulation substrate 101 through a yellow light process. It can be understood that the microchannel layer 601 may include a microchannel 602 and a curing layer 603. The microchannel 602 can be the part of the photoresist material that is dissolved in the developer after development, so a fluid channel can be formed in this part. The curing layer 603 can refer to the part of the photoresist material that does not react with the developer.

[0094] It can be understood that since in the above encapsulation structure, the electrical connection surface of the first encapsulated object 201 is flush with the first surface 103. Therefore, the microchannel 602 can be horizontally arranged, which is beneficial to the flow of the fluid.

[0095] It can be understood that in the above embodiments, according to actual needs, BUMPs (bumps) can be fabricated on the second surface 104 of the encapsulated object through the BUMPING process first, and then cutting and testing can be performed. The bumps can establish electrical connections with external circuits.

[0096] In summary, the encapsulation structure and encapsulation method provided by the embodiments of the present application can achieve the following effects:

[0097] 1. Embedding the first encapsulation object into the encapsulation substrate in a flip-chip bonding manner can reduce the precision requirements of the encapsulation process.

[0098] 2. Before flipping the encapsulation substrate, injecting a fixing material into the first through-hole from the second surface ensures that the gap between the first encapsulation object and the inner wall of the first through-hole is filled. Thus, after flipping the encapsulation substrate, the electrical connection surface of the first encapsulation object can be guaranteed to be flush with the encapsulation substrate, which is beneficial to the subsequent yellow light process.

[0099] 3. The mask technology and equipment can be used in the process to make the process more stable.

[0100] 4. Compared with the encapsulation method of setting semiconductor chips on the encapsulation substrate, the embedding method of the embodiment of the present application can reduce the overall thickness of the encapsulation structure and improve the heat dissipation performance of the encapsulation structure.

[0101] 5. Utilizing the through-hole characteristics of the encapsulation substrate itself avoids the use of TSV technology for three-dimensional stacking, thereby reducing the process difficulty and cost and improving the yield of the encapsulation structure.

[0102] 6. The embodiment of the present application can be applied to different types and shapes of encapsulation substrates and encapsulation objects.

[0103] 7. Stacking the encapsulation objects three-dimensionally in a flip-chip bonding manner enables the shortest connection distance to be formed between the encapsulation objects.

[0104] 8. The heat dissipation layer guides the heat to the second surface of the encapsulation substrate, thereby expanding the heat dissipation area and improving the heat dissipation effect on the first encapsulation object.

[0105] The embodiments of the present utility model have been described in detail above with reference to the drawings. However, the present utility model is not limited to the above embodiments. Within the knowledge scope of those of ordinary skill in the art to which it pertains, various changes can be made without departing from the gist of the present utility model. In addition, the embodiments of the present utility model and the features in the embodiments can be combined with each other without conflict.

Claims

1. An encapsulation structure, characterized in that, The encapsulation structure includes: An encapsulation substrate, the encapsulation substrate is provided with a first through hole, a first surface and a second surface opposite to the first surface, and the first surface is used for electrical connection; A first encapsulation object, the first encapsulation object is arranged in the first through hole, and the electrical connection surface of the first encapsulation object is flush with the first surface; A connection layer, the connection layer is used to electrically connect the electrical connection surface of the first encapsulation object and the first surface.

2. The encapsulation structure according to claim 1, wherein The first encapsulation object is provided with a heat dissipation surface opposite to the electrical connection surface; The encapsulation structure further includes: a heat dissipation layer, the heat dissipation layer is arranged in the first through hole and between the heat dissipation surface and the second surface.

3. The encapsulation structure according to claim 2, wherein The heat dissipation layer includes: A heat conduction layer, the heat conduction layer is arranged in the first through hole, the heat conduction layer is connected to the heat dissipation surface, and the heat conduction layer is used for heat conduction of the first encapsulation object; A diffusion layer, the diffusion layer is arranged in the first through hole, the diffusion layer is arranged between the heat conduction layer and the second surface, and one side of the diffusion layer away from the heat conduction layer is flush with the second surface, and the diffusion layer is used for diffusing heat to the encapsulation substrate.

4. The encapsulation structure according to claim 1, wherein The encapsulation structure further includes: An electronic component, the electronic component is electrically connected to the first surface.

5. The encapsulation structure according to any one of claims 1 to 4, characterized in that, The encapsulation structure further includes: A second encapsulation object, the second encapsulation object is used for electrically connecting to a side of the connection layer away from the first surface.

6. The encapsulation structure according to any one of claims 1 to 4, characterized in that, The encapsulation structure further includes: An intermediate layer, the intermediate layer is arranged on the connection layer, the intermediate layer is provided with a second through hole, and one end of the second through hole is electrically connected to the connection layer; 7. The encapsulation structure according to any one of claims 1 to 4, characterized in that, A third encapsulation object, the third encapsulation object is used for electrically connecting to the other end of the second through hole. The encapsulation structure further includes: A spacer layer, the spacer layer is arranged on the connection layer; 8. The encapsulation structure according to any one of claims 1 to 4, characterized in that, A light-transmitting layer, the light-transmitting layer is arranged on the spacer layer, and the light-transmitting layer is used for connecting different spacer layers to form a cavity between the light-transmitting layer and the first encapsulation object. The encapsulation structure further includes: A microchannel layer, the microchannel layer is arranged on the encapsulation substrate, and the microchannel layer covers the connection layer and the first encapsulation object.

9. The encapsulation structure according to any one of claims 1 to 4, wherein the encapsulation substrate is any one of a printed circuit board, a flexible printed circuit board, a resin substrate, and glass.

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