Electronic package
By designing the embedded ring frame on the periphery of the substrate, the warping problem of the crystal-covered ball grid array semiconductor package is solved, and the cost is reduced without increasing the substrate size and the need for light and short-term terminal products is achieved.
Patent Information
- Application Number
- CN202422237944.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-04
- Filing Date
- 2024-09-12
- Publication Date
- 2025-08-01
- Estimated Expiration
- 2034-09-12
AI Technical Summary
After the chip integration and the increase in I/O number of existing crystal-covered ball grid array semiconductor packages, warpage control is difficult to effectively solve, resulting in an increase in the volume of the package and cannot meet the needs of thin and short terminal products.
An electronic packaging structure with an annular frame embedded on the periphery of the substrate is adopted to resist thermal stress through the frame, avoid warping of the packaging layer, and lay other electronic components without increasing the size of the substrate, reducing production costs.
Effectively prevent the packaging layer from warping during thermal cycling, reduce production costs, and do not increase the substrate size to meet the needs of thin and short terminal products.
Smart Images
Figure CN223181128U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor device, particularly an anti-warpage electronic package. Background Art
[0002] A flip-chip ball grid array (FCBGA) semiconductor package is a structure in which the active surface of at least one chip is electrically connected to a surface of a substrate through a plurality of solder bumps, and a plurality of solder balls serving as input / output (I / O) terminals are implanted on the other surface of the substrate. This packaging structure can significantly reduce the volume and eliminate the design of existing wires at the same time, thereby reducing impedance and improving electrical performance to avoid signal decay during transmission. Therefore, it has indeed become the mainstream packaging technology for next-generation chips and electronic components.
[0003] With the development of semiconductor technology, the functions integrated in chips and the number of I / Os have increased. To ensure the stability of the back-end assembly, a sufficiently large I / O pitch is required. Therefore, the chip size / package size ratio has also increased. This is because the difference in the coefficient of thermal expansion (CTE) between the chip and the substrate is too large, and the molding compound (M / C) is formed on most of the substrate surface, resulting in poor control of the warpage of the package.
[0004] In addition, in response to the rapid development of flip-chip chip scale packages (FCCSPs), chips with fine line pitches need to use a coreless embedded trace substrate (ETS) to carry out signals. Therefore, the common method to control warpage is to adjust the thickness of the M / C or select different types of packaging compounds for optimization. However, as the package becomes larger and larger, the effect of using the method of increasing the thickness of the packaging compound or selecting different types of packaging compounds becomes worse and worse. In particular, the former method will increase the height of the package and thus the overall volume, failing to meet the requirements of thin, light, short, and small for end products.
[0005] Please refer to Figure 1 , although the industry has subsequently developed a structure for controlling warpage by combining a ring-shaped metal frame 12 on the substrate 10 (as shown below Figure 1 ), generally, the larger the size and the thicker the thickness of the metal frame 12, the more obvious the improvement in warpage. However, too large a metal frame 12 will reduce the placement of other electronic components, so the substrate size must be increased, resulting in increased costs. In addition, it will also increase the overall volume and fail to meet the requirements of thin, light, short, and small for end products. Therefore, how to solve the above problems has indeed become a difficult problem that the industry urgently needs to overcome at present. Summary of the Invention
[0006] In view of the above-mentioned deficiencies of the prior art, the present application provides an electronic package, comprising: a substrate; an electronic component disposed on the substrate and electrically connected to the substrate; a packaging layer formed on the substrate to cover the electronic component; and a frame embedded in the packaging layer and located around the substrate without contacting the substrate.
[0007] The present application further provides a method for manufacturing an electronic package, comprising: providing a support member having an opening; disposing a substrate in the opening of the support member; disposing an electronic component on the substrate; disposing a frame in the opening of the support member, wherein the frame is located around the substrate without contacting the substrate; and forming a packaging layer on the support member to cover the substrate, the electronic component and the frame.
[0008] In the foregoing electronic package and its manufacturing method, a carrying structure is further provided to dispose the support member on the carrying structure and remove the carrying structure after forming the packaging layer.
[0009] In the foregoing electronic package and its manufacturing method, the frame is annular and surrounds the periphery of the substrate.
[0010] In the foregoing electronic package and its manufacturing method, the frame is partially exposed from the packaging layer. For example, the packaging layer has opposite first and second surfaces, and the bottom surface of the frame is flush with the second surface of the packaging layer; or the top surface of the frame is flush with the first surface of the packaging layer; or the frame is exposed on the side surface adjacent to the first surface and the second surface; or the height of the frame is greater than the height of the electronic component, so that the frame is exposed from the first surface of the packaging layer, and the electronic component is embedded in the packaging layer.
[0011] In the foregoing electronic package and its manufacturing method, the electronic component is partially exposed from the packaging layer.
[0012] In the foregoing electronic package and its manufacturing method, a shielding layer is further formed on the packaging layer. In addition, a plurality of conductive elements can be further formed on the frame to be grounded and connected to an external device through the plurality of conductive elements.
[0013] In the foregoing electronic package and its manufacturing method, a plurality of conductive elements are further provided on the substrate, and the plurality of conductive elements are exposed from the packaging layer.
[0014] In the foregoing electronic package and its manufacturing method, a plurality of conductive elements are further provided on the frame, and the plurality of conductive elements are exposed from the packaging layer.
[0015] As can be seen from the above, in the electronic package and its manufacturing method of the present application, mainly the frame resists thermal stress to prevent the package layer from warping during thermal cycling. And by disposing the frame outside the substrate, it is beneficial to arrange other electronic components around the electronic component without increasing the size of the substrate, thereby reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 FIG. 6 is a schematic cross-sectional view of a conventional semiconductor package.
[0017] Figures 2A to 2D FIG. 10 is a schematic cross-sectional view of the manufacturing method of the first embodiment of the electronic package of the present application.
[0018] Figure 2D-1 FIG. 14 is Figure 2D a partial bottom view of FIG.
[0019] Figure 3 FIG. 20 is a schematic cross-sectional view of the second embodiment of the electronic package of the present application.
[0020] Figure 4 FIG. 24 is a schematic cross-sectional view of the third embodiment of the electronic package of the present application.
[0021] Figure 4-1 FIG. 28 is Figure 4 a schematic cross-sectional view of other embodiments of FIG.
[0022] Figure 5 FIG. 34 is a schematic cross-sectional view of the fourth embodiment of the electronic package of the present application.
[0023] Figure 5-1 And Figure 5-2 FIG. 40 is Figure 5 a schematic cross-sectional view of other embodiments of FIG.
[0024] Figure 6A And Figure 6B FIG. 48 is a schematic cross-sectional and bottom view of the fifth embodiment of the electronic package of the present application.
[0025] MAIN COMPONENT SYMBOL DESCRIPTION
[0026] 10 Substrate
[0027] 12 Metal Frame
[0028] 2, 3, 4, 5, 6 Electronic Package
[0029] 20 Substrate
[0030] 20a First Side
[0031] 20b Second Side
[0032] 20c Side
[0033] 21 Electronic component
[0034] 21a Active surface
[0035] 21b Non-active surface
[0036] 210 Conductive bump
[0037] 211 Underfill
[0038] 22 Electronic accessory
[0039] 23, 33, 43, 53, 63 Frame
[0040] 24 Encapsulation layer
[0041] 24a First surface
[0042] 24b Second surface
[0043] 24c Side surface
[0044] 25, 55, 65 Conductive element
[0045] 56 Shielding layer
[0046] 30 Carrier structure
[0047] 30a First side
[0048] 30b Second side
[0049] 31 Support
[0050] 310 Opening Detailed implementation manners
[0051] The following describes the implementation manners of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.
[0052] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limited conditions that the present application can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope that the technical content disclosed in the present application can cover. At the same time, the terms such as "upper", "lower", "one", "first", and "second" used in this specification are only for the convenience of clear description and are not used to limit the scope that the present application can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope that the present application can be implemented.
[0053] Figures 2A to 2D This is a schematic cross-sectional view of the manufacturing method of the electronic package 2 of the present application.
[0054] As Figure 2A shown, a carrier structure 30 having a relative first side 30a and a second side 30b is provided. A support member 31 having a plurality of openings 310 is disposed on the first side 30a of the carrier structure 30, so as to dispose a substrate 20 in the openings 310 of the support member 31. In this embodiment, two substrates 20 are shown respectively disposed in adjacent openings 310, but the present application is not limited thereto.
[0055] The carrier structure 30 may be a temporary carrier plate, which may include, for example: a carrier plate composed of an organic polymer sheet or a copper foil substrate, but the present application is not limited to the above.
[0056] The substrate 20 may be, for example, a package substrate having a core layer and a circuit portion or a circuit structure without a core layer. In this embodiment, the substrate 20 includes at least one dielectric layer and a circuit layer bonded to the dielectric layer. The substrate 20 has opposite first side 20a and second side 20b, wherein the second side 20b of the substrate 20 is bonded to the first side 30a of the carrier structure 30.
[0057] It should be understood that the substrate 20 may also be other carrier units for carrying chips, such as a leadframe, a wafer, a silicon interposer, or other plates having metal routing, etc., and is not limited to the above.
[0058] As Figure 2B shown, at least one electronic component 21 is disposed on the first side 20a of the substrate 20 through a plurality of conductive bumps 210, and a coating layer such as an underfill 211 is filled and formed between the first side 20a of the substrate 20 and the electronic component 21 to coat the conductive bumps 210. In addition, at least one electronic accessory 22 may be disposed around the electronic component 21.
[0059] The electronic component 21 described above is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which has opposite functional surfaces 21a and non-functional surfaces 21b, and the functional surface 21a has a plurality of electrode pads (not shown) so that these electrode pads are bonded and electrically connected to the circuit layer of the substrate 20 in a flip-chip manner through a plurality of conductive bumps 210 such as solder materials. In another embodiment of the present invention, the electronic accessory 22 is a passive component, and it can also be disposed on the first side 20a of the substrate 20 through conductive bumps in a space where no electronic component 21 is arranged.
[0060] In other embodiments, the electronic component 21 can also be electrically connected to the circuit layer of the substrate 20 by a plurality of bonding wires in a wire bonding manner (not shown in the figure); or, the electronic component 21 can be directly electrically connected to the circuit layer of the substrate 20. It should be understood that there are many ways to electrically connect the electronic component 21 and the electronic accessory 22 to the substrate 20, and the required types and quantities of the electronic component 21 and the electronic accessory 22 can be disposed on the substrate 20, which is not limited to the above.
[0061] Furthermore, a frame 23 is disposed in the opening 310 of the support 31, where the frame 23 is located at the periphery of the substrate 20 and does not contact the substrate 20.
[0062] The frame 23 described above is a metal frame such as copper material or a semiconductor frame such as silicon material or glass material. In this embodiment, the frame 23 is annular and surrounds the substrate 20.
[0063] As Figure 2C shown, a packaging layer 24 is formed on the first side 30a of the carrier structure 30 so that the packaging layer 24 covers the support 31, the substrate 20, the electronic component 21, the electronic accessory 22, and the frame 23, and then the carrier structure 30 is removed except for the second side 20b of the substrate 20 that is exposed.
[0064] In addition, after the carrier structure 30 is removed, a plurality of conductive components 25 such as metal columns such as copper pillars, metal bumps coated with insulating blocks, solder balls, solder balls with core copper balls (Cu core balls), or other conductive structures can be disposed on the second side 20b of the substrate 20.
[0065] The packaging layer 24 has opposite first surfaces 24a and second surfaces 24b. In this embodiment, the first surface 24a of the packaging layer 24 is higher than the non-functional surface 21b of the electronic component 21 to completely cover the electronic component 21, and the second surface 24b of the packaging layer 24 is flush with the second side 20b of the substrate 20.
[0066] In this embodiment, the encapsulation layer 24 is an insulating material, such as polyimide (PI for short), dry film, an encapsulation colloid such as epoxy resin, or other encapsulation materials (molding compound). For example, the process for forming the encapsulation layer 24 can be selected as lamination or compression molding to be formed on the carrier structure 30.
[0067] As Figure 2D shown, a cutting operation (a single-cut process) is performed on each substrate 20, so that the encapsulation layer 24 defines a side surface 24c adjacent to the first surface 24a and the second surface 24b, to obtain the electronic package 2 of the present application, wherein the bottom surface of the frame 23 is flush with the second surface of the encapsulation layer 24.
[0068] In this embodiment, the cutting path is set to not cut the frame 23, and the frame 23 is exposed on the second surface 24b of the encapsulation layer 24 without exposing its side surface 24c.
[0069] In addition, in this embodiment, as Figure 2D-1 shown in the bottom view schematic diagram, the frame 23 can be formed in a ring shape and continuously surround the periphery of the side surface 20c of the substrate 20 without contacting the substrate 20. It should be understood that in other embodiments, the frame 23 can also be distributed in a discontinuous manner (not shown in the figure) around the periphery of the side surface 20c of the electronic component 21.
[0070] Based on the above, the manufacturing method of the present application mainly reduces warping during thermal cycling through the design of the frame 23 and can conduct the heat of the electronic component outward. Furthermore, since the frame 23 does not contact the substrate 20, it is beneficial to arrange other electronic components or electronic accessories around the electronic component 21 without increasing the size of the substrate 20, thus reducing the manufacturing cost. In addition, the foregoing manufacturing method does not require the development of new processes and materials or the purchase of machines, and the existing materials, old processes, and machines can be used to solve the existing technical problems in the industry, so there will be no large amount of additional cost expenditure.
[0071] Please refer to Figure 3
[0072] Please refer to Figure 4 , showing a cross-sectional schematic view of the third embodiment of the electronic package 4 of the present application. In the electronic package 4, the non-functional surface 21b of the electronic component 21 is exposed on the first surface 24a of the encapsulation layer 24. Specifically, part of the material of the encapsulation layer 24 (even part of the material of the non-functional surface 21b of the electronic component 21) can be removed through a planarization process (such as by grinding), so that the first surface 24a of the encapsulation layer 24 is flush with the non-functional surface 21b of the electronic component 21 and the top surface of the frame 24, so that the non-functional surface 21b of the electronic component 21 is exposed on the first surface 24a of the encapsulation layer 24. Even the frame 43 can be made to expose the first surface 24a, the second surface 24b, and the side surface 24c of the encapsulation layer 24 at the same time, thereby improving the heat dissipation efficiency of the electronic component 21.
[0073] In another embodiment, such as Figure 4-1 shown, the height of the frame 43 is greater than the height of the electronic component 21, so that the frame 43 exposes the first surface 24a of the encapsulation layer 24, but the electronic component 21 is still embedded in the encapsulation layer 24 and does not expose the first surface 24a of the encapsulation layer 24.
[0074] Please refer to Figure 5 , showing a cross-sectional schematic view of the fourth embodiment of the electronic package 5 of the present application. The electronic package 5 mainly exposes the side surface 24c of the encapsulation layer 24 after the singulation process, and forms a shielding layer 56 on the side surface 24c and the first surface 24a of the encapsulation layer 24, so that the shielding layer 56 contacts the frame 53 on the side surface 24c of the encapsulation layer 24. In addition, in other embodiments, the shielding layer 56 can also contact the frame 53 on the first surface 24a or the second surface 24b of the encapsulation layer 24, or does not contact the frame 53. It should be understood that the shielding layer 56 can contact or not contact the electronic component 21 as required, and can also contact or not contact the frame 53 as required, without special restrictions. In this embodiment, mainly through the design of the shielding layer 56, the electronic component 21 is protected from electromagnetic interference (Electromagnetic Interference, abbreviated as EMI), and at the same time, the heat dissipation efficiency of the electronic component 21 can be improved.
[0075] In another embodiment, such as Figure 5-1 and Figure 5-2As shown, the frame 53 can optionally expose the side surface 24c of the encapsulation layer 24 or simultaneously expose the first surface 24a and the side surface 24c of the encapsulation layer 24, and a shielding layer 56 is formed on the first surface 24a and the side surface 24c of the encapsulation layer 24, so that the shielding layer 56 contacts the frame 53. In addition, a plurality of conductive elements 55 can be implanted on the frame 53 that exposes the second surface 24b of the encapsulation layer 24, for subsequent grounding connection to an external device through the plurality of conductive elements 55. In addition, the connection of the conductive element 55 to the frame 53 can make the overall electronic package more stable when connected to an external device.
[0076] Please refer to Figure 6A and Figure 6B , which shows a cross-sectional view and a bottom view schematic diagram of the fifth embodiment of the electronic package 6 of the present application. In this embodiment, conductive elements 65 are mainly implanted on the frame 63 that exposes the second surface 24b of the encapsulation layer 24, so as to avoid the problem of insufficient support in the peripheral area of the electronic package 6 when the electronic package 6 is too large and the area of the substrate 20 is too small when the electronic package 6 is subsequently placed on an external device. At the same time, when the conductive elements 65 implanted on the frame 63 are connected to an external device, the heat generated by the electronic package 6 can be transferred to the external device for heat dissipation. In addition, the connection of the conductive element 65 to the frame 63 can make the overall electronic package 6 more stable when connected to an external device.
[0077] The present application also provides an electronic package 2, 3, 4, 5, 6, including: a substrate 20, an electronic component 21, an encapsulation layer 24, and frames 23, 33, 43, 53, 63.
[0078] The described electronic component 21 is disposed on the substrate 20 and electrically connected to the substrate 20. In addition, electronic accessories 22 can be further provided on the substrate 20.
[0079] The encapsulation layer 24 is formed on the substrate 20 to cover the electronic component 21. Among them, the encapsulation layer 24 has opposite first surface 24a and second surface 24b and side surface 24c adjacent to the first surface 24a and the second surface 24b, and the second surface 24b of the encapsulation layer 24 is flush with the second side 20b of the substrate 20.
[0080] The described frames 23, 33, 53, 63 are embedded in the encapsulation layer 24 and are located at the periphery of the substrate 20 and do not contact the substrate 20.
[0081] In one embodiment, the frame 23 is annular and surrounds the periphery of the substrate 20.
[0082] In one embodiment, the frames 23, 33, 53, 63 are partially exposed from the encapsulation layer 24.
[0083] In one embodiment, the electronic component 21 is partially exposed from the encapsulation layer 24.
[0084] In one embodiment, the electronic package 5 further includes a shielding layer 56 formed on the encapsulation layer 24.
[0085] In one embodiment, conductive elements 65 can be implanted on the carrier 63 exposing the second surface 24b of the encapsulation layer 24.
[0086] In summary, for the electronic package and its manufacturing method of the present application, through the design of the carrier, the thermal stress within the electronic package is resisted, so that warping of the encapsulation layer can be avoided during thermal cycling. Moreover, since the carrier does not contact the substrate, it is beneficial to dispose electronic components on the substrate without increasing the size of the substrate, thereby reducing the manufacturing cost.
[0087] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the rights protected by the present application shall be as listed in the claims.
Claims
1. An electronic package, characterized in that, Comprising: A substrate; An electronic component, disposed on the substrate and electrically connected to the substrate; A packaging layer, formed on the substrate to encapsulate the electronic component; And A frame, embedded in the packaging layer and located around the periphery of the substrate without contacting the substrate.
2. The electronic package according to claim 1, wherein The frame is annular and surrounds the periphery of the substrate.
3. The electronic package according to claim 1, wherein The frame is partially exposed from the packaging layer.
4. The electronic package according to claim 1, wherein The packaging layer has opposite first and second surfaces, and the bottom surface of the frame is flush with the second surface of the packaging layer.
5. The electronic package according to claim 1, wherein The packaging layer has opposite first and second surfaces, and the top surface of the frame is flush with the first surface of the packaging layer.
6. The electronic package according to claim 1, wherein The packaging layer has opposite first and second surfaces and a side surface adjacent to the first and second surfaces, and the frame is exposed from the side surface.
7. The electronic package according to claim 1, characterized in that, The packaging layer has opposite first and second surfaces, and the height of the frame is greater than the height of the electronic component, so that the frame is exposed from the first surface of the packaging layer, and the electronic component is embedded in the packaging layer.
8. The electronic package according to claim 1, wherein, The electronic component is partially exposed from the packaging layer.
9. The electronic package according to claim 1, 5 or 6, characterized in that, The electronic package further includes a shielding layer formed on the packaging layer.
10. The electronic package according to claim 9, wherein The electronic package further includes a plurality of conductive elements formed on the frame.
11. The electronic package according to claim 1, characterized in that, The electronic package further includes a plurality of conductive elements, disposed on the substrate and exposed from the packaging layer.
12. The electronic package according to claim 1, wherein, The electronic package further includes a plurality of conductive elements, disposed on the frame and exposed from the packaging layer.