Wafer-to-wafer bonding structure

Abstract

A wafer-to-wafer bonding structure may include a first wafer including a first circuit electrically connected to a first bonding pad structure, a second wafer including a second circuit electrically connected to a second bonding pad structure, and a third wafer including a third circuit electrically connected to the second bonding pad structure. A first dielectric window structure; and a first alignment mark that aligns the first dielectric window structure in a plan view.

Description

Technical Field

[0001] Embodiments of the present utility model relate to semiconductor technology, and more particularly to a wafer-to-wafer bonding structure. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally formed by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using lithography techniques to form circuit components and elements thereon. Dozens, hundreds, or thousands of integrated circuits can be fabricated on a single semiconductor wafer, and the individual die on the wafer can be separated by sawing along the scribe lines between the integrated circuits. Each die can be individually packaged in, for example, a multi-chip module or other type of package.

[0003] As semiconductor packages become more complex, the package size has tended to become larger to accommodate a greater number of integrated circuits and / or die per package. These larger and more complex semiconductor packages pose additional challenges for achieving effective and reliable electrical interconnections within the semiconductor package. As such, there is a continuing need to improve semiconductor package design, with an emphasis on reducing interconnect length, and thus reducing ohmic loss, heat generation, and signal delay. A promising approach involves forming a wafer-level semiconductor package by bonding one or more wafers containing semiconductor devices to each other. Summary of the Utility Model

[0004] The purpose of the present utility model is to provide a wafer-to-wafer bonding structure to solve at least one of the above problems.

[0005] In some embodiments, a wafer-to-wafer bonding structure is provided. The wafer-to-wafer bonding structure includes a first wafer including a first circuit electrically connected to a first bonding pad structure; a first dielectric window structure; and a first alignment mark that aligns with the first dielectric window structure in a plan view.

[0006] According to one embodiment of the present utility model, it further includes: a second wafer including: a second circuit electrically connected to a second bonding pad structure; and a second alignment mark, wherein: the first wafer is directly bonded to the second wafer such that the first bonding pad structure is electrically connected to the second bonding pad structure, and the first alignment mark is aligned relative to the second alignment mark, and the first dielectric window structure is transparent to visible light to allow imaging of the first alignment mark and the second alignment mark using visible light.

[0007] According to one embodiment of the present utility model, the first wafer is bonded to the second wafer in a face-to-back manner; the first bonding pad structure is a back-side bonding pad structure formed on the back side of the first wafer, such that the back-side bonding pad structure is electrically connected to a via hole structure formed in a semiconductor material layer, and the via hole structure is electrically connected to the first circuit; and the second bonding pad structure is a front-side bonding pad structure formed on the front side of the second wafer, such that the front-side bonding pad structure is electrically connected to an electrical interconnection structure of the second wafer.

[0008] According to one embodiment of the present utility model, the first wafer is bonded to the second wafer in a face-to-face manner; the first bonding pad structure of the first wafer is a first front-side bonding pad structure formed on the first wafer; and the second bonding pad structure of the second wafer is a second front-side bonding pad structure formed on the second wafer.

[0009] According to one embodiment of the present utility model, it further includes: a third wafer, including: a third circuit electrically connected to a third bonding pad structure; a second dielectric window structure; and a third alignment mark that aligns with the second dielectric window structure in the plan view, wherein: the first wafer further includes a fourth bonding pad structure and a fourth alignment mark; the third wafer is directly bonded to the first wafer such that the third bonding pad structure is directly bonded to the fourth bonding pad structure of the first wafer; the third alignment mark is aligned with the fourth alignment mark of the first wafer; and the first dielectric window structure and the second dielectric window structure are laterally displaced from each other to be non-overlapping in the plan view.

[0010] According to one embodiment of the present utility model, the first circuit includes a complementary metal oxide semiconductor circuit or a fin field effect transistor.

[0011] According to one embodiment of the present utility model, the first alignment mark is located in a first dielectric layer of the first wafer.

[0012] According to one embodiment of the present utility model, the first alignment mark is separated from the first dielectric window structure by a portion of the first dielectric layer.

[0013] According to one embodiment of the present utility model, the first wafer further includes a substrate on the first dielectric layer and a semiconductor material layer on the substrate, and the first dielectric window structure vertically extends through the substrate and the semiconductor material layer.

[0014] According to one embodiment of the present utility model, the first wafer further includes a second dielectric layer on the semiconductor material layer, and the first dielectric window structure vertically extends through the second dielectric layer. Description of the Drawings

[0015] The embodiments of the present utility model can be better understood according to the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to the standard practice in this industry, various components (features) in the drawings are not necessarily drawn to scale. In fact, the sizes of various components may be arbitrarily enlarged or reduced for clear illustration.

[0016] Figure 1 A vertical cross-sectional schematic diagram of a wafer-to-wafer bonding structure according to various embodiments.

[0017] Figure 2A A vertical cross-sectional schematic diagram of a structure after forming complementary metal-oxide-semiconductor (CMOS) transistors, metal interconnect structures, and dielectric material layers according to various embodiments.

[0018] Figure 2B A vertical cross-sectional schematic diagram of a further structure during the formation of a front-side interconnect structure according to various embodiments.

[0019] Figure 3A A vertical cross-sectional schematic diagram of an intermediate structure that can be used to form devices on a semiconductor wafer according to various embodiments.

[0020] Figure 3B A vertical cross-sectional schematic diagram of a further intermediate structure that can be used to form devices on a semiconductor wafer according to various embodiments.

[0021] Figure 3C A vertical cross-sectional schematic diagram of a further intermediate structure that can be used to form devices on a semiconductor wafer according to various embodiments.

[0022] Figure 3D A vertical cross-sectional schematic diagram of a further intermediate structure that can be used to form devices on a semiconductor wafer according to various embodiments.

[0023] Figure 4A A vertical cross-sectional schematic diagram of an intermediate structure that can be used to form a first wafer according to various embodiments.

[0024] Figure 4B A vertical cross-sectional schematic diagram of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0025] Figure 4C A vertical cross-sectional schematic diagram of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0026] Figure 4D A vertical cross-sectional schematic diagram of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0027] Figure 4E Schematic vertical cross - section views of further intermediate structures that can be used to form a first wafer, according to various embodiments.

[0028] Figure 4F Schematic vertical cross - section views of further intermediate structures that can be used to form a first wafer, according to various embodiments.

[0029] Figure 5A Schematic vertical cross - section views of further intermediate structures that can be used to form a first wafer, according to various embodiments.

[0030] Figure 5B Schematic vertical cross - section views of further intermediate structures that can be used to form a first wafer, according to various embodiments.

[0031] Figure 5C Schematic vertical cross - section views of further intermediate structures that can be used to form a first wafer, according to various embodiments.

[0032] Figure 6A Schematic vertical cross - section views of intermediate structures that can be used to form a second wafer, according to various embodiments.

[0033] Figure 6B Schematic vertical cross - section views of further intermediate structures that can be used to form a second wafer, according to various embodiments.

[0034] Figure 6C Schematic vertical cross - section views of a second wafer formed by further processing Figure 6B the intermediate structure, according to various embodiments.

[0035] Figure 7A Schematic vertical cross - section views of an intermediate structure, where a first wafer is positioned close to a second wafer before forming a wafer - to - wafer bonding structure, according to various embodiments.

[0036] Figure 7B Schematic vertical cross - section views of a wafer - to - wafer bonding structure formed by bonding Figure 7A a first wafer and a second wafer, according to various embodiments.

[0037] Figure 8A Schematic vertical cross - section views of further intermediate structures of a wafer - to - wafer bonding structure including Figure 7B ..., according to various embodiments.

[0038] Figure 8B Schematic vertical cross - section views of an intermediate structure, where a third wafer is positioned close to a first wafer before forming a further wafer - to - wafer bonding structure, according to various embodiments.

[0039] Figure 8C A vertical cross-sectional view of a further wafer-to-wafer bonding structure formed by bonding a third wafer and a first wafer according to various embodiments. Figure 8B

[0040] Figure 8D A vertical cross-sectional view of a further intermediate structure of a wafer-to-wafer bonding structure according to various embodiments, including Figure 8C

[0041] Figure 9A A vertical cross-sectional view of an intermediate structure that can be used to form a first wafer according to various embodiments.

[0042] Figure 9B A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0043] Figure 9C A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0044] Figure 9D A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0045] Figure 9E A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0046] Figure 9F A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0047] Figure 10A A vertical cross-sectional view of a further intermediate structure that can be formed by further processing an intermediate structure according to various embodiments. Figure 9F

[0048] Figure 10B A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0049] Figure 11A A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0050] Figure 11B A vertical cross-sectional view of a further intermediate structure that can be used to form a first wafer according to various embodiments.

[0051] Figure 12ASchematic vertical cross-section of an intermediate structure, where a first wafer is positioned close to a second wafer before forming a wafer-to-wafer bonding structure.

[0052] Figure 12B Schematic vertical cross-section of a wafer-to-wafer bonding structure formed by bonding a first wafer and a second wafer according to various embodiments. Figure 12A

[0053] Figure 13 Flowchart showing the operations of a method for forming a wafer-to-wafer bonding structure according to various embodiments.

[0054] Figure 14 Flowchart showing the operations of a further method for forming a wafer-to-wafer bonding structure according to various embodiments.

[0055] Reference numerals are as follows:

[0056] 8: Substrate

[0057] 8a: First substrate

[0058] 8b: Second substrate

[0059] 8c: Third substrate

[0060] 10: Semiconductor material layer

[0061] 10a: First semiconductor material layer

[0062] 10b: Second semiconductor material layer

[0063] 10c: Third semiconductor material layer

[0064] 12: Shallow trench isolation structure

[0065] 14: Source / drain region

[0066] 15: Semiconductor channel

[0067] 18: Metal-semiconductor alloy region

[0068] 20: Gate structure

[0069] 22: Gate dielectric

[0070] 24: Gate electrode

[0071] 26: Dielectric gate spacer

[0072] 28: Gate capping dielectric

[0073] [[ID=7D]]31A: Planarization dielectric layer

[0074] 31B: First interconnect level dielectric layer

[0075] 32: Second interconnection level dielectric layer

[0076] 33: Third interconnection level dielectric layer

[0077] 41L: First metal line

[0078] 41V: Contact via hole structure

[0079] 42L: Second metal line

[0080] 42V: First metal via hole structure

[0081] 50: Device area

[0082] 52: Peripheral logic area

[0083] 75: Complementary metal oxide semiconductor circuit

[0084] 95: Back-end device

[0085] 100,800c,1200b: Wafer-to-wafer bonding structure

[0086] 102a: First wafer

[0087] 102b: Second wafer

[0088] 102c: Third wafer

[0089] 104a: First bonding pad structure

[0090] 104b: Second bonding pad structure

[0091] 104c: Third bonding pad structure

[0092] 104d: Fourth bonding pad structure

[0093] 106a: First dielectric window structure

[0094] 106b: Second dielectric window structure

[0095] 106L: Dielectric material layer

[0096] 108a: First alignment mark

[0097] 108b: Second alignment mark

[0098] 108c: Third alignment mark

[0099] 108d: Fourth alignment mark

[0100] 110: Carrier substrate

[0101] 112: Adhesive

[0102] 114: Optical system

[0103] 116: Visible light

[0104] 118: Via hole structure

[0105] 122: Interconnection structure

[0106] 124a: First dielectric layer

[0107] 124b: Second dielectric layer

[0108] 124c: Third dielectric layer

[0109] 124d: Fourth dielectric layer

[0110] 124e: Fifth dielectric layer

[0111] 200a, 200b, 300a, 300b, 300c, 300d, 400a, 400b, 400c, 400d, 400e, 400f, 500a, 500b, 500c, 600a, 600b, 600c, 700a, 800a, 800b, 800d, 900a, 900b, 900c, 900d, 900e, 900f, 1000a, 1000b, 1100a, 1100b, 1200a: Intermediate structure

[0112] 301: Transistor structure

[0113] 304L: Metal line

[0114] 304V: Via hole

[0115] 310L: First backside metal line

[0116] 310V: First backside via hole

[0117] 312: First backside metallization layer

[0118] 402: Opening

[0119] 1300, 1400: Method

[0120] 1302, 1304, 1306, 1308, 1402, 1404, 1406, 1408, 1410: Operation

[0121] L0: Contact level structure

[0122] L1: First interconnection level structure

[0123] L2: Second interconnection level structure

[0124] L3: The third interconnection level structure

[0125] M1: The first metal layer

[0126] V1: The first via layer Detailed implementation manners

[0127] It should be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. The following describes specific examples of each component and its arrangement to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present utility model. For example, the size of the element is not limited to the range or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the element. In addition, in the subsequent description, embodiments in which a first component is formed above or on a second component include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components such that the first and second components do not directly contact. In addition, different examples in the disclosure may use repeated reference signs and / or words. These repeated signs or words are for the purpose of simplification and clarity, and are not intended to limit the relationship between each embodiment and / or the described appearance structure.

[0128] Furthermore, for the convenience of describing the relationship between an element or component in the drawings and another (plural) element or (plural) component, spatially relative terms may be used, such as "under", "below", "lower part", "above", "upper part" and similar terms. In addition to the orientation shown in the drawings, the spatially relative terms also cover different orientations during the use or operation of the device. The device may also be positioned otherwise (for example, rotated 90 degrees or in other orientations), and the description of the spatially relative terms used may be interpreted accordingly. Unless otherwise explicitly stated, each element having the same reference sign is assumed to have the same material composition and a thickness within the same thickness range.

[0129] Wafer-on-wafer (WoW) bonding can be performed to provide increasingly smaller devices. Stacked wafers of logic-logic, logic-memory, or memory-memory devices can increase the number of transistors per unit area by reducing the interconnect distance, while also reducing the overall power consumption. Existing wafer-on-wafer structures have bonding pitches in the range of 1 to 20 μm. Systems exhibiting sub-micron bonding pitches may be beneficial for future applications. However, one of the difficulties in achieving smaller bonding pitches is the challenge posed by the desire to accurately observe alignment and overlay marks before and after wafer bonding, respectively. Different from alignment in lithography, where the lens can observe the alignment marks unobstructed, typical wafer-on-wafer bonding requires separately measuring the positions of the alignment marks on each wafer, storing the position data in the tool computer, and then moving the wafers together based on the stored data. Due to the size of the optical lens, it must be moved away before bonding, which requires moving the wafer more than 10 to 100 mm, which may result in a positioning error of about 50 nm over the travel distance in this range.

[0130] After completion of the bonding, in order to measure the overlay, an imaging system may be required to image the bonding marks of silicon with various thicknesses (e.g., tens to hundreds of microns). Currently, infrared light wavelengths above 1000 nm are used because this wavelength can penetrate the silicon wafer. However, the relatively long wavelength of infrared light limits the resolution of the infrared radiation. In this regard, the wavelength of infrared radiation is approximately twice that of visible light, so its resolution is about twice worse than that of visible light. Therefore, wafer-on-wafer alignment and overlay errors may exceed those of lithography, and it may be difficult to achieve alignment and overlay below 20 nm.

[0131] Various embodiments disclosed herein may be advantageous by using visible light to establish a direct line of sight to observe the alignment marks on individual wafers through systems and methods. In this regard, various embodiments disclosed herein for wafer-to-wafer bonding may include one or more dielectric windows that allow visible light to transmit through, such that the alignment marks can be imaged with visible light. Using visible light can improve alignment and overlay. In this regard, alignment can be performed when the first wafer and the second wafer are in close proximity to each other. In this way, using visible light can allow the resolution of the alignment marks to be doubled, thereby improving the alignment and overlay characteristics.

[0132] An embodiment of a method of forming a component of a wafer-to-wafer bonding structure may include forming a plurality of circuits in a semiconductor material layer of a substrate of a first wafer, forming an interconnect layer including an electrical interconnect structure over the plurality of circuits such that the electrical interconnect structure is electrically connected to the plurality of circuits, forming a first dielectric window structure extending through the semiconductor material layer and into the substrate, and removing a backside portion of the substrate to expose the first dielectric window structure. The method may further include forming a via structure electrically connected to the electrical interconnect structure and extending into the semiconductor material layer such that the step of removing the backside portion of the substrate further exposes the via structure.

[0133] A further embodiment of a method of forming a wafer-to-wafer bonding structure may include placing a first wafer including a first circuit adjacent to a second wafer including a second circuit such that a first bonding pad structure of the first wafer is substantially aligned with a second bonding pad structure of the second wafer, and imaging one or more first alignment marks and second alignment marks through a first dielectric window structure formed in the first wafer to determine the position of the one or more first alignment marks of the first wafer relative to the one or more second alignment marks of the second wafer. The method may further include adjusting the relative positions of the first wafer and the second wafer based on the imaging of the one or more first alignment marks and the one or more second alignment marks through the first dielectric window structure to align the one or more first alignment marks of the first wafer relative to the one or more second alignment marks of the second wafer, placing the first wafer in contact with the second wafer such that the first bonding pad structure of the first wafer contacts the second bonding pad structure of the second wafer, and performing a direct bonding process to bond the first wafer to the second wafer.

[0134] An exemplary wafer-to-wafer bonding structure may include a first wafer including a first circuit electrically connected to a first bonding pad structure; a first dielectric window structure; and a first alignment mark aligned with the first dielectric window structure in a plan view. The exemplary wafer-to-wafer bonding structure may further include a second wafer including a second circuit electrically connected to a second bonding pad structure; and a second alignment mark. The first wafer is directly bonded to the second wafer such that the first bonding pad structure is electrically connected to the second bonding pad structure and the first alignment mark is aligned relative to the second alignment mark. The first dielectric window structure may be configured to be transparent to visible light to permit imaging of the first alignment mark and the second alignment mark using visible light.

[0135] As used herein, "back-end-of-line (BEOL)" components represent any components formed at the contact level or a metal interconnect level. A "metal interconnect level" represents a level through which metal interconnect structures (such as metal lines or metal vias) vertically extend. As used herein, "front-end-of-line (FEOL)" components represent any components before the formation of any contact level structure, if a contact layer structure is formed later, or if no contact level structure or any metal interconnect structure is formed (i.e., no contact level structure or any metal interconnect structure is formed later).

[0136] Generally speaking, FEOL components represent semiconductor device components that can be formed during a complementary metal oxide semiconductor (CMOS) manufacturing process before the formation of any contact via structure at the nodes of field effect transistors, and BEOL components represent semiconductor device components that can be formed during the CMOS manufacturing process during and after the earliest contact via process (forming a contact via structure at the nodes of field effect transistors). In an embodiment of any implementation step integrated into the CMOS manufacturing process, components formed before the formation of any contact via structure at the nodes of field effect transistors can be referred to as FEOL components, and components formed during and after the earliest contact via formation process of forming a contact via structure at the nodes of field effect transistors can be referred to as BEOL components.

[0137] Generally speaking, FEOL components can be formed in a semiconductor substrate, directly on a semiconductor substrate, or indirectly on a semiconductor substrate, without any metal interconnect structure between the semiconductor substrate and the components. Examples of FEOL components include planar field effect transistors that use a portion of the semiconductor substrate as part of the channel, fin field effect transistors (FinFETs), gate-all-around field effect transistors, and any device component in which a lateral extent of a portion containing semiconductor is greater than a lateral extent of a corresponding device component. Generally, for each FEOL component, no metal interconnect structure vertically extends from a first horizontal plane including a top surface of the FEOL component to a second horizontal plane including a bottom surface of the FEOL component, or the FEOL component contacts a semiconductor material layer or is laterally surrounded by a semiconductor material layer having a greater lateral extent than the FEOL component.

[0138] Examples of back-end components may include any dielectric material layer embedded in a metal interconnect structure or in a metal line structure, any metal interconnect structure, memory cells formed without using any part of a semiconductor substrate, selector cells formed without using any part of a semiconductor substrate, thin-film transistors formed using any part of a semiconductor substrate (however, may include a patterned semiconductor material portion having a lateral extent not exceeding the lateral extent of an individual thin-film transistor or a cluster of combined thin-film transistors), and bonding pads. Generally, for each back-end component, at least one metal interconnect structure extends vertically from a first horizontal plane including the top surface of the back-end to a second horizontal plane including the bottom surface of the back-end component, and the back-end component does not contact a semiconductor material layer and is not laterally surrounded by a semiconductor material layer having a larger lateral extent than the back-end component.

[0139] Figure 1 For various embodiments, a vertical cross-sectional schematic view of a wafer-to-wafer bonding structure 100. The wafer-to-wafer bonding structure 100 may include a first wafer 102a bonded to a second wafer 102b. The first wafer 102a may include a first circuit (please refer to Figure 2A and Figure 2B complementary metal-oxide semiconductor circuit 75, Figure 3A transistor structure 301, etc.) formed in a first semiconductor material layer 10a of a first substrate 8a. The first circuit (complementary metal-oxide semiconductor circuit 75, transistor structure 301) may be electrically connected to a first bonding pad structure 104a. The first wafer 102a may further include a first dielectric window structure 106a and a first alignment mark 108a. As Figure 1 shown, in a plan view (when viewed along Figure 1 the z direction of

[0140] ), the first alignment mark 108a may be aligned with the first dielectric window structure 106a. Figure 1In an exemplary embodiment, the first wafer 102a may be temporarily adhered to the carrier substrate 110 with an adhesive 112. A material transparent to visible light may be selected for the carrier substrate 110. The adhesive 112 may be configured to be separated from the carrier substrate 110 and the first wafer 102a by applying heat or ultraviolet radiation (i.e., UV light). The first dielectric window structure 106a may be configured to be transparent to visible light 116. In this way, the optical system 114 may be used to image the first alignment mark 108a relative to the second alignment mark 108b of the second wafer 102b by transmitting and receiving visible light 116 through the first dielectric window structure 106a. In this regard, the first dielectric window structure 106a may be formed of a material transparent to visible light, such as silicon dioxide. In other embodiments, other transparent materials may be used to form the first dielectric window structure 106a. Compared with an alternative embodiment that does not include the first dielectric window structure 106a, using visible light 116 may allow the first wafer 102a to be positioned more accurately relative to the second wafer 102b.

[0141] The second wafer 102b may include a second circuit (refer to Figure 2A and Figure 2B the complementary metal oxide semiconductor circuit 75, Figure 3A the transistor structure 301, etc.) formed in a second semiconductor material layer 10b above the second substrate 8b. The second circuit (complementary metal oxide semiconductor circuit 75) may be electrically connected to the second bonding pad structure 104b. The first wafer 102a may be directly bonded to the second wafer 102b such that the first bonding pad structure 104a is electrically connected to the second bonding pad structure 104b, and the first alignment mark 108a is aligned with the second alignment mark 108b.

[0142] As Figure 1 shown, the first wafer 102a may be bonded to the second wafer 102b in a face-to-back manner. In this regard, the first bonding pad structure 104a may be configured as a backside bonding pad structure in a first dielectric layer 124a on the backside of the first substrate 8a of the first wafer 102a. In this way, the first bonding pad structure 104a may be electrically connected to a via structure 118 formed in the first semiconductor material layer 10a and penetrating the first substrate 8a. The via structure 118 may also be configured to be electrically connected to the first circuit (complementary metal oxide semiconductor circuit 75, transistor structure 301). Furthermore, as Figure 1As shown, the second bonding pad structure 104b can be configured as a front-side bonding pad structure formed in a second dielectric layer 124b on the front side of the second wafer 102b. The second bonding pad structure 104b can be electrically connected to the front-side interconnect structure 122 (sometimes also referred to as an electrical interconnect structure) of the second wafer 102b. The first wafer 102a may further include additional front-side interconnect structures 122 formed in a third dielectric layer 124c.

[0143] The first alignment mark 108a and the first bonding pad structure 104a can be formed in the first dielectric layer 124a, as Figure 1 shown. Similarly, the second alignment mark 108b and the second bonding pad structure 104b can be formed in the second dielectric layer 124b. The first wafer 102a can be bonded to the second wafer 102b by performing a hybrid bonding process such that a direct dielectric-to-dielectric bond can be formed between the first dielectric layer 124a and the second dielectric layer 124b. Similarly, the hybrid bonding process can result in a direct metal-to-metal bond between the first bonding pad structure 104a and the second bonding pad structure 104b. The formation of the first wafer 102a is described in more detail below with reference to Figures 4A to 5C and the formation of the second wafer 102b is described in more detail below with reference to Figures 6A to 6C . The process of aligning and bonding the first wafer 102a to the second wafer 102b in a face-to-back manner is described in more detail below with reference to Figure 7A and Figure 7B . In various other embodiments, the first wafer 102a can be bonded to the second wafer 102b in a face-to-face manner, which is described in more detail below with reference to Figure 1 Figures 9A to 12B

[0144] Figure 2A

[0145] FIG. 200a is a vertical cross-sectional schematic view of an intermediate structure 200a after forming complementary metal-oxide semiconductor (CMOS) transistors, metal interconnect structures, and dielectric material layers in accordance with various embodiments. The intermediate structure 200a is an exemplary structure that can be used to form the first circuit and the second circuit in the first wafer 102a and the second wafer 102b, respectively. The intermediate structure 200a can include a substrate 8, which can be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 can include a semiconductor material layer 10 at least on the upper portion of the substrate 8. The substrate 8 can include a bulk semiconductor substrate (such as a silicon substrate) in which the semiconductor material layer 10 continuously extends from the top surface of the substrate 8 to the bottom surface of the substrate 8, or include a semiconductor-on-insulator (SOI) layer in which the semiconductor material layer 10 is a top semiconductor layer covering a buried insulating layer (such as a silicon oxide layer). This structure can include various device regions 50 in which devices are subsequently formed.

[0145] This structure may also include a peripheral logic region 52, in which electrical connections can be subsequently formed between various device regions and various peripheral circuits (including field effect transistors). During a front-end operation, semiconductor devices (such as field effect transistors (FETs)) can be formed on and / or in the semiconductor material layer 10. For example, by forming shallow trenches and subsequently filling the shallow trenches with a dielectric material (such as silicon oxide), the shallow trench isolation structure 12 can be formed in the upper portion of the semiconductor material layer 10. Other suitable dielectric materials are also contemplated in the embodiments of the present invention. Various doped wells (not explicitly shown) can be formed in respective regions of the upper portion of the semiconductor material layer 10 by performing a masked ion implantation process.

[0146] By depositing and patterning a gate dielectric layer, a gate electrode layer, and a gate capping dielectric layer, the gate structure 20 can be formed above the top surface of the substrate 8. Each gate structure 20 can include a vertical stack of a gate dielectric 22, a gate electrode 24, and a gate capping dielectric 28, which are collectively referred to herein as the gate stack. An ion implantation process can be performed to form extension implant regions, which can include source extension regions and drain extension regions. Dielectric gate spacers 26 can be formed around the gate stack (gate dielectric 22, gate electrode 24, and gate capping dielectric 28). The components of each gate stack (gate dielectric 22, gate electrode 24, and gate capping dielectric 28) and the dielectric gate spacers 26 can constitute the gate structure 20. An additional ion implantation process can be performed, using the gate structure 20 as a self-aligned implantation mask to form a deep source region.

[0147] This deep source region can include a deep source region and a deep drain region. The upper portion of the deep source region can overlap with a part of the extension implant region. Depending on the electrical biasing, each combination of the extension implant region and the deep source region can constitute a source / drain region 14. The semiconductor channel 15 can be formed below each gate stack (gate dielectric 22, gate electrode 24, and gate capping dielectric 28) between adjacent pairs of source / drain regions 14. A metal-semiconductor alloy region 18 can be formed on the top surface of each source / drain region 14.

[0148] A field effect transistor may be formed on a semiconductor material layer 10. Each field effect transistor may include a gate structure 20, a semiconductor channel 15, a pair of source / drain regions 14 (one of which serves as the source region and the other as the drain region), and an optional metal-semiconductor alloy region 18. A complementary metal oxide semiconductor circuit 75 may be provided on the semiconductor material layer 10, which may include peripheral circuits for a transistor array, such as thin film transistors (TFTs) and phase-change material (PCM) switches, etc.

[0149] In one embodiment, the substrate 8 may include a single crystalline silicon substrate, and the complementary metal oxide semiconductor circuit 75 may include a corresponding portion of the single crystalline silicon substrate as the semiconductor channel. As used herein, a "semiconductor" element represents an element having a conductivity in the range of 1.0x 10 -6 S / cm to 1.0x 10 5 S / cm. As used herein, a "semiconductor material" represents a material having a conductivity in the range of 1.0x 10 -6 S / cm to 1.0x 10 5 S / cm in the absence of electrical dopants, and capable of producing a doped material having a conductivity in the range of 1.0 S / cm to 1.0x 10 5 S / cm after doping with appropriate electrical dopants.

[0150] Various interconnect hierarchical structures may be subsequently formed, which may form the front-side interconnect layer described above. The interconnect hierarchical structure may be referred to as the underlying interconnect hierarchical structure and may be formed before any additional back-end devices (such as additional memory devices). In some embodiments, one or more additional devices may be formed above one or more layers of the interconnect hierarchical metal lines. For example, one or more additional devices may include thin film transistors, memory devices, or phase-change material switches.

[0151] The underlying interconnect hierarchical structure may include a contact hierarchical structure L0, a first interconnect hierarchical structure L1, and a second interconnect hierarchical structure L2. The contact hierarchical structure L0 may include a planarized dielectric layer 31A, the planarized dielectric layer 31A including a planarizable dielectric material, such as silicon oxide. The contact hierarchical structure L0 also includes various contact via hole structures 41V, the contact via hole structures 41V contacting a corresponding one of the source / drain regions 14 or the gate electrode 24 and formed in the planarized dielectric layer 31A.

[0152] The first interconnect level structure L1 may include a first interconnect level dielectric (ILD) layer 31B and first metal lines 41L formed in the first interconnect level dielectric layer 31B. The first interconnect level dielectric layer 31B is also referred to as the first wire level dielectric layer. The first metal lines 41L may contact corresponding ones of the contact via hole structures 41V. The second interconnect level structure L2 may include a second interconnect level dielectric layer 32 and a stack of a first via level dielectric material layer and a second wire level dielectric material layer or a wire and via level dielectric material layer. The second interconnect level dielectric layer 32 may include second interconnect level metal interconnect structures therein, and the second interconnect level metal interconnect structures include first metal via hole structures 42V and second metal lines 42L. The top surface of the second metal lines 42L may be coplanar with the top surface of the second interconnect level dielectric layer 32.

[0153] Figure 2B FIG. is a vertical cross-sectional schematic diagram of a further intermediate structure 200b during the formation of one or more additional back-end devices (such as phase change material switches, memory devices, etc.) according to various embodiments. One or more additional back-end devices may be formed in the device region 50 above the second interconnect level structure L2. A third interconnect level dielectric layer 33 may be formed during the formation of one or more additional back-end devices. The combination of all structures at the level of one or more back-end devices 95 may be referred to as the third interconnect level structure L3. In other embodiments, depending on circuit design considerations, various additional interconnect layers may be formed above the intermediate structure 200b as needed.

[0154] Figures 3A to 3D FIG. is a vertical cross-sectional schematic diagram that can be used to form intermediate structures 300a, 300b, 300c, 300d in the first wafer 102a according to various embodiments. The intermediate structure 300a may include a semiconductor material layer 10 having a plurality of transistor structures 301 formed on a substrate 8 (sometimes referred to as a semiconductor substrate) in a front-end process, as referred to above with reference to Figure 2A and Figure 2B described. In this exemplary embodiment, the transistor structures 301 are shown as fin field effect transistors. However, other types of transistor structures may be formed in the semiconductor material layer 10. For example, in other embodiments, the semiconductor material layer 10 may include complementary metal oxide semiconductor circuits 75, as referred to above with reference to Figure 2A and Figure 2B described. Each transistor structure 301 may be separated from each other by a plurality of shallow trench isolation structures 12. The intermediate structure 300a may further include a planarized dielectric layer 31A, and the planarized dielectric layer 31A includes a planarizable dielectric material, such as silicon oxide.

[0155] Figure 3B The intermediate structure 300b can be formed from Figure 3A the intermediate structure 300a by removing the top of the planarized dielectric layer 31A above the top surface of the transistor structure 301 and by forming a via structure 118 through the semiconductor material layer 10. As shown, the via structure 118 can be formed in the shallow trench isolation structure 12 in the region between the transistor structures 301. The via structure 118 can have a width in the range of about 10 nm to 20 nm, but narrower or wider via structures 118 can be used. As Figure 3B shown, deep vias can be formed to penetrate the semiconductor material layer 10 and enter the substrate 8. In other embodiments, the via structure 118 can be formed at locations other than between the transistor structures 301.

[0156] Figure 3C The intermediate structure 300c can be formed from Figure 3B the intermediate structure 300b by forming an additional layer of the planarized dielectric layer 31A above the via structure 118. Via 304V can then be formed in the planarized dielectric layer 31A. Thus, as Figure 3C shown, a first via layer V1 and a first metal layer M1 can be formed. As Figure 3C shown, the first via layer V1 can represent the top structure of the semiconductor material layer 10, and the first metal layer M1 can be the front-side interconnect structure 122 to be formed. In various embodiments, one or more additional metal lines 304L and vias 304V can be formed above the first via layer V1 and the first metal layer M1. For example, in some embodiments, the final front-side interconnect structure can include 10 to 20 interconnect levels formed in 10 to 20 corresponding front-side dielectric layers.

[0157] Figure 3D is a vertical cross-sectional schematic diagram of a further intermediate structure 300d that can be used to form the first wafer 102a according to various embodiments. In this regard, the intermediate structure 300c can be flipped (e.g., refer to Figure 3D ) Figure 3C so that additional back-end processes can be performed to form a back-side interconnect structure (e.g., refer to Figure 1 the first bonding pad structure 104a formed in the first dielectric layer 124a). In this regard, the back-side portion of the substrate 8 can be removed by a planarization process, and a plurality of via holes (not shown) can be formed in the remaining portion of the substrate 8. As Figure 3D shown, a first back-side via 310V can then be formed. Then, a first back-side metallization layer 312 including a first back-side metal line 310L can be formed.

[0158] As Figure 3DAs shown, the dorsal portion of the substrate 8 including the first dorsal vias 310V and the first dorsal metallization layer 312 can form the first component of the dorsal interconnect structure. In some embodiments, a plurality of additional metal lines and vias can then be formed above the first dorsal vias 310V and the first dorsal metallization layer 312 to form additional components of the dorsal interconnect structure. For example, in some embodiments, the final dorsal interconnect structure can include 5 to 10 interconnect levels formed in 5 to 10 corresponding dorsal dielectric layers. Then, the first dielectric layer 124a and the first bonding pad structure 104a (e.g., refer to Figure 1 ) can be formed above the dorsal interconnect structure ( Figure 3D The first dielectric layer 124a and the first bonding pad structure 104a are not shown).

[0159] Figures 4A to 4F According to various embodiments, it is a schematic vertical cross-sectional view of the corresponding intermediate structures 400a, 400b, 400c, 400d, 400e, 400f that can be used to form the first wafer 102a. In this regard, Figure 4A The intermediate structure 400a can include a first substrate 8a, and the first substrate 8a can be a semiconductor substrate, such as a crystalline silicon substrate or a semiconductor-on-insulator substrate. Figure 4B The intermediate structure 400b can be formed from the intermediate structure 400a by forming a plurality of first circuits (e.g., refer to Figure 2A and Figure 2B The complementary metal oxide semiconductor circuit 75 of Figure 3A The transistor structure 301 of

[0160] Figure 4C The intermediate structure 400c can be formed from the intermediate structure 400b by forming a via structure 118 and an interconnect structure 122 above the Figure 4B The intermediate structure 400b. In this regard, the via structure 118 and the interconnect structure 122 can be formed as described above with reference to Figures 3A to 3C . Then, the third dielectric layer 124c (e.g., refer to Figure 1 ) can be formed above the via structure 118 and the interconnect structure 122. For clarity, Figure 1 and Figure 4C Only a single via structure 118 is shown. However, as Figures 3B to 3D shown, a plurality of via structures 118 can be formed. The via structure can be electrically connected to a plurality of first circuits (complementary metal oxide semiconductor circuit 75, transistor structure 301) and the interconnect structure 122.

[0161] Figure 4DThe intermediate structure 400d can be formed from the intermediate structure 400c by forming an opening 402 in the intermediate structure 400c. The opening 402 can be formed in various shapes. For example, the opening 402 can be formed as a trench or as a cylindrical opening, etc. The opening 402 can be formed by performing an anisotropic etching process on Figure 4C the intermediate structure 400c. In this regard, a patterned photoresist (not shown) can be formed above the intermediate structure 400c, and the patterned photoresist can be used as an etching mask during the etching process. In this regard, the etching process can etch the portion of the intermediate structure 400c that is not shielded by the patterned photoresist, thereby forming the opening 402. As Figure 4D shown, the etching process can be performed to etch through the third dielectric layer 124c, through the first semiconductor material layer 10a, and into a portion of the first substrate 8a. Then, a dielectric material (such as Figure 4E the dielectric material layer 106L shown) can be deposited in the opening 402 to form the first dielectric window structure 106a, as described in more detail below with reference to Figure 4E and Figure 4F more details.

[0162] By depositing the dielectric material layer 106L above the Figure 4D intermediate structure 400d, an Figure 4E intermediate structure can be formed. In this regard, the dielectric material layer 106L can be formed as a blanket layer and can include various dielectric materials, such as silicon oxide. Other suitable dielectric materials are within the scope of consideration in the embodiments of the present invention. By removing the portion of the dielectric material layer 106L above the top surface of the third dielectric layer 124c, an Figure 4F intermediate structure 400f can be formed. For example, a planarization process (such as chemical mechanical polishing (CMP)) can be performed to remove the excess portion of the dielectric material layer 106L. The portion of the dielectric material layer 106L remaining in the opening 402 can thereby form the first dielectric window structure 106a.

[0163] Figures 5A to 5C FIGS. are vertical cross-sectional schematic diagrams of corresponding intermediate structures 500a, 500b, 500c that can be used to form the first wafer 102a according to various embodiments. In this regard, the intermediate structure 500a can be formed by attaching the carrier substrate 110 to the Figure 4F intermediate structure 400f. The carrier substrate 110 can be adhered to the intermediate structure 400f using an adhesive 112. The adhesive 112 can be configured as a temporary adhesive that can be separated from the carrier substrate 110 and the intermediate structure 400f by applying heat or UV light. Figure 5BThe intermediate structure 500b can be formed from the intermediate structure 500a by removing the dorsal portion of the first substrate 8a. For example, a grinding process can be performed on the dorsal side of the first substrate 8a to reduce the thickness of the first substrate 8a. In this way, the grinding process can remove a sufficient amount of the first substrate 8a such that the via hole structure 118 and the bottom surface of the first dielectric window structure 106a can be exposed, as Figure 5B shown.

[0164] Next, the intermediate structure 500c can be formed by depositing a first dielectric layer 124a over the dorsal side of the first substrate 8a and then forming a first bonding pad structure 104a and a first alignment mark 108a. In this regard, the first dielectric layer 124a can be patterned to form openings corresponding to the positions of the first bonding pad structure 104a and the first alignment mark 108a to be formed. Then, a conductive material can be deposited in the openings to form the first bonding pad structure 104a and the first alignment mark 108a. As Figure 5C shown, the intermediate structure 500c can include a first wafer 102a bonded to a carrier substrate 110 having a removable adhesive 112.

[0165] Figure 6A and Figure 6B are vertical cross-sectional schematic diagrams of corresponding intermediate structures 600a, 600b that can be used to form a second wafer 102b according to various embodiments, and Figure 6C is a vertical cross-sectional schematic diagram of a final second wafer 102b formed by further processing Figure 6B the intermediate structure 600b. In this regard, Figure 6A the intermediate structure 600a can include a second substrate 8b, which can be a semiconductor substrate, such as a crystalline silicon substrate or a semiconductor-on-insulator substrate. Figure 6B The intermediate structure 600b of Figure 2A can be formed from the intermediate structure 600a by forming a plurality of second circuits (such as, for example, referring to Figure 2B the complementary metal-oxide semiconductor circuit 75 of Figure 3A and

[0166] the transistor structure 301 of Figure 6C etc.) in a second semiconductor material layer 10b of the second substrate 8b.

[0166] According to various embodiments, the intermediate structure 600c of the second wafer 102b including Figure 6C shown can be formed from the intermediate structure 600b by further processing Figure 6B the intermediate structure 600b. These further processing operations can include forming an interconnect structure 122 over the intermediate structure 600b of Figure 6B . In this regard, the interconnect structure 122 can be formed as described above with reference to FIGS. 2A to 3C. Then, a second dielectric layer 124b (such as, for example, referring to Figure 1) may be formed over the interconnect structure 122. Next, the second dielectric layer 124b may be patterned, and a conductive material may be formed over the patterned second dielectric layer 124b to form the second bonding pad structure 104b and the second alignment mark 108b.

[0167] Figure 7A Shows an intermediate structure 700a according to various embodiments, where before forming the wafer-to-wafer bonding structure 100 (e.g., refer to Figure 1 and Figure 7B ), the first wafer 102a (e.g., refer to Figure 5C ) is positioned close to the second wafer 102b (e.g., refer to Figure 6C ). The intermediate structure 700a may be formed by positioning the first wafer 102a relative to the second wafer 102b such that the first bonding pad structure 104a of the first wafer 102a is generally aligned with the second bonding pad structure 104b of the second wafer 102b. Next, an optical system 114 may be used to image one or more first alignment marks 108a and one or more second alignment marks 108b through the first dielectric window structure 106a formed in the first wafer 102a to determine the positions of the one or more first alignment marks 108a of the first wafer 102a relative to the one or more second alignment marks 108b of the second wafer 102b.

[0168] In this regard, imaging the one or more first alignment marks 108a and the one or more second alignment marks 108b may include using the optical system 114 to direct visible light 116 through the first dielectric window structure 106a and observing or recording the images of the one or more first alignment marks 108a and the one or more second alignment marks 108b generated by the visible light 116. Next, the relative positions of the first wafer 102a and the second wafer 102b may be adjusted to align the one or more first alignment marks 108a of the first wafer 102a with the one or more second alignment marks 108b of the second wafer 102b. The degree to which the relative positions of the first wafer 102a and the second wafer 102b can be adjusted may depend on the imaging of the one or more first alignment marks 108a and the one or more second alignment marks 108b through the first dielectric window structure 106a. After the first wafer 102a and the second wafer 102b are aligned relative to each other, a bonding operation may be performed, as described in more detail with reference to Figure 7B more specifically.

[0169] Figure 7B According to various embodiments, a wafer-to-wafer bonding structure 100 is formed by bonding Figure 7A the first wafer 102a and the second wafer 102b. In this regard, the wafer-to-wafer bonding structure 100 may be formed from Figure 7AThe intermediate structure 700a is formed by placing the first wafer 102a in contact with the second wafer 102b such that the first bonding pad structure 104a of the first wafer 102a contacts the second bonding pad structure 104b of the second wafer 102b, and by performing a direct bonding process to bond the first wafer 102a and the second wafer 102b. In this regard, the first wafer 102a can be bonded to the second wafer 102b by performing a hybrid bonding process such that a direct dielectric-to-dielectric bond can be formed between the first dielectric layer 124a and the second dielectric layer 124b. Similarly, the hybrid bonding process can create a direct metal-to-metal bond between the first bonding pad structure 104a and the second bonding pad structure 104b.

[0170] As Figure 1 and Figure 7B shown, the first wafer 102a can be bonded to the second wafer 102b in a face-to-back manner. In this regard, the first bonding pad structure 104a can be configured as a back-side bonding pad structure in the first dielectric layer 124a formed on the back side of the first substrate 8a of the first wafer 102a, as described above with reference to Figure 5C Thus, the first bonding pad structure 104a can be electrically connected to the via structure 118, which is formed in the first semiconductor material layer 10a and penetrates the first substrate 8a. The via structure 118 can also be configured to be electrically connected to the first circuits (complementary metal oxide semiconductor circuits 75, transistor structures 301) formed in the first semiconductor material layer 10a of the first wafer 102a.

[0171] Furthermore, as Figure 7B shown, the second bonding pad structure 104b can be configured as a front-side bonding pad structure in the second dielectric layer 124b formed on the front side of the second wafer 102b. The second bonding pad structure 104b can be electrically connected to the interconnect structure 122 of the second wafer 102b. The first wafer 102a can further include an additional front-side interconnect structure 122 formed in the third dielectric layer 124c. The interconnect structure 122 formed in the third dielectric layer 124c can be used to form electrical connections with subsequently formed additional circuit components and / or additional interconnect structures.

[0172] Figure 8A and Figure 8B are vertical cross-sectional schematic diagrams of corresponding intermediate structures 800a, 800b that can be used to form further wafer-to-wafer bonding structures according to various embodiments, while Figure 8C is a vertical cross-sectional schematic diagram of the final wafer-to-wafer bonding structure 800c (e.g., refer to Figure 8C ) according to various embodiments. The intermediate structure 800a can be obtained from Figure 7BThe wafer-to-wafer bonding structure 100 is formed by removing the carrier substrate 110 of the wafer-to-wafer bonding structure 100. In this regard, the adhesive 112 (for example, refer to Figure 7B ) can be a removable adhesive that can be deactivated by applying heat or UV light. In this way, the carrier substrate 110 can be removed by first deactivating the adhesive 112 and then removing the carrier substrate 110. Then, the final intermediate structure 800b can be used as a starting structure, on which additional circuit components can be formed. For example, one or more additional wafers can be subsequently bonded to the intermediate structure 800b, as described in more detail below with reference to [[ID= and ​ .

[0173] ​ Figure 800b shows an intermediate structure according to various embodiments, in which a third wafer 102c is positioned close to the first wafer 102a before forming the wafer-to-wafer bonding structure 800c (for example, refer to ​ ). The third wafer 102c can be similar to the first wafer 102a and can be formed using a process similar to that described above with reference to ​ . In this regard, the third wafer 102c can include a third circuit (for example, refer to ​ and ​ complementary metal-oxide semiconductor circuit 75, ​ transistor structure 301, etc.) that can be formed in a third semiconductor material layer 10c of a third substrate 8c. The third circuit can be electrically connected to the third bonding pad structure 104c through a via structure 118. As shown in ​ , the third wafer 102c can include a second dielectric window structure 106b that can be laterally displaced from the first dielectric window structure 106a of the first wafer 102a and is shown as non-overlapping in a plan view (i.e., along the ​ z direction).

[0174] The third wafer 102c can also include a third alignment mark 108c that aligns with the second dielectric window structure 106b in a plan view (when viewed along the ​ z direction). As shown in ​As shown, the first wafer 102a may further include one or more fourth bonding pad structures 104d and one or more fourth alignment marks 108d. In this way, by transmitting and receiving visible light 116 through the second dielectric window structure 106b and observing or recording an image of one or more third alignment marks 108c and one or more fourth alignment marks 108d generated by the visible light 116, the optical system 114 can be used to image the third alignment marks 108c of the third wafer 102c relative to the fourth alignment marks 108d of the first wafer 102a. Then, the relative positions of the third wafer 102c and the first wafer 102a can be adjusted to align one or more third alignment marks 108c of the third wafer 102c relative to one or more fourth alignment marks 108d of the first wafer 102a. The degree to which the relative positions of the third wafer 102c and the first wafer 102a can be adjusted may depend on the imaging of one or more third alignment marks 108c and one or more fourth alignment marks 108d through the second dielectric window structure 106b. After the third wafer 102c and the first wafer 102a are aligned relative to each other, a bonding operation can be performed, as described in more detail with reference to ​ More detailed description.

[0175] ​ According to various embodiments, a wafer-to-wafer bonding structure 800c formed by bonding ​ the third wafer 102c and the first wafer 102a. In this regard, the wafer-to-wafer bonding structure 800c can be formed from ​ an intermediate structure 800b by placing the third wafer 102c in contact with the first wafer 102a such that the third bonding pad structure 104c of the third wafer 102c contacts the fourth bonding pad structure 104d of the first wafer 102a and by performing a direct bonding process to bond the third wafer 102c to the first wafer 102a. In this regard, the third wafer 102c can be bonded to the first wafer 102a by performing a hybrid bonding process such that a direct dielectric-to-dielectric bond can be formed between the third dielectric layer 124c of the first wafer 102a and the fourth dielectric layer 124d of the third wafer 102c. Similarly, the hybrid bonding process can create a direct metal-to-metal bond between the third bonding pad structure 104c and the fourth bonding pad structure 104d.

[0176] As ​ shown, the third wafer 102c can be bonded to the first wafer 102a in a face-to-back manner. In this regard, the third bonding pad structure 104c can be configured as a backside bonding pad structure in the fourth dielectric layer 124d formed on the backside of the third substrate 8c of the third wafer 102c. In various embodiments, similar to that described above with reference to ​The described process can be used for the third bonding pad structure 104c. In this way, the third bonding pad structure 104c can be electrically connected to the via structure 118, which is formed in the third semiconductor material layer 10c and penetrates the third substrate 8c. The via structure 118 can also be configured to be electrically connected to the third circuits (complementary metal oxide semiconductor circuit 75, transistor structure 301) formed in the third semiconductor material layer 10c.

[0177] Furthermore, as ​ shown, the fourth bonding pad structure 104d can be configured as a front-side bonding pad structure in the third dielectric layer 124c on the front side of the first wafer 102a. The fourth bonding pad structure 104d can be electrically connected to the interconnect structure 122 of the first wafer 102a. The third wafer 102c can also include additional front-side interconnect structures 122 formed in the fifth dielectric layer 124e. The interconnect structures 122 formed in the fifth dielectric layer 124e can be used to form electrical connections with subsequently formed additional circuit components and / or additional interconnect structures.

[0178] ​ For various embodiments, a schematic vertical cross-sectional view of a further intermediate structure 800d of the wafer-to-wafer bonding structure 800c including ​ . The intermediate structure 800d can be formed from the ​ wafer-to-wafer bonding structure 800c by removing the carrier substrate 110. In this regard, the adhesive 112 (for example, refer to ​ ) can be a removable adhesive that can be deactivated by applying heat or UV light. In this way, the carrier substrate 110 can be removed by first deactivating the adhesive 112 and then removing the carrier substrate 110. Then, the final intermediate structure 800d can be used as a starting structure on which additional circuit components can be formed. For example, one or more additional wafers can be subsequently bonded to the intermediate structure 800d, as described in more detail with reference to ​ and ​ .

[0179] ​ For various embodiments, schematic vertical cross-sectional views of corresponding intermediate structures 900a, 900b, 900c, 900d, 900e, 900f that can be used to form the first wafer 102a. The first wafer 102a formed according to the process described with reference to ​ can be used in embodiments of wafer-to-wafer bonding structures 1200b having a face-to-face bonding method (for example, refer to ​ ). In this regard, ​ the intermediate structure 900a can include a first substrate 8a, and the first substrate 8a can be a semiconductor substrate, such as a crystalline silicon substrate or a semiconductor-on-insulator substrate. ​The intermediate structure 900b can be formed from the intermediate structure 900a by forming a plurality of first circuits (for example, refer to ​ and ​ complementary metal-oxide semiconductor circuits 75 of ​ the transistor structure 301, etc.) in the first semiconductor material layer 10a of the first substrate 8a.

[0180] ​ The intermediate structure 900c can be formed from the intermediate structure 900b by forming a via hole structure 118 and an interconnect structure 122 above the ​ intermediate structure 900b. In this regard, the via hole structure 118 and the interconnect structure 122 can be formed as described above with reference to ​ . Then, a first dielectric layer 124a can be formed above the via hole structure 118 and the interconnect structure 122. For clarity, ​ only a single via hole structure 118 is shown. However, as ​ shown, a plurality of via hole structures 118 can be formed. The via hole structure can be electrically connected to the plurality of first circuits (complementary metal-oxide semiconductor circuits 75, transistor structure 301) and the interconnect structure 122.

[0181] ​ The intermediate structure 900d can be formed from the intermediate structure 900c by forming an opening 402 in the intermediate structure 900c. The opening 402 can be formed in various shapes. For example, the opening 402 can be formed as a trench or as a cylindrical opening, etc. The opening 402 can be formed by performing an anisotropic etching process on the ​ intermediate structure 900c. In this regard, a patterned photoresist (not shown) can be formed above the intermediate structure 900c, and the patterned photoresist can be used as an etching mask during the etching process. In this regard, the etching process can etch the portion of the intermediate structure 900c not covered by the patterned photoresist, thereby forming the opening 402. As ​ shown, the etching process can be performed to etch through the first dielectric layer 124a, through the first semiconductor material layer 10a, and into a part of the first substrate 8a. Then, a dielectric material (such as the dielectric material layer 106L as ​ shown) can be deposited in the opening 402 to form a first dielectric window structure 106a, as described in more detail below with reference to ​ and ​ .

[0182] By depositing a dielectric material layer 106L above the ​ intermediate structure 900d, ​The intermediate structure 900e. In this regard, the dielectric material layer 106L can be formed as a blanket layer and can include various dielectric materials, such as silicon oxide. Other suitable dielectric materials are within the scope of consideration of the embodiments of the present invention. By removing the portion of the dielectric material layer 106L above the top surface of the first dielectric layer 124a, ​ the intermediate structure 900f can be formed. For example, a planarization process (such as chemical mechanical polishing (CMP)) can be performed to remove the excess portion of the dielectric material layer 106L. The portion of the dielectric material layer 106L remaining in the opening 402 can in turn form the first dielectric window structure 106a.

[0183] ​ FIG. is a vertical cross-sectional schematic diagram of a further intermediate structure 1000a according to various embodiments. The intermediate structure 1000a can be formed by further processing ​ the intermediate structure 900f. These further processing operations can include forming an interconnect structure 122 above ​ the intermediate structure 900f. In this regard, the interconnect structure 122 can be formed as described above with reference to ​ FIG. Then, an additional amount of the first dielectric layer 124a can be formed above the interconnect structure 122. Then, the first dielectric layer 124a can be patterned, and a conductive material can be formed above the patterned first dielectric layer 124a to form the first bonding pad structure 104a and the first alignment mark 108a.

[0184] ​ FIG. is a vertical cross-sectional schematic diagram of a further intermediate structure 1000b that can be used to form the first wafer 102a according to various embodiments. In this regard, the intermediate structure 1000b can be formed by attaching the carrier substrate 110 to ​ the intermediate structure 1000a. The carrier substrate 110 can be adhered to the intermediate structure 1000a using an adhesive 112. The adhesive 112 can be configured to be separable from the carrier substrate 110 and the intermediate structure 1000a by applying heat or UV light.

[0185] ​ and ​ FIG. is a vertical cross-sectional schematic diagram of further intermediate structures 1100a, 1100b that can be used to form the first wafer 102a according to various embodiments. ​ The intermediate structure 1100a can be formed from the intermediate structure 1000b by removing the backside portion of the first substrate 8a. For example, a grinding process can be performed on the backside of the first substrate 8a to reduce the thickness of the first substrate 8a. In this way, the grinding process can remove a sufficient amount of the first substrate 8a such that the bottom surfaces of the via hole structure 118 and the first dielectric window structure 106a can be exposed, as ​ shown. In this way, the first wafer 102a can be produced.

[0186] The intermediate structure 1100b can be formed from the intermediate structure 1100a by attaching the second carrier substrate 110 to the back side of the first wafer 102a (e.g., refer to ​ ), and by removing the carrier substrate 110 from the front side of the first wafer 102a (e.g., refer to ​ ). As described above, the carrier substrate 110 (e.g., refer to ​ ) can be separated from the adhesive 112 by applying heat or UV light. After removing ​ 's carrier substrate 110, the front surface of the first wafer 102a can be exposed. In this way, the first bonding pad structure 104a can be configured as a front-side bonding pad structure. Then, the final first wafer 102a can be bonded to the second wafer 102b to form a wafer-to-wafer bonding structure with a face-to-face bonding manner, as further described in detail with reference to ​ and ​ .

[0187] ​ Shows an intermediate structure 1200a according to various embodiments, where before forming the wafer-to-wafer bonding structure 1200b (e.g., refer to ​ ), the first wafer 102a (e.g., refer to ​ ) has been flipped and positioned close to the second wafer 102b (e.g., refer to ​ ). The first wafer 102a can be formed according to the process described with reference to ​ above, and the second wafer 102b can be formed according to the process described with reference to ​ above. The intermediate structure 1200a can be formed by positioning the first wafer 102a relative to the second wafer 102b such that the first bonding pad structure 104a of the first wafer 102a is generally aligned with the second bonding pad structure 104b of the second wafer 102b. Then, an optical system 114 can be used to image one or more first alignment marks 108a and one or more second alignment marks 108b through the first dielectric window structure 106a formed in the first wafer 102a to determine the position of one or more first alignment marks 108a of the first wafer 102a relative to one or more second alignment marks 108b of the second wafer 102b.

[0188] In this regard, imaging the one or more first alignment marks 108a and the one or more second alignment marks 108b may include directing visible light 116 through the first dielectric window structure 106a using the optical system 114, and observing or recording images of the one or more first alignment marks 108a and the one or more second alignment marks 108b produced by the visible light 116. Next, the relative positions of the first chip 102a and the second chip 102b may be adjusted to align the one or more first alignment marks 108a of the first chip 102a with respect to the one or more second alignment marks 108b of the second chip 102b. The extent to which the relative positions of the first chip 102a and the second chip 102b can be adjusted may depend on the imaging of the one or more first alignment marks 108a and the one or more second alignment marks 108b through the first dielectric window structure 106a. After the first chip 102a and the second chip 102b are aligned relative to each other, a bonding operation may be performed, as shown with reference to ​ Describe in more detail.

[0189] ​ According to various embodiments, by bonding ​ The wafer-to-wafer bonding structure 1200b is formed by the first wafer 102a and the second wafer 102b. In this regard, the wafer-to-wafer bonding structure 1200b can be formed by ​ The intermediate structure 1200a is formed by placing the first wafer 102a in contact with the second wafer 102b such that the first bonding pad structure 104a of the first wafer 102a contacts the second bonding pad structure 104b of the second wafer 102b, and performing a direct bonding process to bond the first wafer 102a and the second wafer 102b. In this regard, the first wafer 102a can be bonded to the second wafer 102b by performing a hybrid bonding process, such that a direct dielectric-to-dielectric bond is formed between the first dielectric layer 124a and the second dielectric layer 124b. Similarly, the hybrid bonding process can produce a direct metal-to-metal bond between the first bonding pad structure 104a and the second bonding pad structure 104b.

[0190] like ​ As shown, the first wafer 102a can be bonded to the second wafer 102b in a face-to-face manner. In this regard, the first bonding pad structure 104a can be configured as a front side bonding pad structure formed in the first dielectric layer 124a on the front side of the first wafer 102a, as described above with reference to ​ As described above, the first bonding pad structure 104a can be electrically connected to the via structure 118, which is formed in the first semiconductor material layer 10a and penetrates the first substrate 8a. The via structure 118 can also be configured to be electrically connected to the first circuit (complementary metal oxide semiconductor circuit 75, transistor structure 301) formed in the first semiconductor material layer 10a.

[0191] Furthermore, as ​ shown, the second bonding pad structure 104b can be configured as a front-side bonding pad structure in a second dielectric layer 124b formed on the front side of the second wafer 102b. The second bonding pad structure 104b can be electrically connected to the interconnect structure 122 of the second wafer 102b. After bonding the first wafer 102a to the second wafer 102b, the carrier substrate 110 can be removed. As described above, the carrier substrate 110 can be removed by applying heat or UV light to the adhesive 112 to separate the adhesive 112 from the carrier substrate 110 and the wafer-to-wafer bonding structure 1200b. After removing the carrier substrate 110, the final wafer-to-wafer bonding structure 1200b can be used as a further intermediate structure to which one or more additional wafers (not shown) can be bonded.

[0192] ​ FIG. is a flowchart showing the operations of a method 1300 for forming wafer-to-wafer bonding structures 100, 800c, 1200b in accordance with various embodiments. At operation 1302, the method 1300 can include forming a plurality of circuits (complementary metal oxide semiconductor circuits 75, transistor structures 301) in a first semiconductor material layer 10a of a first substrate 8a of a first wafer 102a. At operation 1304, the method 1300 can include forming an interconnect layer that includes an interconnect structure 122 over the plurality of circuits (complementary metal oxide semiconductor circuits 75, transistor structures 301) such that the interconnect structure 122 is electrically connected to the plurality of circuits (complementary metal oxide semiconductor circuits 75, transistor structures 301). At operation 1306, the method 1300 can include forming a first dielectric window structure 106a that extends through the first semiconductor material layer 10a and into the first substrate 8a. At operation 1308, the method 1300 can include removing a back-side portion of the first substrate 8a to expose the first dielectric window structure 106a (e.g., refer to ​ and ​ ).

[0193] Method 1300 may further include forming a via structure 118 that is electrically connected to the interconnect structure 122 and extends into the first semiconductor material layer 10a. Further, the operation of removing the backside portion of the first substrate 8a may further include exposing the via structure 118. In accordance with operation 1306 of forming the first dielectric window structure 106a, method 1300 may further include forming an opening 402 that extends through the first semiconductor material layer 10a and into the first substrate 8a, and filling the opening 402 with a dielectric material layer 106L that is transparent to visible light. In accordance with operation 1306 of forming the first dielectric window structure 106a, method 1300 may further include forming a first dielectric window structure 106a that has a lateral displacement relative to the via structure 118 such that the first dielectric window structure 106a appears non-overlapping with the second dielectric window structure 106b of the second wafer 102a in a plan view (i.e., along ​ the z direction), where the first wafer 102a and the second wafer 102b are aligned relative to each other.

[0194] Method 1300 may further include forming one or more backside bonding pad structures (first bonding pad structure 104a) on the backside of the first substrate 8a such that the backside bonding pad structures (first bonding pad structure 104a) are electrically connected to the via structure 118 (e.g., please refer to ​ ). Method 1300 may further include forming one or more backside alignment marks (first alignment mark 108a) on the backside of the first substrate 8a such that the one or more backside alignment marks (first alignment mark 108a) are aligned with the first dielectric window structure 106a in a plan view (i.e., along ​ the z direction). In accordance with method 1300, the process of forming one or more backside bonding pad structures (first bonding pad structure 104a) and one or more backside alignment marks (first alignment mark 108a) may further include depositing a first dielectric layer 124a on the backside of the first substrate 8a and patterning the dielectric material layer 106L to form a patterned dielectric material layer 106L that includes openings corresponding to the locations of the one or more backside bonding pad structures (first bonding pad structure 104a) and the one or more backside alignment marks (first alignment mark 108a) to be formed subsequently. Method 1300 may further include depositing a conductive material over the patterned first dielectric layer 124a to form one or more backside bonding pad structures (first bonding pad structure 104a) and one or more backside alignment marks (first alignment mark 108a) (e.g., please refer to ​ ).

[0195] In other embodiments (e.g., please refer to ​),Method 1300 may further include forming one or more front - side bonding pad structures (first bonding pad structure 104a) on the front side of the first wafer 102a such that the one or more front - side bonding pad structures (first bonding pad structure 104a) are electrically connected to the interconnect structure 122. Method 1300 may further include forming front - side alignment marks (first alignment marks 108a) on the front side of the first wafer 102a such that the front - side alignment marks (first alignment marks 108a) are aligned with the first dielectric window structure 106a in a planar view (i.e., along ​ the z - direction).

[0196] ​ According to various embodiments, a flowchart showing the operations of a method 1400 for forming wafer - to - wafer bonding structures 100, 800c, 1200b is shown. At operation 1402, method 1400 may include placing a first wafer 102a including a first circuit close to a second wafer 102b including a second circuit such that the first bonding pad structure 104a of the first wafer 102a is generally aligned with the second bonding pad structure 104b of the second wafer 102b (e.g., refer to ​ and ​ ). At operation 1404, method 1400 may include imaging one or more first alignment marks 108a and second alignment marks 108b through the first dielectric window structure 106a formed in the first wafer 102a to determine the position of the one or more first alignment marks 108a of the first wafer 102a relative to the second alignment marks 108b of the second wafer 102b. At operation 1406, method 1400 may include adjusting the relative positions of the first wafer 102a and the second wafer 102b based on the imaging of the one or more first alignment marks 108a and second alignment marks 108b through the first dielectric window structure 106a to align the one or more first alignment marks 108a of the first wafer 102a with the second alignment marks 108b of the second wafer 102b. At operation 1408, method 1400 may include placing the first wafer 102a in contact with the second wafer 102b such that the first bonding pad structure 104a of the first wafer 102a contacts the second bonding pad structure 104b of the second wafer 102b (e.g., refer to ​ and ​ ). At operation 1410, method 1400 may include bonding the first wafer 102a to the second wafer 102b by performing a direct bonding process.

[0197] In operation 1404 that includes imaging one or more first alignment marks 108a and one or more second alignment marks 108b through a first dielectric window structure 106a formed in a first wafer 102a, method 1400 may further include directing visible light 116 through the first dielectric window structure 106a and observing or recording an image of the one or more first alignment marks 108a and the one or more second alignment marks 108b generated by the visible light 116. In operation 1408 that includes placing the first wafer 102a close to the second wafer 102b, method 1400 may further include placing the first wafer 102a and the second wafer 102b in a face-to-back manner (e.g., refer to ​ , ​ and ​ ). In this face-to-back configuration, the first bonding pad structure 104a of the first wafer 102a may be a back-side bonding pad structure formed on the back side of the first substrate 8a of the first wafer 102a, and the second bonding pad structure 104b of the second wafer 102b may be a front-side bonding pad structure formed on the front side of the second wafer 102b, such that the second bonding pad structure 104b is electrically connected to the interconnect structure 122 of the second wafer 102b.

[0198] In a further embodiment (e.g., refer to ​ and ​ ), in operation 1408 that includes placing the first wafer 102a close to the second wafer 102b, method 1400 may further include placing the first wafer 102a and the second wafer 102b in a face-to-face manner. In this configuration, the first bonding pad structure 104a of the first wafer 102a may be configured as a first front-side bonding pad structure formed on the first wafer 102a (e.g., refer to ​ ), and the second bonding pad structure 104b of the second wafer 102b may be configured as a second front-side bonding pad structure formed on the second wafer 102b (e.g., refer to ​ [[ID=I7]]).

[0199] In a further embodiment (e.g., refer to ​ , ​ and ​),Method 1400 may further include placing a third wafer 102c including a third circuit (complementary metal oxide semiconductor circuit 75, transistor structure 301) close to the first wafer 102a such that one or more third bonding pad structures 104c of the third wafer 102c are substantially aligned with one or more fourth bonding pad structures 104d of the first wafer 102a. Method 1400 may further include imaging one or more third alignment marks 108c and one or more fourth alignment marks 108d through a second dielectric window structure 106b formed in the third wafer 102c to determine the positions of the one or more third alignment marks 108c of the third wafer 102c relative to the one or more fourth alignment marks 108d of the first wafer 102a.

[0200] Method 1400 may further include adjusting the relative positions of the third wafer 102c and the first wafer 102a based on the imaging of the one or more third alignment marks 108c and the one or more fourth alignment marks 108d through the second dielectric window structure 106b to align the one or more third alignment marks 108c of the third wafer 102c with the one or more fourth alignment marks 108d of the first wafer 102a. Method 1400 may further include placing the third wafer 102c in contact with the first wafer 102a such that the third bonding pad structure 104c of the third wafer 102c contacts one or more fourth bonding pad structures 104d of the first wafer 102a, and performing a direct bonding process to bond the third wafer 102c to the first wafer 102a (for example, refer to ​ ). According to method 1400, adjusting the relative positions of the third wafer 102c and the first wafer 102a may further include ensuring that the first dielectric window structure 106a and the second dielectric window structure 106b are non-overlapping in a plan view (for example, refer to ​ ).

[0201] Referring to all the drawings and according to various embodiments of the present invention, wafer-to-wafer bonding structures 100, 800c, 1200b are provided. The wafer-to-wafer bonding structures 100, 800c, 1200b may include a first wafer 102a including a first circuit (complementary metal oxide semiconductor circuit 75, transistor structure 301) electrically connected to a first bonding pad structure 104a; a first dielectric window structure 106a; and a first alignment mark 108a aligned with the first dielectric window structure 106a in a plan view (for example, along the ​ , ​ , ​ z direction).

[0202] In one embodiment, the wafer-to-wafer bonding structures 100, 800c, 1200b may further include a second wafer 102b that includes a second circuit (complementary metal oxide semiconductor circuit 75, transistor structure 301) electrically connected to a second bonding pad structure 104b; and a second alignment mark 108b. In this regard, the first wafer 102a may be directly bonded to the second wafer 102b such that the first bonding pad structure 104a is electrically connected to the second bonding pad structure 104b, and the first alignment mark 108a is aligned relative to the second alignment mark 108b. Furthermore, the first dielectric window structure 106a is transparent to visible light 116 to allow imaging of the first alignment mark 108a and the second alignment mark 108b using the visible light 116.

[0203] In some embodiments, the first wafer 102a may be bonded to the second wafer 102b in a face-to-back manner (e.g., refer to ​ and ​ ). In this configuration, the first bonding pad structure 104a may be configured as a back-side bonding pad structure formed on the back side of the first wafer 102a (e.g., refer to ​ ), such that the back-side bonding pad structure is electrically connected to a via structure 118 formed in the first semiconductor material layer 10a, and the via structure 118 is electrically connected to a first circuit (complementary metal oxide semiconductor circuit 75, transistor structure 301). Furthermore, in this configuration, the second bonding pad structure 104b may be a front-side bonding pad structure formed on the front side of the second wafer 102b (e.g., refer to ​ ), such that the front-side bonding pad structure is electrically connected to an electrical interconnect structure 122 of the second wafer 102b.

[0204] In some embodiments, the first wafer 102a may be bonded to the second wafer 102b in a face-to-face manner (e.g., refer to ​ ). In this configuration, the first bonding pad structure 104b of the first wafer 102a may be configured as a first front-side bonding pad structure formed on the first wafer 102a (e.g., refer to ​ ), and the second bonding pad structure 104b of the second wafer 102b may be configured as a second front-side bonding pad structure formed on the second wafer 102b (e.g., refer to ​ ).

[0205] In a further embodiment, the wafer-to-wafer bonding structures 100, 800c, 1200b may further include a third wafer 102c (e.g., refer to ​ and ​), the third wafer 102c may include a third circuit (complementary metal oxide semiconductor circuit 75, transistor structure 301), electrically connected to the third bonding pad structure 104c; a second dielectric window structure 106b; and a third alignment mark 108c, which is aligned with the second dielectric window structure 106b in a plan view (e.g., along ​ the z direction). In this embodiment, the first wafer 102a may further include a fourth bonding pad structure 104d and a fourth alignment mark 108d. Furthermore, the third wafer 102c may be directly bonded to the first wafer 102a such that the third bonding pad structure 104c is directly bonded to the fourth bonding pad structure 104d of the first wafer 102a, the third alignment mark 108c may be aligned with the fourth alignment mark 108d of the first wafer 102a, and the first dielectric window structure 106a and the second dielectric window structure 106b are laterally displaced from each other to be non-overlapping in a plan view, as ​ shown.

[0206] According to various embodiments of the present invention, a method for forming a component with a wafer-to-wafer bonding structure for a first wafer is provided. This method includes forming a plurality of circuits in a semiconductor material layer of a substrate of the first wafer; forming an interconnect layer, the interconnect layer including electrical interconnect structures above the plurality of circuits such that the electrical interconnect structures are electrically connected to the plurality of circuits; forming a first dielectric window structure extending through the semiconductor material layer and into the substrate; and removing a backside portion of the substrate to expose the first dielectric window structure.

[0207] In some other embodiments, the above method further includes forming a via structure electrically connected to the electrical interconnect structure and extending into the substrate, wherein the step of removing the backside portion of the substrate further exposes the via structure.

[0208] In some other embodiments, the step of forming the first dielectric window structure further includes: forming an opening extending through the semiconductor material layer and extending into the substrate; and filling the opening with a dielectric material transparent to visible light.

[0209] In some other embodiments, the step of forming the first dielectric window structure further includes: forming the first dielectric window structure having a lateral displacement relative to the via structure such that the first dielectric window structure is non-overlapping with a second dielectric window structure of a second wafer in a plan view, wherein the first wafer and the second wafer are aligned with each other.

[0210] In some other embodiments, the above method further includes forming a backside bonding pad structure on the backside of the substrate such that the backside bonding pad structure is electrically connected to the via structure; and forming a backside alignment mark on the backside of the substrate such that the backside alignment mark is aligned with the first dielectric window structure in a plan view.

[0211] In some other embodiments, the steps of forming the dorsal bonding pad structure and forming the dorsal alignment marks further include: depositing a dielectric material on the dorsal side of the substrate; patterning the dielectric material to form a patterned dielectric material including openings corresponding to the positions of the subsequent dorsal bonding pad structure and dorsal alignment marks to be formed; and depositing a conductive material over the patterned dielectric material to thereby form the dorsal bonding pad structure and the dorsal alignment marks.

[0212] In some other embodiments, the above method further includes forming a front-side bonding pad structure on the front side of the first wafer such that the front-side bonding pad structure is electrically connected to the electrical interconnect structure; and forming a front-side alignment mark on the front side of the first wafer such that the front-side alignment mark is aligned with the first dielectric window structure in a plan view.

[0213] According to various embodiments of the present invention, a method for forming a wafer-to-wafer bonding structure is provided, the method including placing a first wafer including a first circuit close to a second wafer including a second circuit such that the first bonding pad structure of the first wafer is substantially aligned with the second bonding pad structure of the second wafer; and imaging a first alignment mark and a second alignment mark through a first dielectric window structure formed in the first wafer to determine the position of the first alignment mark of the first wafer relative to the second alignment mark of the second wafer.

[0214] In some other embodiments, the step of imaging the first alignment mark and the second alignment mark through the first dielectric window structure further includes: guiding visible light through the first dielectric window structure; and observing or recording an image of the first alignment mark and the second alignment mark generated by the visible light.

[0215] In some other embodiments, the above method further includes adjusting the relative positions of the first wafer and the second wafer based on the imaging of the first alignment mark and the second alignment mark through the first dielectric window structure to align the first alignment mark of the first wafer with the second alignment mark of the second wafer; placing the first wafer in contact with the second wafer such that the first bonding pad structure of the first wafer contacts the second bonding pad structure of the second wafer; and performing a direct bonding process to bond the first wafer to the second wafer.

[0216] In some other embodiments, the step of placing the first wafer close to the second wafer further includes placing the first wafer and the second wafer in a face-to-back manner, wherein: the first bonding pad structure of the first wafer is a dorsal bonding pad structure formed on the dorsal side of the substrate of the first wafer; and the second bonding pad structure of the second wafer is a front-side bonding pad structure formed on the front side of the second wafer such that the front-side bonding pad structure is electrically connected to the second wafer.

[0217] In some other embodiments, the step of placing the first wafer adjacent to the second wafer further includes placing the first wafer and the second wafer face-to-face, and wherein: the first bonding pad structure of the first wafer includes a front-side bonding pad structure formed on the first wafer; and the second bonding pad structure of the second wafer is a second front-side bonding pad structure formed on the second wafer.

[0218] In some other embodiments, the method further includes placing a third wafer including a third circuit adjacent to the first wafer such that the third bonding pad structure of the third wafer is substantially aligned with the fourth bonding pad structure of the first wafer; and imaging a third alignment mark and a fourth alignment mark through a second dielectric window structure formed in the third wafer to determine the position of the third alignment mark of the third wafer relative to the fourth alignment mark of the first wafer.

[0219] In some other embodiments, the method further includes adjusting the relative positions of the third wafer and the first wafer based on the imaging of the third alignment mark and the fourth alignment mark through the second dielectric window structure to align the third alignment mark of the third wafer with the fourth alignment mark of the first wafer; placing the third wafer in contact with the first wafer such that the third bonding pad structure of the third wafer contacts the fourth bonding pad structure of the first wafer; and performing a direct bonding process to bond the third wafer to the first wafer.

[0220] In some other embodiments, the step of adjusting the relative positions of the third wafer and the first wafer further includes ensuring that the first dielectric window structure and the second dielectric window structure are non-overlapping in a plan view.

[0221] The foregoing text outlines the features of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A wafer-to-wafer bonding structure, characterized in that, Comprising: A first wafer, comprising: A first circuit, electrically connected to a first bonding pad structure; A first dielectric window structure; and A first alignment mark, aligning with the first dielectric window structure in a planar view.

2. The wafer-to-wafer bonding structure according to claim 1, wherein, Further comprising: A second wafer, comprising: A second circuit, electrically connected to a second bonding pad structure; and A second alignment mark, wherein: The first wafer is directly bonded to the second wafer such that the first bonding pad structure is electrically connected to the second bonding pad structure, and the first alignment mark is aligned relative to the second alignment mark, and The first dielectric window structure is transparent to visible light to allow imaging of the first alignment mark and the second alignment mark using visible light.

3. The wafer-to-wafer bonding structure according to claim 2, wherein, The first wafer is bonded to the second wafer in a face-to-back manner; The first bonding pad structure is a back-side bonding pad structure formed on the back side of the first wafer such that the back-side bonding pad structure is electrically connected to a via structure formed in a semiconductor material layer, and the via structure is electrically connected to the first circuit; and The second bonding pad structure is a front-side bonding pad structure formed on the front side of the second wafer such that the front-side bonding pad structure is electrically connected to an electrical interconnect structure of the second wafer.

4. The wafer-to-wafer bonding structure according to claim 2, wherein, The first wafer is bonded to the second wafer in a face-to-face manner; The first bonding pad structure of the first wafer is a first front-side bonding pad structure formed on the first wafer; and The second bonding pad structure of the second wafer is a second front-side bonding pad structure formed on the second wafer.

5. The wafer-to-wafer bonding structure according to any one of claims 1 to 4, characterized in that, Further comprising: A third wafer, comprising: A third circuit, electrically connected to a third bonding pad structure; A second dielectric window structure; and A third alignment mark, aligning with the second dielectric window structure in the planar view, wherein: The first wafer further comprises a fourth bonding pad structure and a fourth alignment mark; The third wafer is directly bonded to the first wafer such that the third bonding pad structure is directly bonded to the fourth bonding pad structure of the first wafer; The third alignment mark is aligned relative to the fourth alignment mark of the first wafer; and The first dielectric window structure and the second dielectric window structure are laterally displaced from each other to be non-overlapping in the planar view.

6. The wafer-to-wafer bonding structure according to any one of claims 1 to 4, characterized in that, The first circuit includes a complementary metal oxide semiconductor circuit or a fin field effect transistor.

7. The wafer-to-wafer bonding structure according to any one of claims 1 to 4, characterized in that The first alignment mark is located in a first dielectric layer of the first wafer.

8. The wafer-to-wafer bonding structure according to claim 7, wherein, The first alignment mark is separated from the first dielectric window structure by a portion of the first dielectric layer.

9. The wafer-to-wafer bonding structure according to claim 7, wherein, The first wafer further comprises a substrate on the first dielectric layer and a semiconductor material layer on the substrate, and the first dielectric window structure extends vertically through the substrate and the semiconductor material layer.

10. The wafer-to-wafer bonding structure as claimed in claim 9, wherein, The first wafer further comprises a second dielectric layer on the semiconductor material layer, and the first dielectric window structure extends vertically through the second dielectric layer.

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