Wafer-level wrapping type bump packaging structure

Abstract

A wafer-level package type bump packaging structure comprises a bare wafer structure, and a plurality of pad bases are fixed on the top surface of the bare wafer structure in an embedded manner; the upper side of the pad base is provided with a non-ferrous metal inner convex point, and the outer side of the non-ferrous metal inner convex point is fixedly provided with a full-wrapping inert metal layer. According to the utility model, the low-cost bump packaging structure is obtained, and the stability of low-cost bump packaging can be improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip packaging, and particularly relates to a wafer-level wrapped bump packaging structure. Background Art

[0002] In the field of drive chip packaging, due to the high-frequency input and output environment of drive chips, extremely high requirements are imposed on the input and output contacts of the chips. Currently, the mainstream input and output contacts of drive chips in the market are pure Au gold bumps, as Figure 1 shown.

[0003] However, with the increasing price of gold and the fierce competition in the display drive market, more and more customers need to change the original Au structure and develop diversified low-cost structures while meeting the basic requirements of the contacts. Low-cost composite structures of non-ferrous metals such as CuNi have emerged as the times require.

[0004] Currently, there is an IC package bump that uses a copper-nickel-gold combination to replace pure gold, which can effectively reduce costs. Its structure includes a carrier, a conductive layer, an insulating layer, a titanium layer, a first copper layer, a second copper layer, a nickel layer, and a gold layer arranged in sequence from bottom to top, as Figure 2 shown.

[0005] With market verification, the exposed structure of CuNiAu non-ferrous metals has also revealed its disadvantages due to the exposure of the underlying Cu non-ferrous metal. The most critical problem is the oxidation of the non-ferrous metal Cu, which reduces the reliability of the contacts, affects the service life of the contacts, and requires frequent replacement, greatly increasing the cost of replacement. Content of the Utility Model

[0006] In view of the above technical problems, the present technical solution provides a wafer-level wrapped bump packaging structure. The top surface and side surfaces of the non-ferrous metal inner bumps are completely wrapped and sealed by a fully wrapped inert metal layer, which plays a role in fixing and protecting the non-ferrous metal inner bumps, avoids the oxidation of the non-ferrous metal inner bumps, and increases the service life of the non-ferrous metal inner bumps; it can effectively solve the above problems.

[0007] The utility model is realized through the following technical solutions:

[0008] A wafer-level wrapped bump packaging structure includes a bare wafer structure, and a plurality of pad bases are fixedly embedded on the top surface of the bare wafer structure; non-ferrous metal inner bumps are arranged on the upper side of the pad bases, and a fully wrapped inert metal layer is fixed outside the non-ferrous metal inner bumps.

[0009] Furthermore, the thickness of the fully wrapped inert metal layer is greater than or equal to 1.5 microns.

[0010] Further, the fully encapsulated inert metal layer is made of inert noble metal elements and is fixed on the outer surface layer including the side surface of the non-ferrous metal inner bump through electroplating or chemical plating processes.

[0011] Further, the inert noble metal element can be the gold (Au) element.

[0012] Further, the fully encapsulated inert metal layer is formed by electrochemically depositing non-ferrous metal Au atoms into the gap formed between the non-ferrous metal inner bump and the photoresist. The gold ions gradually grow in the gap and form an organic whole with the surface layer of the non-ferrous metal inner bump through the electroplating solution and the positive and negative electrodes of the power supply, thus obtaining the fully encapsulated inert metal layer.

[0013] Further, the non-ferrous metal inner bump is formed by electrochemically depositing non-ferrous metal Cu atoms into the openings of the photoresist. The copper ions gradually grow in the PR openings and form an organic whole with the top layer of the seed layer through the electroplating solution and the positive and negative electrodes of the power supply, thus obtaining the non-ferrous metal inner bump.

[0014] Further, a seed layer is provided between the pad base and the non-ferrous metal inner bump.

[0015] Further, the seed layer is selected from titanium (Ti), copper (Cu), titanium tungsten (TiW), gold (Au), or various alloy metals.

[0016] Further, the seed layer includes a first seed layer connected to the bottom layer of the non-ferrous metal bump and a second seed layer fixed to the top layer of the pad base. The first seed layer and the second seed layer are fixed on the upper layer of the pad base by sputtering.

[0017] Further, the non-ferrous metal bump and the first seed layer are made of the same metal material.

[0018] Further, the bare wafer structure includes a substrate provided at the bottommost layer, and a plurality of pad bases are fixed at designated positions on the top surface of the substrate; a protective layer is provided between the pad bases on the top surface of the substrate, and the protective layer extends to the edges of the pad bases, forming a pad base embedded structure.

[0019] Advantageous Effects

[0020] A wafer-level encapsulated bump packaging structure proposed by the present utility model has the following advantageous effects as compared with the prior art:

[0021] (1) The utility model fully wraps and seals the top surface and side surface of the non-ferrous metal inner bump through a fully enclosed inert metal layer, which plays a role in fixing and protecting the non-ferrous metal inner bump, avoids the oxidation of the non-ferrous metal inner bump, and increases the service life of the non-ferrous metal inner bump; at the same time, it also solves the problem that in the prior art, during the subsequent etching operation of the upper and lower structure packaging, the exposed parts on the side of the bumps made of non-ferrous metals Cu and Ni are affected by etching and holes appear, resulting in unstable morphology and causing problems with pressure difference stability. The utility model not only obtains a low-cost bump packaging structure, but also improves the reliability and stability of the low-cost bump packaging.

[0022] (2) The utility model uses non-ferrous metal Cu to make the non-ferrous metal inner bump, reduces the use of precious metal Au, reduces the manufacturing cost of the bump, and solves the problem of high bump packaging cost in the prior art. It is fixed on the surface layer of the non-ferrous metal inner bump by electroplating or chemical plating to wrap and fix the non-ferrous metal inner bump, improves the stability of the bump, and can effectively solve the problem of structural differences between the gold cap and the underlying metal in the prior art. Description of the Drawings

[0023] Figure 1 Schematic diagram of the input / output contact as a pure Au gold bump in the background technology.

[0024] Figure 2 Schematic diagram of the IC package bump using a copper-nickel-gold combination instead of pure gold in the background technology.

[0025] Figure 3 Schematic diagram of the physical object photographed by the lens of a microscope in Example 1.

[0026] Figure 4 Schematic diagram of the overall structure in Example 1.

[0027] Figure 5 Schematic diagram of the overall structure in Example 3.

[0028] Figure 6 For Figure 5 Enlarged schematic diagram of part A in

[0029] Figure 7 Schematic diagram of the structure in Example 3.

[0030] Figure 8 Schematic diagram of the operating principle of step 1 in the manufacturing method.

[0031] Figure 9 Result diagram obtained after the operation of step 1 in the manufacturing method.

[0032] Figure 10 Schematic diagram of the operating principle of step 2 in the manufacturing method.

[0033] Figure 11 It is the result diagram obtained after the operation in Step 2 of the manufacturing method.

[0034] Figure 12 It is the schematic diagram of the operation process in Step 3 of the manufacturing method.

[0035] Figure 13 It is the operation principle diagram of Step 3 of the manufacturing method.

[0036] Figure 14 It is the result diagram obtained after the operation in Step 3 of the manufacturing method.

[0037] Figure 15 It is the operation principle diagram of Step 4 of the manufacturing method.

[0038] Figure 16 It is the result diagram obtained after the operation in Step 4 of the manufacturing method.

[0039] Figure 17 It is the result diagram obtained after the operation in Step 5 of the manufacturing method.

[0040] Figure 18 It is the result diagram obtained after the operation in Step 6 of the manufacturing method.

[0041] Figure 19 It is the Figure 18 physical diagram of

[0042] Figure 20 It is the result diagram obtained after the operation in Step 8 of the manufacturing method.

[0043] Figure 21 It is the result diagram obtained after the operation in Step 9 of the manufacturing method.

[0044] Figure 22 It is the schematic diagram of the states before and after the operation in Step P2 of the manufacturing method.

[0045] Figure 23 It is the scatter plot of the gold volume saving ratio and the package electroplating of the present utility model.

[0046] Figure 24 It is the test data diagram of the relationship between the thickness and hardness of different package metal layers of the present utility model.

[0047] Figure 25 It is the scatter plot of the conversion hardness and the package electroplating of the present utility model.

[0048] Figure 26 It is the scatter plot of the reliability test of the present utility model.

[0049] Figure 27 It is the data diagram of the stability test of the present utility model.

[0050] Figure 28 This is a scatter plot of the stability test of the present utility model.

[0051] Reference numerals in the drawings: 1 - bare wafer structure, 11 - substrate, 12 - pad base, 13 - protective layer, 2 - non-ferrous metal inner bump, 3 - fully encapsulated inert metal layer, 4 - seed layer, 41 - seed layer one, 42 - seed layer two. Detailed implementation manners

[0052] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. The described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Without departing from the design concept of the present utility model, various modifications and improvements made by those of ordinary skill in the art to the technical solutions of the present utility model shall fall within the protection scope of the present utility model.

[0053] Embodiment 1:

[0054] As Figures 3 to 4 shown, a wafer-level encapsulated bump structure includes a bare wafer structure. The bare wafer structure includes a substrate disposed at the bottommost layer, and a plurality of pad bases are fixedly arranged at designated positions on the top surface of the substrate; a protective layer is disposed between the pad bases on the top surface of the substrate, and the protective layer extends to the edge of the pad base to form a pad base embedded structure.

[0055] A non-ferrous metal inner bump is provided on the upper side of the pad base, and a fully encapsulated inert metal layer is fixedly arranged outside the non-ferrous metal inner bump.

[0056] In this embodiment, the non-ferrous metal inner bump is formed by electrochemically depositing non-ferrous metal Cu atoms into the openings of the photoresist. The copper ions gradually grow in the PR opening and form an organic whole with the top layer of the seed layer through the electroplating solution and the positive and negative electrodes of the power supply to obtain the non-ferrous metal inner bump.

[0057] The thickness of the fully encapsulated inert metal layer is greater than or equal to 1.5 microns. The fully encapsulated inert metal layer uses the gold Au element and is fixed on the outer surface layer including the side surface of the non-ferrous metal inner bump through electroplating or chemical plating processes.

[0058] In this embodiment, the fully encapsulated inert metal layer is formed by electrochemically depositing non-ferrous metal Au atoms into the gap formed between the non-ferrous metal inner bump and the photoresist. The gold ions gradually grow in the gap and form an organic whole with the surface layer of the non-ferrous metal inner bump through the electroplating solution and the positive and negative electrodes of the power supply to obtain the fully encapsulated inert metal layer.

[0059] The top surface and side surfaces of the non-ferrous metal inner bumps are fully enclosed and sealed by a fully wrapped inert metal layer, which plays a role in fixing and protecting the non-ferrous metal inner bumps, avoiding the oxidation of the non-ferrous metal inner bumps, and increasing the service life of the non-ferrous metal inner bumps; at the same time, it also solves the problem that in the prior art, during the subsequent etching operation of the upper and lower structure packaging, the exposed parts on the side of the bumps made of non-ferrous metals Cu and Ni are affected by etching and holes appear, resulting in unstable morphology and causing problems with pressure difference stability. This embodiment not only obtains a bump packaging structure with low cost, but also improves the reliability, gold and stability of the low-cost bump packaging.

[0060] Embodiment 2:

[0061] On the basis of Embodiment 1, a seed layer can also be provided between the pad base and the non-ferrous metal inner bump. The seed layer can be any one of metals such as titanium Ti, copper Cu, tungsten Tiw, gold Au, etc., or it can also be an alloy metal formed by two or more metals.

[0062] The setting of the seed layer can effectively increase the bonding force between the pad base and the non-ferrous metal inner bump.

[0063] Embodiment 3:

[0064] As Figures 5 to 6 shown, on the basis of Embodiment 2, the seed layer is further refined. The seed layer includes a first seed layer connected to the bottom layer of the non-ferrous metal bump and a second seed layer fixed to the top layer of the pad base. The first seed layer and the second seed layer are fixed on the upper layer of the pad base by sputtering.

[0065] The first seed layer and the second seed layer can be any one of metals such as titanium Ti, copper Cu, tungsten Tiw, gold Au, etc., or it can also be an alloy metal formed by two or more metals. However, it is best for the first seed layer to use the same metal material as the non-ferrous metal bump. As Figure 7 shown. Figure 7 In [reference], the color of the first seed layer is the same as that of the inner bump, indicating that the same metal material is used for the two parts.

[0066] When the first seed layer uses the same metal material as the non-ferrous metal bump, the bonding force between the seed layer and the non-ferrous metal inner bump can be further increased.

[0067] Manufacturing method:

[0068] A forming process of a wafer-level wrapped bump packaging structure for manufacturing a wafer-level wrapped bump packaging structure of the above Embodiments 1 to 3. The specific process flow includes:

[0069] Step 1: Perform sputtering on the wafer surface to obtain a seed layer covering the wafer surface; the specific operation method is:

[0070] As Figure 8 shown, in a vacuum environment, target materials of different metals (according to requirements) are placed in the cavity, and the object to be plated (wafer) is placed in the vacuum cavity, corresponding to different positive and negative electrodes respectively. Under the action of high voltage, an inert gas is simultaneously introduced. Plasma is generated under the action of high voltage, continuously bombarding the target material so that the atoms in the target material obtain energy and collide and fly out. The target atoms fly towards the object to be plated and fall to start the nucleation and film formation process and continue continuously, forming the seed layer two.

[0071] Then, the second raw material for the thickness of the seed layer is sputtered to obtain the seed layer one. This raw material can select various alloy metals such as Ti, Cu, Tiw, Au, etc. In this embodiment, Cu is selected. According to different sputtering requirements of the seed layer, the corresponding sputtering time is controlled.

[0072] Parameters: The parameters mainly control the Ar gas flow rate, power and time. In this embodiment, the Ar gas flow rate is controlled at about 80 sccm and adjusted according to different machine performances. The control parameters for Ti and Cu are as follows:

[0073] Step Target Time(sec) Power(W) Ar(sccm) 1 Ti1 75 6800 80.0 2 Cu1 56 8600 80.0

[0074] The thickness of the seed layer can be selected according to different process conditions. In this embodiment, Ti is 0.1 um and Cu is 0.3 um are selected; the effects as Figure 9 shown are obtained.

[0075] Step 2: Coat a layer of resin glue that can be opened by exposure on the upper side of the seed layer on the wafer surface. The thickness of the resin glue coating is greater than the planned height of the non-ferrous metal inner bumps; the specific operation steps are as follows:

[0076] As Figure 10 shown, coat a layer of photoresist on the surface of the seed layer of the wafer, then through soft baking, evaporate and remove the PR component in the remaining solvent to relieve stress; finally cool down to make the wafer that has expanded after soft baking release stress and return to its original state.

[0077] The photoresist can select resin glue, positive glue or negative glue. In this embodiment, resin glue is selected. Because the resin glue contains a photosensitizer, different light exposure position conditions can be used to open a suitable opening. Coating a removable resin glue on the wafer is to open different openings under subsequent light exposure conditions.

[0078] Environment: Normal temperature environment; Parameters: Mainly use the ratio of rotation speed and time to obtain the thickness.

[0079] Stop Range 200 RPM Step Time(sec) <![CDATA[Rot Spd (rpm)]]> 1 4.0 10 2 5.0 10 3 30.0 200 4 10.0 500 5 10.0 1000 6 20.0 3150

[0080] Final thickness of the resin glue: Generally, the PR thickness can be made from 1 to 300 um; in this design, the PR thickness can be adjusted according to different chip sizes. The PR thickness in this embodiment is 20 um. Finally, Figure 11 is obtained.

[0081] Step 3: After coating is completed, exposure and development are carried out to obtain a PR opening consistent with the size of the inner bump; the specific operation method is as follows:

[0082] Due to the penetration ability of light with different wavelengths, the photosensitizer in the photoresist is directly or indirectly broken, forming different acid and alkali resistance capabilities in the exposed and unexposed areas. Then, through an alkaline developer, the mask pattern can be transferred to the photoresist, such as Figure 12 and ​ shown.

[0083] In different areas of the chip, according to requirements, the resin glue is opened at the specified position to form a set shape. Utilizing the properties of different photosensitizers in the resin glue, it is broken to form exposed and unexposed areas with different acid and alkali resistance capabilities. Through an alkaline developer, the mask pattern can be transferred to the photoresist to obtain an opening as shown in ​ shown. In this embodiment, the obtained opening is 10*10 um.

[0084] Raw materials: Prepared according to the exposure condition requirements in the existing technology; necessary environment: Different necessary environmental conditions are adopted according to different PR properties; the necessary parameters are shown in the following table:

[0085] ​ ​ ​ 1 -1 1246

[0086] After exposure is completed, it can enter the developer for dissolution, and finally openings of different sizes are formed. The opening area shown in ​ is a 10*10 opening.

[0087] Step 4: Inside the PR opening, non-ferrous metal inner bumps are obtained by electroplating or chemical plating; the specific operation method is as follows:

[0088] After the opening is completed in Step 3, the bump material is made. In the current process flow, generally, electroplating and chemical plating methods can be used. According to different actual use environments, electroplating is generally used for display driving to ensure thickness and stability. The principle of electroplating is mainly to deposit atoms through an electrochemical reaction onto the photoresist opening to form inner metal bumps. The seed layer on the wafer surface, the inner metal bumps grown from the electroplating solution inside the opening, and the positive and negative electrodes of the power supply form an organic whole, such as ​ shown.

[0089] Under the overall action of the wafer, copper plating solution, and anode and cathode, copper ions gradually grow in the PR opening, and the corresponding height is controlled by adjusting the time and current density given by the machine.

[0090] Raw materials: copper plating solution, additives, sulfuric acid, etc.; Ratio: The copper ion control of the copper plating solution is 45 g / L, and the sulfuric acid content is 130 g / L; Parameters: According to different electroplating heights, different electroplating times are adopted. Generally, the environmental parameter for metal electroplating is a general current density of 10 - 15 ASD. According to different electroplating solution systems, the temperature is controlled at about 26 °C. Finally, in the PR opening and the sputtered seed layer, a non-ferrous metal layer grows, such as ​ shown.

[0091] Step 5: Remove the resin glue to obtain the exposed seed layer and the non-ferrous metal internal bump structure; The specific operation method is:

[0092] After the internal metal bumps are completed, the next step of the encapsulation layer metal production needs to be continued. It is necessary to remove the resin glue between the internal metal bumps to prepare for the large-size opening cleaning in the next step. The main raw material is: H202 hydrogen peroxide with a ratio of 13%. The parameters during operation are: temperature, 70 ± 3 °C, time 340 s; Finally, the exposed structure of the internal metal bumps as shown in ​ is formed.

[0093] Step 6: Perform the second coating, coat a photoresist layer between the non-ferrous metal internal bumps on the wafer surface, and the thickness of the photoresist layer is greater than the height of the non-ferrous metal internal bumps; The specific operation method is the same as that in Step 2, and the glue is applied again.

[0094] Step 7: Perform the second exposure and development to obtain a PR opening consistent with the outer dimension of the bump plan, forming a gap between the metal bump and the photoresist layer; The specific operation method is the same as that in Step 3, only the necessary parameters are modified to obtain an opening of 14 * 14 um; The necessary parameters for this step are necessary parameters:

[0095] ​ ​ ​ 1 -2 1476

[0096] Finally, a 2-um gap between the metal bump and the photoresist layer is obtained, as shown in ​ and ​ shown.

[0097] Step 8: Electroplate a noble metal layer in the gap to form a fully encapsulated inert metal layer; If direct Au electroplating cannot be performed, directly go to Step P2. The specific operation method is:

[0098] Use electroplating or electroless plating methods again to electroplate the outer encapsulation noble metal layer. In this embodiment, the noble metal used is gold Au.

[0099] Under the overall action of the wafer, the gold plating solution (or other precious metals, inert metals), and the anode and cathode, metal ions gradually grow in the PR opening. By controlling the time and current density given by the machine, the corresponding height of the metal layer is controlled. Raw materials: copper plating solution, additives, sulfuric acid, etc.; Ratio: The gold ion control of the gold plating solution is 5 g / L, and the PH (6.0) is 5.5 - 6.5; Parameters: According to different electroplating heights / thicknesses, different electroplating times are adopted. The general current density of metal electroplating is generally 0.1 - 1 ASD. According to different electroplating solution systems, the temperature is controlled at about 45 degrees. Finally, a fully encapsulated inert metal layer grows on the PR opening and gap, as well as on the surface layer of the sputtered seed layer and the inner metal bumps, such as ​ shown

[0100] Step 9: Perform the second degumming to remove the resin glue on the upper side of the seed layer on the wafer surface and around the bumps, obtaining the exposed seed layer and the bump structure with a fully encapsulated inert metal layer, as ​ shown; The specific operation method of this step is the same as that of step 5

[0101] Step 10: Perform the etching operation to remove the seed layer between the bumps on the upper side of the wafer surface, obtaining the exposed wafer surface and the bumps with a fully encapsulated inert metal layer as ​ shown, completing the production of the encapsulated bump packaging structure

[0102] The etching step is because after step 9 is completed, in addition to the bump positions, the seed layer in the first step also exists in the remaining positions on the wafer surface, and metal removal is required to achieve the independence of a single chip. Utilizing metal etching technology, the peripheral metal can be effectively removed to obtain the final form of the encapsulated bump

[0103] The raw materials used are metal etching solution + H2O2; Parameters: The etching efficiency is mainly controlled by the etching temperature and time, where the temperature and time are 23 ± 3 °C and 1800 s respectively. The specific time can be adjusted according to the different thicknesses of the seed layer

[0104] Step P2: When performing the operation of step 8, if the capillary effect phenomenon occurs, resulting in the electroplating solution being unable to enter the narrow space for electroplating, then a pre-treatment operation of descum or PLASMA plasma cleaning before gold plating is required

[0105] According to the actual verification effect, due to the relatively narrow gap formed in step 7, the electroplating solution cannot enter the narrow gap space for electroplating due to the capillary effect phenomenon. Therefore, pre-treatment is required, such as ​As shown in the figure. The pretreatment is abbreviated as descum or PLASMA plasma cleaning (also known as plasma). The principle used is the method of plasma bombardment cleaning. After processing products such as existing small holes, dense holes, and blind vias on circuit boards, there are often residual smears or surface burrs need to be removed, so this operation is required to make it smooth and hydrophilic. Therefore, the dry process of plasma cleaning has attracted attention: it is now widely used in the in-hole cleaning process after circuit board drilling. For the internal metal layer, because it is necessary to ensure its stability and non-oxidizability, it is necessary to avoid using oxygen for plasma cleaning, and argon or nitrogen needs to be used. The main control parameters are: low-pressure pressure (250 mtorr), working pressure (300 - 350 mtorr), power (6 - 8 kw), time (10 - 15 min), gas flow rate and ratio (6:2:1).

[0106] To verify the superiority and effectiveness of this solution, the utility model inventor verified through the following experiments and data, specifically:

[0107] Verification of cost:

[0108] Calculated based on the material with length 10 * width 10 * height 10, for the gold consumption with a volume of 10^3, if the exposed type is adopted, generally the top metal layer is about 1 um, but there are extremely low reliability problems and it is not recommended to use.

[0109] If the encapsulated type is adopted, the specific data is shown in Table 1. According to the data in Table 1, the curve graph as shown in the figure can be obtained, and the following conclusions can be drawn: ​ As shown in the figure, and the following conclusions can be obtained:

[0110] If the encapsulated type is adopted and the thickness is 0.1 um, the cost is saved by 94.11% compared with the all-gold bump;

[0111] If the encapsulated type is adopted and the thickness is 0.2 um, the cost is saved by 88.4% compared with the all-gold bump;

[0112] If the encapsulated type is adopted and the thickness is 0.3 um, the cost is saved by 83.0% compared with the all-gold bump;

[0113] If the encapsulated type is adopted and the thickness is 0.4 um, the cost is saved by 77.85% compared with the all-gold bump;

[0114] If the encapsulated type is adopted and the thickness is 1 um, the cost is saved by 72.9% compared with the all-gold bump;

[0115] If the encapsulated type is adopted and the thickness is 2 um, the cost is saved by 21.6% compared with the all-gold bump.

[0116]

[0117] Table 1

[0118] Calculated according to the volume formula, the thinner the thickness of the encapsulated type, the more gold can be saved. However, the following limitations in actual applications also need to be considered:

[0119] ① Dimension standard type: The control of dimensions can be achieved through the control of thickness. As long as the actual dimensions meet the standards, it will not affect the actual thickness.

[0120] ② Hardness compliance: In the backend packaging, there are various packaging types, and basically they need to be mutually pressed together. This requires the surface of the chip to have corresponding hardness, which limits the thickness from being too thin (if it is too thin, it is impossible to control the hardness and perform the pressing).

[0121] Hardness test:

[0122] Press in using a needle. If it is too hard, the indentation is small; if it is too soft, the indentation is large. The obtained data is as shown in ​ and the curve chart is as shown in ​ . Thus, the conclusion can be drawn that the thickness of the fully encapsulated inert metal layer generally needs to reach more than 1.5um to have high stability.

[0123] Reliability test:

[0124] Compared with the traditional chip bump structure, it has the following advantages: the same reliability stability; no difference after reliability testing. The data graph summary is shown in ​ . The data is basically the same; no difference after reliability testing. The data performance is shown in the following table:

[0125]

[0126] Stability test:

[0127] It has better anti-sidewall etching stability compared with the upper and lower structure bumps (the sidewalls of the bumps are exposed), avoiding the instability caused by sidewall etching. The specific data is shown in ​ and the matrix graph is shown in ​ . According to the data analysis, the traditional chip bumps or the sidewall-exposed bump structures of the upper and lower structures are basically negative depressions, while the encapsulated bumps basically maintain an outward expansion state, which can well protect the overall chip state.

[0128] The above embodiments are only used to illustrate the technical concept and features of the present invention, and their purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it accordingly. It should not be used to limit the protection scope of the present invention. Any equivalent transformation or modification made according to the spirit and essence of the present invention should be covered by the present invention.

Claims

1. A wafer-level encapsulated bump packaging structure, comprising a bare wafer structure, and a plurality of pad bases are fixedly embedded on the top surface of the bare wafer structure; characterized in that: Non-ferrous metal inner convex points are provided on the upper side of the pad base, and a fully wrapped inert metal layer is fixed outside the non-ferrous metal inner convex points.

2. The wafer-level encapsulated bump structure according to claim 1, wherein: The thickness of the fully wrapped inert metal layer is greater than or equal to 1.5 micrometers.

3. A wafer-level encapsulated bump packaging structure according to claim 1 or 2, characterized in that: The fully wrapped inert metal layer is made of inert noble metal elements and is fixed on the outer surface layer including the side surface of the non-ferrous metal inner convex points through electroplating or chemical plating processes.

4. The wafer-level encapsulated bump structure according to claim 3, wherein: The inert noble metal elements can be gold (Au) elements.

5. The wafer-level encapsulated bump structure according to claim 4, wherein: The fully wrapped inert metal layer is formed by electrochemically depositing non-ferrous metal Au atoms into the gap formed between the non-ferrous metal inner convex points and the photoresist. The gold ions gradually grow in the gap and form an organic whole with the surface layer of the non-ferrous metal inner convex points through the electroplating solution and the positive and negative electrodes of the power supply, resulting in the fully wrapped inert metal layer.

6. The wafer-level encapsulated bump structure according to claim 1, wherein: The non-ferrous metal inner convex points are formed by electrochemically depositing non-ferrous metal Cu atoms into the openings of the photoresist. The copper ions gradually grow in the PR openings and form an organic whole with the top layer of the seed layer through the electroplating solution and the positive and negative electrodes of the power supply, resulting in the non-ferrous metal inner convex points.

7. The wafer-level encapsulated bump structure according to claim 1, wherein: A seed layer is provided between the pad base and the non-ferrous metal inner convex points.

8. The wafer-level encapsulated bump structure according to claim 7, wherein: The seed layer is selected from titanium (Ti), copper (Cu), tungsten titanium (Tiw), gold (Au), or various alloy metals.

9. A wafer-level encapsulated bump packaging structure according to claim 7 or 8, characterized in that: The seed layer includes a first seed layer connected to the bottom layer of the non-ferrous metal convex points and a second seed layer fixed to the top layer of the pad base. The first seed layer and the second seed layer are fixed on the upper layer of the pad base by sputtering.

10. A wafer-level encapsulated bump packaging structure according to claim 9, wherein: The non-ferrous metal convex points and the first seed layer are made of the same metal material.

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