Multi-power-domain electrostatic discharge protection circuit and chip

Abstract

The utility model discloses a multi-power-domain electrostatic discharge protection circuit and a chip. The electrostatic discharge protection circuit comprises a signal grounding end, a power grounding end and at least one positive power connecting end. Wherein a plurality of electrostatic discharge protection units which are sequentially connected in series are arranged between the signal grounding end and the power supply grounding end; the positive power supply connecting end is connected with a first node, and the first node is located on a connecting circuit between any two adjacent electrostatic discharge protection units between the signal grounding end and the power supply grounding end. In the technical scheme of the utility model, the first node is located on the connection circuit between any two adjacent electrostatic discharge protection units between the signal grounding end and the power supply grounding end, so that the electrostatic discharge protection units between the signal grounding end and the power supply grounding end are multiplexed, the design number of the electrostatic discharge protection units is reduced, and the cost is reduced. Therefore, the area of the chip is reduced, and the manufacturing cost of the chip is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to an electrostatic discharge protection circuit and a chip with multiple power domains. Background Art

[0002] When designing a chip, electrostatic discharge (ESD) protection is required in each power domain, and electrostatic discharge protection is also required between different power domains.

[0003] Currently, when designing the electrostatic discharge protection for the power domains in a chip, an electrostatic discharge protection unit needs to be designed for each power domain, and electrostatic discharge protection units also need to be designed between different power domains. Among them, when the chip is designed with a high-voltage process, multiple electrostatic discharge protection units need to be set between each power domain and between different power domains, and the electrostatic discharge protection units in each power domain or between different power domains only protect against electrostatic discharge in that area, which increases the area of the chip and also increases the manufacturing cost of the chip.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Utility Model

[0005] In view of the above deficiencies of the existing technology, the purpose of the present utility model is to provide an electrostatic discharge protection circuit and a chip with multiple power domains, so as to solve the problem in the existing technology that the electrostatic discharge protection units in each power domain or between different power domains only protect against electrostatic discharge in that area, which increases the area of the chip and also increases the manufacturing cost of the chip.

[0006] The technical solution adopted by the present utility model to solve its technical problems is: to provide an electrostatic discharge protection circuit with multiple power domains, including: a signal ground terminal, a power ground terminal, and at least one positive power connection terminal; wherein:

[0007] A plurality of electrostatic discharge protection units connected in series in sequence are arranged between the signal ground terminal and the power ground terminal;

[0008] The positive power connection terminal is connected to a first node, and the first node is located on the connection path between any two adjacent electrostatic discharge protection units between the signal ground terminal and the power ground terminal.

[0009] In a further setting of the present utility model, a plurality of electrostatic discharge protection units 40 connected in sequence are arranged on the connection path between the positive power connection terminal and the first node.

[0010] In a further setting of the present utility model, the electrostatic discharge protection unit is a low-voltage electrostatic discharge protection device.

[0011] Further setting of the present utility model, the low-voltage electrostatic discharge protection device includes an electrostatic discharge protection diode or a switching tube.

[0012] Further setting of the present utility model, the switching tube is a low-voltage isolation type N-MOS tube.

[0013] Further setting of the present utility model, the switching tube is a low-voltage isolation type P-MOS tube.

[0014] Further setting of the present utility model, the high potential of the low-voltage electrostatic discharge protection device between the first node and the power supply ground terminal is close to the first node, and the high potential of the low-voltage electrostatic protection device between the first node and the signal ground terminal is close to the first node.

[0015] The present utility model also provides a chip applying the electrostatic discharge protection circuit of a multi-power supply domain as described above. The chip includes: a signal ground terminal, a power supply ground terminal, and at least one positive power supply connection terminal; wherein:

[0016] A plurality of electrostatic discharge protection units connected in series in sequence are arranged between the signal ground terminal and the power supply ground terminal, and the positive power supply connection terminal is connected to the connection path between any two adjacent electrostatic discharge protection units among the plurality of electrostatic discharge protection units connected in sequence.

[0017] Beneficial effects:

[0018] The present utility model discloses an electrostatic discharge protection circuit and a chip of a multi-power supply domain. The electrostatic discharge protection circuit includes: a signal ground terminal, a power supply ground terminal, and at least one positive power supply connection terminal; wherein: a plurality of electrostatic discharge protection units connected in series in sequence are arranged between the signal ground terminal and the power supply ground terminal; the positive power supply connection terminal is connected to a first node, and the first node is located on the connection path between any two adjacent electrostatic discharge protection units between the signal ground terminal and the power supply ground terminal. In the technical solution of the present utility model, since the first node is located on the connection path between any two adjacent electrostatic discharge protection units between the signal ground terminal and the power supply ground terminal, the electrostatic discharge protection units between the signal ground terminal and the power supply ground terminal are reused, reducing the designed number of electrostatic discharge protection units, thereby reducing the chip area and simultaneously reducing the manufacturing cost of the chip. Description of the drawings

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for describing the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0020] Figure 1 It is a schematic diagram of the electrostatic discharge protection circuit for a multi-power domain when the present invention is provided with a positive power connection terminal.

[0021] Figure 2 It is a schematic diagram of the electrostatic discharge protection circuit for a multi-power domain when the present invention is provided with two positive power connection terminals in one embodiment.

[0022] Figure 3 It is an electrostatic discharge protection circuit for a power domain built only with electrostatic discharge diodes when the present invention is provided with a positive power connection terminal in one embodiment.

[0023] Figure 4 It is an electrostatic discharge protection circuit for a power domain built only with electrostatic discharge diodes when the present invention is provided with two positive power connection terminals in one embodiment.

[0024] Figure 5 It is an electrostatic discharge protection circuit for a power domain built only with electrostatic discharge diodes when the prior art is provided with a positive power connection terminal.

[0025] Figure 6 It is an electrostatic discharge protection circuit for a power domain built only with electrostatic discharge diodes when the prior art is provided with two positive power connection terminals.

[0026] Marks in the drawings: 10, positive power connection terminal; 20, power ground terminal; 30, signal ground terminal; 40, electrostatic discharge protection unit; 50, first node. Detailed Embodiments

[0027] To have a clearer understanding of the technical features, objectives, and effects of the present invention, the detailed embodiments of the present invention will now be described in detail with reference to the drawings. In the following description, it should be understood that the orientation or positional relationships indicated by "front", "rear", "upper", "lower", "left", "right", "longitudinal", "transverse", "vertical", "horizontal", "top", "bottom", "inner", "outer", "head", "tail", etc. are based on the orientation or positional relationships shown in the drawings, and are constructed and operated in a specific orientation. This is only for the convenience of describing the technical solution and does not indicate that the device or element referred to must have a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0028] When designing a chip, electrostatic discharge (ESD) protection is required in each power domain, and also between different power domains.

[0029] As Figure 5 shown, the circuit structure used for ESD protection design of an integrated circuit with one positive power connection terminal (VCC in Figure 5 ), one signal ground terminal, and one power ground terminal in the prior art is presented. It can be seen from Figure 5 that an ESD protection unit is provided between the positive power connection terminal and the signal ground terminal, an ESD protection unit is provided between the positive power connection terminal and the power ground terminal, and an ESD protection unit is provided between the signal ground terminal and the power ground terminal.

[0030] Specifically, as Figure 5 shown, several sequentially connected ESD protection units are provided between the positive power connection terminal and the signal ground terminal, several sequentially connected ESD protection units are provided between the positive power connection terminal and the power ground terminal, and several sequentially connected ESD protection units are provided between the signal ground terminal and the power ground terminal. Figure 5 One ESD diode in

[0031] As Figure 6 shown, the circuit structure used for ESD protection design of an integrated circuit with two positive power connection terminals (VCC represents one positive power connection terminal, and VM represents the other positive power connection terminal), one signal ground terminal, and one power ground terminal in the prior art is presented. It can be seen from Figure 6 that several sequentially connected ESD protection units are provided between the signal ground terminal and the power ground terminal, several sequentially connected ESD protection units are provided between VCC and the power ground terminal, several sequentially connected ESD protection units are provided between VCC and the signal ground terminal, several sequentially connected ESD protection units are provided between VM and the power ground terminal, and several sequentially connected ESD protection units are provided between VM and the signal ground terminal. Figure 6 One ESD diode in

[0032] Currently, when a chip is designed using a high-voltage process, multiple ESD protection units need to be provided both within and between each power domain, and the ESD protection units within each power domain or between different power domains only protect that area, resulting in an increase in the chip area and also an increase in the chip manufacturing cost.

[0033] Based on the above problems, as Figure 1 、Figure 2 As shown, the present invention provides an electrostatic discharge protection circuit for multiple power domains, which may include a signal ground terminal 30, a power ground terminal 20 and at least one positive power connection terminal 10; wherein, a plurality of electrostatic discharge protection units 40 connected in series are arranged between the signal ground terminal 30 and the power ground terminal 20; the positive power connection terminal 10 is connected to a first node 50, and the first node 50 is located on the connection path between any two adjacent electrostatic discharge protection units 40 between the signal ground terminal 30 and the power ground terminal 20.

[0034] In this embodiment, the positive power connection terminal 10 is connected to the first node 50. Therefore, a plurality of electrostatic discharge protection units 40 connected in series between the power ground terminal 20 and the signal ground terminal 30 provide electrostatic discharge protection between the positive power connection terminal 10 and the signal ground terminal 30 (electrostatic discharge protection unit 40 between the positive power connection terminal 10 and the signal ground terminal 30), and also provide electrostatic discharge protection between the positive power connection terminal 10 and the power ground terminal 20 (electrostatic discharge protection between the positive power connection terminal 10 and the power ground terminal 20). Furthermore, electrostatic discharge protection is provided between the power ground terminal 20 and the signal ground terminal 30 (electrostatic discharge protection unit 40 between the power ground terminal 20 and the signal ground terminal 30).

[0035] It can be seen that since the first node 50 is located on the connection path between any two adjacent electrostatic discharge protection units 40 between the signal ground terminal 30 and the power ground terminal 20, the electrostatic discharge protection units 40 between the signal ground terminal 30 and the power ground terminal 20 are reused, thereby reducing the design number of electrostatic discharge protection units 40, thereby reducing the chip area and reducing the manufacturing cost of the chip.

[0036] In this embodiment, when the electrostatic discharge protection unit 40 is set, it is necessary to base it on the trigger voltage of the electrostatic discharge protection unit 40, the maintenance voltage of the electrostatic discharge protection unit 40, the maximum operating voltage of the chip, and the maximum withstand voltage of the internal circuit (the number of electrostatic discharge protection units 40 set can ensure that the normal operation of the chip is not affected during normal operation, and can play a protective role when static electricity is present).

[0037] For example, if the maximum operating voltage between a positive power connection terminal 10 and a power ground terminal 20 is 20V and the maximum withstand voltage of the internal circuit is 32V, then when an ESD protection unit 40 is provided between the positive power connection terminal 10 and the power ground terminal 20, assuming that the trigger voltage of the ESD protection unit 40 is 7V and the maintenance voltage is 6V, four ESD protection units 40 need to be provided between the positive power connection terminal 10 and the power ground terminal 20 (32V is greater than 28V (4*7V), and 24V (4*6V) is greater than 20V).

[0038] Further, a plurality of sequentially connected electrostatic discharge protection units 40 are provided on the connection path between the positive power supply connection terminal 10 and the first node 50.

[0039] In this embodiment, a plurality of sequentially connected electrostatic discharge protection units 40 can be provided between the positive power supply connection terminal 10 and the first node 50, so that when the electrostatic discharge protection units 40 between the first node 50 and the signal ground terminal 30 alone cannot meet the electrostatic discharge protection requirements between the positive power supply connection terminal 10 and the signal ground terminal 30, or when the electrostatic discharge protection units 40 between the first node 50 and the power ground terminal 20 alone cannot meet the electrostatic discharge protection requirements between the positive power supply connection terminal 10 and the power ground terminal 20, the electrostatic discharge protection requirements between the positive power supply connection terminal 10 and the signal ground terminal 30, and the electrostatic discharge protection requirements between the positive power supply connection terminal 10 and the power ground terminal 20 can be met by providing electrostatic discharge protection units 40 between the positive power supply connection terminal 10 and the first node 50.

[0040] As Figure 1 shown, it is the circuit structure adopted in the electrostatic discharge protection design of an integrated circuit with one positive power supply connection terminal 10, one signal ground terminal 30, and one power ground terminal 20. Among them, a plurality of sequentially connected electrostatic discharge protection units 40 are provided between the signal ground terminal 30 and the power ground terminal 20, and a plurality of sequentially connected electrostatic discharge protection units 40 are provided between the positive power supply connection terminal 10 and the first node 50. It can be seen from Figure 1 this that the electrostatic discharge protection units 40 between the positive power supply connection terminal 10 and the first node 50 and the electrostatic discharge protection units 40 between the first node 50 and the signal ground terminal 30 perform electrostatic discharge protection between the positive power supply connection terminal 10 and the signal ground terminal 30, and the electrostatic discharge protection units 40 between the positive power supply connection terminal 10 and the first node 50 and the electrostatic discharge protection units 40 between the first node 50 and the power ground terminal 20 perform electrostatic discharge protection between the positive power supply connection terminal 10 and the power ground terminal 20.

[0041] In addition, when there are multiple positive power supply connection terminals 10, the method of providing electrostatic discharge protection units 40 on the connection path between the positive power supply connection terminal 10 and the first node 50 can also perform electrostatic discharge protection between the multiple positive power supply connection terminals 10.

[0042] As Figure 2As shown, it is the circuit structure adopted in the electrostatic discharge protection design of an integrated circuit with two positive power connection terminals 10, one signal ground terminal 30, and one power ground terminal 20. Among them, several electrostatic discharge protection units 40 connected in series are arranged between the signal ground terminal 30 and the power ground terminal 20. Several electrostatic discharge protection units 40 connected in series are arranged between one positive power connection terminal 10 and the first node 50. Several electrostatic discharge protection units 40 connected in series are arranged between the other positive power connection terminal 10 and the first node 50. The specific logic of the electrostatic discharge protection between this one positive power connection terminal 10 and the power ground terminal 20 and the signal ground terminal 30 can refer to the above-mentioned logic of the electrostatic discharge protection between one positive power connection terminal 10, one signal ground terminal 30, and one power ground terminal 20. The specific logic of the electrostatic discharge protection between the other positive power connection terminal 10 and the power ground terminal 20 and the signal ground terminal 30 can refer to the above-mentioned logic of the electrostatic discharge protection between one positive power connection terminal 10, one signal ground terminal 30, and one power ground terminal 20. From Figure 2 it can be seen that the electrostatic discharge protection units 40 between this one positive power connection terminal 10 and the first node 50 and the electrostatic discharge protection units 40 between the other positive power connection terminal 10 and the first node 50 also provide electrostatic discharge protection between this one positive power connection terminal 10 and the other positive power connection terminal 10.

[0043] In some embodiments, the electrostatic discharge protection unit 40 can be a low-voltage electrostatic discharge protection device.

[0044] Furthermore, the low-voltage electrostatic discharge protection device can include an electrostatic discharge (ESD) diode or a switching transistor.

[0045] When setting the low-voltage electrostatic discharge protection device, it can be set with only an electrostatic discharge diode or a switching transistor as the protection device in an electrostatic discharge protection circuit, or an electrostatic discharge diode and a switching transistor can be used simultaneously as protection devices in a mixed manner (that is, the electrostatic discharge protection circuit is set with a mixture of an electrostatic discharge diode and a switching transistor). Those skilled in the art can set it according to the actual situation and will not be elaborated here.

[0046] Here, it should be noted that this actual situation refers to when determining whether to use only an electrostatic discharge diode or a switching transistor as a protection device or to use both an electrostatic discharge diode and a switching transistor in combination. It is necessary to consider the trigger voltage of the low-voltage electrostatic discharge protection device (electrostatic discharge diode, switching transistor), the holding voltage of the low-voltage electrostatic discharge protection device (electrostatic discharge diode, switching transistor), the maximum operating voltage of the chip, and the maximum withstand voltage of the internal circuit. That is, to ensure that when the chip is operating normally, it does not affect the normal operation of the chip, and it can play a protective role when there is electrostatic discharge.

[0047] In this embodiment, when setting up the electrostatic discharge protection circuit, only an electrostatic discharge diode or a switching transistor can be used, or both an electrostatic discharge diode and a switching transistor can be used in combination as protection devices, which reflects the flexibility of the electrostatic discharge protection circuit.

[0048] Here, it should be noted that the trigger voltage of the electrostatic discharge diode is close to or equal to the holding voltage.

[0049] Furthermore, the switching transistor can be a low-voltage isolated N-MOS transistor. The full English name of the N-MOS transistor is N-Metal-Oxide-Semiconductor, and the full Chinese name is N-channel metal-oxide-semiconductor transistor; it can also be a low-voltage isolated P-MOS transistor. The full English name of the P-MOS transistor is positive channel Metal Oxide Semiconductor, and the full Chinese name is P-channel metal-oxide-semiconductor transistor.

[0050] When setting up the electrostatic discharge protection circuit, whether to choose a low-voltage isolated N-MOS transistor or a low-voltage isolated P-MOS transistor also needs to be determined according to the actual situation.

[0051] Specifically, the trigger voltage of the low-voltage isolated P-MOS transistor is close to or the same as the holding voltage, and the trigger voltage of the low-voltage isolated N-MOS transistor is higher than the holding voltage. When choosing a low-voltage isolated N-MOS transistor, after the electrostatic discharge exceeds the trigger voltage of the low-voltage isolated N-MOS transistor, the low-voltage isolated N-MOS transistor conducts, and the voltage drop across the low-voltage isolated N-MOS transistor will sweep back to the holding voltage. Due to the difference in the trigger voltage between the low-voltage isolated N-MOS transistor and the low-voltage isolated P-MOS transistor, choosing a low-voltage isolated N-MOS transistor can achieve the same protection effect as a low-voltage isolated P-MOS transistor or an electrostatic discharge diode with a smaller area.

[0052] However, when selecting a low-voltage isolation N-MOS transistor, since the holding voltage of the low-voltage isolation N-MOS transistor is low and the trigger voltage is lower than the holding voltage, when multiple low-voltage isolation N-MOS transistors are connected in series, it is not easy to meet the requirement that the sum of the holding voltages is greater than the maximum operating voltage of the chip. At this time, a mixed setting method of low-voltage isolation N-MOS transistors and low-voltage isolation P-MOS transistors can be selected to meet the requirements. Of course, a mixed setting method of low-voltage isolation N-MOS transistors and electrostatic discharge diodes can also be used to meet the requirements, or a mixed setting method of low-voltage isolation N-MOS transistors, electrostatic discharge diodes, and low-voltage isolation P-MOS transistors can be used to meet the requirements.

[0053] For example, the trigger voltage of the low-voltage isolation N-MOS transistor is 9V and the holding voltage is 6V; the trigger voltage and the holding voltage of the low-voltage isolation P-MOS transistor are both 9V; the highest operating voltage between a positive power connection terminal 10 and a power ground terminal 20 is 20V, and the maximum withstand voltage of the internal circuit is 32V. When setting under this background, two low-voltage isolation P-MOS transistors and one low-voltage isolation N-MOS transistor can be set between the positive power connection terminal 10 and the power ground terminal 20. At this time, the sum of the trigger voltages is 9 + 9 + 9 = 27V, and the sum of the holding voltages is 9 + 9 + 6 = 24V, meeting the requirements that the sum of the trigger voltages is less than 32V and greater than 20V, and the sum of the holding voltages is less than 32V and greater than 20V.

[0054] Furthermore, when setting the low-voltage electrostatic discharge device, the high potential of the low-voltage electrostatic discharge protection device between the first node 50 and the power ground terminal 20 is close to the first node 50, and the high potential of the low-voltage electrostatic protection device between the first node 50 and the signal ground terminal 30 is close to the first node 50.

[0055] Specifically, when setting a low-voltage electrostatic discharge protection device between the power ground terminal 20 and the signal ground terminal 30, with the first node 50 as a reference, when the low-voltage electrostatic protection device between the first node 50 and the power ground terminal 20 releases static electricity, the high-potential end is close to the first node 50; when the low-voltage electrostatic discharge protection unit 40 device between the first node 50 and the signal ground terminal 30 releases static electricity, the high-potential end is close to the first node 50.

[0056] Here, it should be noted that the high potential refers to the end with a higher potential on the low-voltage electrostatic protection device when releasing static electricity.

[0057] In this embodiment, the high potential of the low-voltage electrostatic discharge protection device between the first node 50 and the power ground terminal 20 is close to the first node 50, and the high potential of the low-voltage electrostatic protection device between the first node 50 and the signal ground terminal 30 is close to the first node 50, so that several series-connected low-voltage electrostatic protection devices between the power ground terminal 20 and the signal ground terminal 30 are equivalent to the sum of the forward voltage drop and reverse breakdown voltage of a diode.

[0058] To further illustrate the specific application of this electrostatic discharge protection circuit, the following example is used for illustration.

[0059] Example 1: As Figure 3 shown, it is an electrostatic discharge protection circuit only set with electrostatic discharge diodes. In Figure 3 , between the positive power connection terminal 10 (VCC in Figure 3 represents the positive power connection terminal 10) and the first node 50, two electrostatic discharge diodes are connected in series in sequence. Among them, the negative electrode of the electrostatic discharge diode between the positive power connection terminal 10 and the first node 50 is close to the positive power connection terminal 10; between the signal ground terminal 30 (COM in Figure 3 represents the signal ground terminal 30) and the power ground terminal 20 (GND in Figure 3 represents the signal ground terminal 30), two electrostatic discharge diodes are set. Among them, the negative electrode of the electrostatic discharge diode between the signal ground terminal 30 and the power ground terminal 20 is close to the first node 50.

[0060] In this example, the three electrostatic discharge diodes between the positive power connection terminal 10 and the power ground terminal 20 provide electrostatic discharge protection between the positive power connection terminal 10 and the power ground terminal 20. The three electrostatic discharge diodes between the positive power connection terminal 10 and the signal ground terminal 30 provide electrostatic discharge protection between the positive power connection terminal 10 and the signal ground terminal 30. The two electrostatic discharge diodes between the signal ground terminal 30 and the power ground terminal 20 provide electrostatic discharge protection between the signal ground terminal 30 and the power ground terminal 20.

[0061] Example 2: In an integrated circuit with one positive power connection terminal 10, one signal ground terminal 30, and one power ground terminal 20, only low-voltage isolation type N-MOS transistors are set. Two series-connected low-voltage isolation type N-MOS transistors are set between the power ground terminal 20 and the signal ground terminal 30. Three series-connected low-voltage isolation type N-MOS transistors are set on the connection path between the positive power connection terminal 10 and the first node 50 (on the connection path of the two low-voltage isolation type N-MOS transistors).

[0062] When making specific connections, when a low-voltage isolation type N-MOS transistor is arranged between the positive power connection terminal 10 and the first node 50, the drain of the low-voltage isolation type N-MOS transistor connected to the positive power connection terminal 10 is connected to the positive power connection terminal 10. When two low-voltage isolation type N-MOS transistors are connected, the drain of one low-voltage isolation type N-MOS transistor among the two low-voltage isolation type N-MOS transistors is connected to the source of the other low-voltage isolation type N-MOS transistor, and the source of the low-voltage isolation type N-MOS transistor connected to the first node 50 is connected to the first node 50; when a low-voltage isolation type N-MOS transistor is arranged between the signal ground terminal 30 and the power ground terminal 20, the source of one low-voltage isolation type N-MOS transistor is connected to the power ground terminal 20 and the drain is connected to the drain of the other low-voltage isolation type N-MOS transistor, and the source of the other low-voltage isolation type N-MOS transistor is connected to the signal ground terminal 30; wherein, the ISO port in each low-voltage isolation type N-MOS transistor can be left floating or connected to the drain of the low-voltage isolation type N-MOS transistor to which it belongs. The ISO port refers to the isolation well potential of the low-voltage isolation type N-MOS transistor, and the source of each low-voltage isolation type N-MOS transistor is connected to the gate.

[0063] In this example, when performing electrostatic discharge protection between the positive power connection terminal 10 and the signal ground terminal 30, between the positive power connection terminal 10 and the power ground terminal 20, and between the signal ground terminal 30 and the power ground terminal 20, the above Example 1 can be referred to. The only difference is that the low-voltage electrostatic discharge protection device is a low-voltage isolation type N-MOS transistor, which will not be elaborated here.

[0064] Example 3: In an integrated circuit having one positive power connection terminal 10, one signal ground terminal 30, and one power ground terminal 20, only low-voltage isolation type P-MOS transistors are arranged. Two series-connected low-voltage isolation type P-MOS transistors are arranged between the power ground terminal 20 and the signal ground terminal 30, and three series-connected low-voltage isolation type P-MOS transistors are arranged on the connection path between the positive power connection terminal 10 and the first node 50 (on the connection path of the two low-voltage isolation type P-MOS transistors).

[0065] When making specific connections, when a low-voltage isolation P-MOS transistor is set between the positive power supply connection terminal 10 and the first node 50, the source of the low-voltage isolation P-MOS transistor connected to the positive power supply connection terminal 10 is connected to the positive power supply connection terminal 10. When two low-voltage isolation P-MOS transistors are connected, the source of one low-voltage isolation P-MOS transistor among the two low-voltage isolation P-MOS transistors is connected to the drain of the other low-voltage isolation P-MOS transistor, and the drain of the low-voltage isolation P-MOS transistor connected to the first node 50 is connected to the first node 50; when a low-voltage isolation P-MOS transistor is set between the signal ground terminal 30 and the power supply ground terminal 20, the drain of one low-voltage isolation P-MOS transistor is connected to the power supply ground terminal 20 and the source is connected to the source of the other low-voltage isolation P-MOS transistor, and the drain of the other low-voltage isolation P-MOS transistor is connected to the signal ground terminal 30, and the source of each low-voltage isolation P-MOS transistor is connected to the gate.

[0066] In this example, when performing electrostatic discharge protection between the positive power supply connection terminal 10 and the signal ground terminal 30, between the positive power supply connection terminal 10 and the power supply ground terminal 20, and between the signal ground terminal 30 and the power supply ground terminal 20, the above Example 1 can be referred to. The only difference is that the low-voltage electrostatic discharge protection device is a low-voltage isolation P-MOS transistor, which will not be elaborated here.

[0067] Example 4: When low-voltage isolation N-MOS transistors and low-voltage isolation P-MOS transistors are mixed and set in an integrated circuit having one positive power supply connection terminal 10, one signal ground terminal 30, and one power supply ground terminal 20 (two low-voltage isolation P-MOS transistors and three low-voltage isolation N-MOS transistors are set).

[0068] When specifically connecting, on the connection path between the positive power supply connection terminal 10 and the first node 50, two low-voltage isolation P-MOS transistors and one low-voltage isolation N-MOS transistor are provided. Among them, the source of one low-voltage isolation P-MOS transistor is connected to the positive power supply connection terminal 10, the drain of this low-voltage isolation P-MOS transistor is connected to the source of another low-voltage isolation P-MOS transistor, the drain of this one low-voltage isolation N-MOS transistor is connected to the drain of the other low-voltage isolation P-MOS transistor, and the source of this low-voltage isolation P-MOS transistor is connected to the first node 50; between the signal ground terminal 30 and the power supply ground terminal 20, two low-voltage isolation N-MOS transistors are provided. Among them, the source of one low-voltage isolation N-MOS transistor is connected to the power supply ground terminal 20, the drain of this one low-voltage isolation N-MOS transistor is connected to the drain of another low-voltage isolation N-MOS transistor, and the source of the other low-voltage isolation N-MOS transistor is connected to the signal ground terminal 30. Among them, the source of each low-voltage isolation P-MOS transistor is also connected to the gate, the gate of each low-voltage isolation N-MOS transistor is connected to the source, and the ISO port of each low-voltage isolation N-MOS transistor is floating or connected to the drain.

[0069] In this example, when performing electrostatic discharge protection between the positive power supply connection terminal 10 and the signal ground terminal 30, the positive power supply connection terminal 10 and the power supply ground terminal 20, and the signal ground terminal 30 and the power supply ground terminal 20, the above Example 1 can be referred to. The difference is only that the low-voltage electrostatic discharge protection devices are a mixture of low-voltage isolation P-MOS transistors and low-voltage isolation P-MOS transistors, which will not be elaborated here.

[0070] Example 5: As Figure 4 shown, in an integrated circuit having two positive power supply connection terminals 10 ( Figure 4 VCC in which represents one positive power supply connection terminal 10, and VM represents the other positive power supply connection terminal 10), one signal ground terminal 30, and one power supply ground terminal 20, only electrostatic discharge diodes are provided. Among them, two electrostatic discharge diodes are provided between VCC and the first node 50, two electrostatic discharge diodes are provided between VM and the first node 50, and two electrostatic discharge diodes are provided between the signal node terminal and the power supply ground terminal 20.

[0071] In this example, three electrostatic discharge diodes between VCC and the power ground terminal 20 provide electrostatic discharge protection between VCC and the power ground terminal 20, and three electrostatic discharge diodes between VCC and the signal ground terminal 30 provide electrostatic discharge protection between VCC and the signal ground terminal 30. Three electrostatic discharge diodes between VM and the power ground terminal 20 provide electrostatic discharge protection between VM and the power ground terminal 20, and three electrostatic discharge diodes between VM and the signal ground terminal 30 provide electrostatic discharge protection between VM and the signal ground terminal 30. Two electrostatic discharge diodes between the signal ground terminal 30 and the power ground terminal 20 provide electrostatic discharge protection between the signal ground terminal 30 and the power ground terminal 20. Four electrostatic discharge diodes between VM and VCC provide electrostatic discharge protection between VM and VCC.

[0072] In some embodiments, the present invention further provides a chip applying the electrostatic discharge protection circuit of the multi-power domain as described above. The chip may include a signal ground terminal 30, a power ground terminal 20, and at least one positive power connection terminal 10. Among them, several electrostatic discharge protection units 40 connected in series in sequence are arranged between the signal ground terminal 30 and the power ground terminal 20, and the positive power connection terminal 10 is connected to the connection path between any two adjacent electrostatic discharge protection units 40 among the several electrostatic discharge protection units 40 connected in sequence.

[0073] In this embodiment, since the first node 50 is located on the connection path between any two adjacent electrostatic discharge protection units 40 between the signal ground terminal 30 and the power ground terminal 20, the electrostatic discharge protection units 40 between the signal ground terminal 30 and the power ground terminal 20 are reused, reducing the designed number of the electrostatic discharge protection units 40, thereby reducing the chip area and at the same time reducing the manufacturing cost of the chip.

[0074] Here, it should be noted that the description of the above chip embodiment is similar to the description of the above electrostatic discharge protection circuit embodiment of the multi-power domain, and has beneficial effects similar to those of the above electrostatic discharge protection circuit of the multi-power domain. For the technical details not disclosed in the chip embodiment, please refer to the description of the electrostatic discharge protection circuit embodiment of the multi-power domain of the present invention for understanding.

[0075] In summary, the present invention provides an electrostatic discharge protection circuit and a chip of a multi-power domain, having the following beneficial effects:

[0076] Since the first node 50 is located on the connection path between any two adjacent electrostatic discharge protection units 40 between the signal ground terminal 30 and the power ground terminal 20, the electrostatic discharge protection units 40 between the signal ground terminal 30 and the power ground terminal 20 are multiplexed, reducing the designed number of electrostatic discharge protection units 40, thereby reducing the chip area and at the same time reducing the manufacturing cost of the chip.

[0077] It can be understood that the above embodiments only represent the preferred embodiments of the present invention, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patent of the present invention; it should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, the above technical features can be freely combined, and several deformations and improvements can also be made, which all belong to the protection scope of the present invention; therefore, all equivalent transformations and modifications made to the scope of the claims of the present invention shall fall within the scope covered by the claims of the present invention.

Claims

1. An electrostatic discharge protection circuit for multiple power domains, characterized in that, Comprising: A signal ground terminal, a power ground terminal, and at least one positive power connection terminal; wherein: A plurality of electrostatic discharge protection units connected in series in sequence are provided between the signal ground terminal and the power ground terminal; The positive power connection terminal is connected to a first node, and the first node is located on the connection path between any two adjacent electrostatic discharge protection units between the signal ground terminal and the power ground terminal.

2. The electrostatic discharge protection circuit for a multi-power supply domain according to claim 1, characterized in that A plurality of electrostatic discharge protection units connected in sequence are provided on the connection path between the positive power connection terminal and the first node.

3. The electrostatic discharge protection circuit for multiple power domains according to claim 1, characterized in that, The electrostatic discharge protection unit is a low-voltage electrostatic discharge protection device.

4. The electrostatic discharge protection circuit for multiple power domains according to claim 3, characterized in that, The low-voltage electrostatic discharge protection device includes an electrostatic discharge protection diode or a switching tube.

5. The electrostatic discharge protection circuit for multiple power domains according to claim 4, characterized in that The switching tube is a low-voltage isolation type N-MOS tube.

6. The electrostatic discharge protection circuit for multiple power domains according to claim 4, characterized in that The switching tube is a low-voltage isolation type P-MOS tube.

7. The electrostatic discharge protection circuit for a multi-power supply domain according to any one of claims 4 to 6, characterized in that, The high potential of the low-voltage electrostatic discharge protection device between the first node and the power ground terminal is close to the first node, and the high potential of the low-voltage electrostatic protection device between the first node and the signal ground terminal is close to the first node.

8. A chip applying the electrostatic discharge protection circuit with multiple power domains as described in any one of claims 1 - 7, characterized in that The chip includes: a signal ground terminal, a power ground terminal, and at least one positive power connection terminal; wherein: A plurality of electrostatic discharge protection units connected in series in sequence are provided between the signal ground terminal and the power ground terminal, and the positive power connection terminal is connected to the connection path between any two adjacent electrostatic discharge protection units among the plurality of electrostatic discharge protection units connected in sequence.

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