Soft start circuit for power management chip

Abstract

The utility model discloses a soft start circuit used for a power supply management chip, which comprises a power supply management chip U6, an NPN tube Q22, an NPN tube Q30, a diode D23, a diode D29 and a capacitor C65, the anode of the diode D29 is connected with the COMP end of the power supply management chip U6, the cathode of the diode D29 is connected with the collector of the NPN tube Q22, the emitter of the NPN tube Q22 is grounded, and the capacitor C65 is connected with the power supply management chip U6. The base electrode of the NPN tube Q22 is connected to the VREF end of the power management chip U6 through the resistor R72, the cathode of the diode D23 is connected to the VREF end of the power management chip U6, the anode of the diode D23 is connected to the first end of the capacitor C65, the second end of the capacitor C65 is grounded, the diode D23 is connected with the resistor R60 in parallel, the resistor R69 is connected between the cathode of the diode D29 and the first end of the capacitor C65, the collector electrode of the NPN tube Q30 is connected to the base electrode of the NPN tube Q22, and the cathode of the NPN tube Q22 is connected to the first end of the capacitor C65. The emitter electrode of the NPN tube Q30 is grounded, and the base electrode of the NPN tube Q30 is used for accessing an enable signal POWEREN.

Description

Technical Field

[0001] The utility model relates to a power supply circuit, in particular to a soft start circuit for a power management chip. Background Art

[0002] The power management chip includes a COMP terminal, which has various functions such as controlling the open-loop gain and phase compensation, aiming to achieve stable output voltage. In the prior art, when the power management chip is powered on, the COMP pin usually has an overshoot during power-on. The factors causing the overshoot include circuit architecture, component selection, system response, etc. These factors will directly affect the stability of the output voltage of the power supply circuit. Therefore, how to reduce the system impact at the beginning of power-on of the power supply circuit is a technical problem to be solved urgently in the existing similar circuits. Summary of the Utility Model

[0003] The technical problem to be solved by the utility model is to provide a soft start circuit for a power management chip with an enable control function and capable of realizing soft start, aiming at the deficiencies of the prior art.

[0004] To solve the above technical problem, the utility model adopts the following technical solutions.

[0005] A soft start circuit for a power management chip includes a power management chip U6, an NPN transistor Q22, an NPN transistor Q30, a diode D23, a diode D29, and a capacitor C65. The anode of the diode D29 is connected to the COMP terminal of the power management chip U6, the cathode of the diode D29 is connected to the collector of the NPN transistor Q22, the emitter of the NPN transistor Q22 is grounded, the base of the NPN transistor Q22 is connected to the VREF terminal of the power management chip U6 through a resistor R72, the cathode of the diode D23 is connected to the VREF terminal of the power management chip U6, the anode of the diode D23 is connected to the first end of the capacitor C65, the second end of the capacitor C65 is grounded, a resistor R60 is connected in parallel with the diode D23, a resistor R69 is connected between the cathode of the diode D29 and the first end of the capacitor C65, the collector of the NPN transistor Q30 is connected to the base of the NPN transistor Q22, the emitter of the NPN transistor Q30 is grounded, and the base of the NPN transistor Q30 is used to access an enable signal POWER_EN.

[0006] Preferably, a resistor R53 and a resistor R59 are connected in series in sequence between a preset power supply terminal VCC5V and the ground, and the connection point of the resistor R53 and the resistor R59 is connected to the COMP terminal of the power management chip U6 through a resistor R56 and a capacitor C26 connected in series in sequence.

[0007] Preferably, the VREF terminal of the power management chip U6 is grounded through a sequentially connected resistor R67 and capacitor C63, and the connection point of the resistor R67 and the capacitor C63 is connected to the RT / CT terminal of the power management chip U6.

[0008] Preferably, a resistor R76 is connected in series to the base of the NPN transistor Q30, and the other end of the resistor R76 is used to connect to the enable signal POWER_EN.

[0009] Preferably, the base of the NPN transistor Q30 is grounded through a capacitor C71.

[0010] Preferably, the chip model of the power management chip U6 is UCC28C41.

[0011] In the soft start circuit for a power management chip disclosed by the present utility model, during the working process, when the enable signal POWER_EN is at a low level, the NPN transistor Q30 is not turned on, the NPN transistor Q22 is turned on, and the COMP terminal of the power management chip U6 is pulled low to the ground through the diode D29 and the NPN transistor Q22, and the power management chip U6 does not work at this time; when the enable signal POWER_EN is at a high level, the NPN transistor Q30 is turned on, the NPN transistor Q22 is not turned on, the VREF terminal of the power management chip U6 charges the capacitor C65 through the resistor R60, causing the voltage of the capacitor C65 to rise slowly. During this process, the COMP terminal of the power management chip U6 is clamped to the voltage of the capacitor C65 through the resistor 69 and the diode D29, thereby realizing a slow release of the COMP terminal of the power management chip U6. The voltage rise process of the capacitor C65 is the soft start process of the power management chip U6. By changing the capacitance value of the capacitor C65, the soft start time can be adjusted. Based on the above principle, it can be seen that the present utility model not only has an enable control function, but also better realizes the soft start function, thus meeting the application requirements of the power supply circuit. Description of the Drawings

[0012] Figure 1 is the schematic diagram of the soft start circuit for the power management chip of the present utility model;

[0013] Figure 2 is the start waveform diagram of the power supply circuit. Detailed Embodiments

[0014] The present utility model will be described in more detail below with reference to the drawings and embodiments.

[0015] The present utility model discloses a soft start circuit for a power management chip. Please refer to Figure 1, which includes a power management chip U6, an NPN transistor Q22, an NPN transistor Q30, a diode D23, a diode D29, and a capacitor C65. The anode of the diode D29 is connected to the COMP terminal of the power management chip U6, the cathode of the diode D29 is connected to the collector of the NPN transistor Q22, the emitter of the NPN transistor Q22 is grounded, the base of the NPN transistor Q22 is connected to the VREF terminal of the power management chip U6 through a resistor R72, the cathode of the diode D23 is connected to the VREF terminal of the power management chip U6, the anode of the diode D23 is connected to the first end of the capacitor C65, the second end of the capacitor C65 is grounded, a resistor R60 is connected in parallel with the diode D23, a resistor R69 is connected between the cathode of the diode D29 and the first end of the capacitor C65, the collector of the NPN transistor Q30 is connected to the base of the NPN transistor Q22, the emitter of the NPN transistor Q30 is grounded, and the base of the NPN transistor Q30 is used to access an enable signal POWER_EN.

[0016] During the operation of the above circuit, when the enable signal POWER_EN is at a low level, the NPN transistor Q30 is not conducting, the NPN transistor Q22 is conducting, and the COMP terminal (i.e., pin 1) of the power management chip U6 is pulled low to ground through the diode D29 and the NPN transistor Q22, and the power management chip U6 does not work at this time; when the enable signal POWER_EN is at a high level, the NPN transistor Q30 is conducting, the NPN transistor Q22 is not conducting, the VREF terminal of the power management chip U6 charges the capacitor C65 through the resistor R60, causing the voltage of the capacitor C65 to rise slowly. During this process, the COMP terminal of the power management chip U6 is clamped to the voltage of the capacitor C65 through the resistor 69 and the diode D29, thereby realizing a slow release of the COMP terminal of the power management chip U6. The rising process of the voltage of the capacitor C65 is the soft start process of the power management chip U6. By changing the capacitance value of the capacitor C65, the soft start time can be adjusted. Based on the above principle, it can be seen that the present invention not only has an enable control function, but also preferably realizes a soft start function, thereby meeting the application requirements of the power supply circuit.

[0017] As a preferred method, a resistor R53 and a resistor R59 are connected in series in turn between a preset power supply terminal VCC5V and ground, and the connection point of the resistor R53 and the resistor R59 is connected to the COMP terminal of the power management chip U6 through a resistor R56 and a capacitor C26 connected in series in turn. Among them, the connection point of the resistor R53 and the resistor R59 is also directly connected to the VFB terminal of the power management chip U6.

[0018] As the peripheral circuit of the power management chip U6, in this embodiment, the VREF terminal of the power management chip U6 is grounded through a sequentially connected resistor R67 and capacitor C63, and the connection point of the resistor R67 and the capacitor C63 is connected to the RT / CT terminal of the power management chip U6.

[0019] Regarding the access of the enable signal POWER_EN, this embodiment also has a filtering effect. Specifically, please refer to Figure 1 , a resistor R76 is connected in series to the base of the NPN transistor Q30, and the other end of the resistor R76 is used to access the enable signal POWER_EN. Further, the base of the NPN transistor Q30 is grounded through a capacitor C71. In the above circuit, the resistor R76 and the capacitor C71 form an RC low-pass filter circuit, whose function is to filter out the clutter interference in the enable signal POWER_EN to make the startup control accurate.

[0020] Regarding the chip selection of the power management chip U6, in this embodiment, the chip model of the power management chip U6 is UCC28C41.

[0021] The soft start circuit disclosed by the present utility model, after being applied to the power circuit, the power startup waveform curve is as Figure 2 shown. It can be seen from the power startup waveform diagram that there is a soft start time of nearly 10 ms.

[0022] The above is only a preferred embodiment of the present utility model and is not used to limit the present utility model. Any modifications, equivalent replacements, or improvements made within the technical scope of the present utility model shall be included within the scope protected by the present utility model.

Claims

1. A soft start circuit for a power management chip, characterized in that, It includes a power management chip U6, an NPN transistor Q22, an NPN transistor Q30, a diode D23, a diode D29, and a capacitor C65. The anode of the diode D29 is connected to the COMP terminal of the power management chip U6, the cathode of the diode D29 is connected to the collector of the NPN transistor Q22, the emitter of the NPN transistor Q22 is grounded, the base of the NPN transistor Q22 is connected to the VREF terminal of the power management chip U6 through a resistor R72, the cathode of the diode D23 is connected to the VREF terminal of the power management chip U6, the anode of the diode D23 is connected to the first end of the capacitor C65, the second end of the capacitor C65 is grounded, a resistor R60 is connected in parallel with the diode D23, a resistor R69 is connected between the cathode of the diode D29 and the first end of the capacitor C65, the collector of the NPN transistor Q30 is connected to the base of the NPN transistor Q22, the emitter of the NPN transistor Q30 is grounded, and the base of the NPN transistor Q30 is used to access the enable signal POWER_EN.

2. The soft start circuit for a power management chip according to claim 1, characterized in that, A resistor R53 and a resistor R59 are connected in series in turn between the preset power supply terminal VCC5V and the ground, and the connection point of the resistor R53 and the resistor R59 is connected to the COMP terminal of the power management chip U6 through a resistor R56 and a capacitor C26 connected in series in turn.

3. The soft start circuit for a power management chip according to claim 1, characterized in that, The VREF terminal of the power management chip U6 is grounded through a resistor R67 and a capacitor C63 connected in series in turn, and the connection point of the resistor R67 and the capacitor C63 is connected to the RT / CT terminal of the power management chip U6.

4. The soft start circuit for a power management chip as described in claim 1, wherein A resistor R76 is connected in series with the base of the NPN transistor Q30, and the other end of the resistor R76 is used to access the enable signal POWER_EN.

5. The soft start circuit for a power management chip as described in claim 4, characterized in that, The base of the NPN transistor Q30 is grounded through a capacitor C71.

6. The soft start circuit for a power management chip as claimed in claim 1, wherein The chip model of the power management chip U6 is UCC28C41.

Images