Printed circuit board

Abstract

The utility model discloses a printed circuit board. The printed circuit board comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are stacked, the printed circuit board comprises at least two power devices which are connected in parallel, a driving chip and a signal ground; a first pole and a second pole of the power device are located on the fourth conductive layer, the first pole is connected with a first end of a first winding of the transformer, a second end of the first winding is connected with a power supply, the second end of the first winding is connected with a first end of the capacitor, and a second end of the capacitor is connected with the second pole; the control electrode of the power device and the driving chip are located on the fourth conductive layer. The signal ground is located on the third conductive layer. The driving chip is connected with the control electrode, the second electrode is connected with the signal ground, and the signal ground is connected with the driving chip to form a driving loop. According to the technical scheme of the utility model, the parasitic inductance of the printed circuit board is reduced, and the reliability of the printed circuit board is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of printed circuit boards, and particularly relates to a printed circuit board. Background Art

[0002] The power conversion circuit can convert the input power, for example, convert the power of the input power, so as to meet the requirements of the load. The power conversion circuit includes power devices, and the power devices can be Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), that is, MOS tubes. The power conversion circuit can be a flyback circuit, and the power device is connected to the flyback transformer.

[0003] In order to control the on and off of the MOS tube, the power conversion circuit further includes a drive chip. The drive chip outputs a drive signal to the MOS tube according to the pulse width modulation signal to realize the drive of the MOS tube.

[0004] In the prior art, in the printed circuit board where the power conversion circuit is located, the area of the drive loop formed by the drive chip and the MOS tube is large, the parasitic inductance in the drive loop is large, and it is easily interfered by the power signal, resulting in poor reliability of the power conversion circuit. Summary of the Utility Model

[0005] The utility model provides a printed circuit board to solve the problem that the parasitic inductance in the drive loop of the printed circuit board is large and it is easily interfered by the power signal, resulting in poor reliability of the power conversion circuit.

[0006] The utility model provides a printed circuit board, which includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked; the printed circuit board includes at least two power devices connected in parallel, a drive chip and a signal ground;

[0007] The first pole and the second pole of the power device are located on the fourth conductive layer. The first pole is connected to the first end of the first winding of the transformer. The second end of the first winding is connected to the power supply. The second end of the first winding is connected to the first end of the capacitor. The second end of the capacitor is connected to the second pole.

[0008] The control pole of the power device and the drive chip are located on the fourth conductive layer, and the signal ground is located on the third conductive layer; the drive chip is connected to the control pole, the second pole is connected to the signal ground, and the signal ground is connected to the drive chip to form a drive loop.

[0009] Optionally, the third pole of the power device is located in the first conductive layer, the fourth pole of the power device is located in the second conductive layer, the third pole is connected to the first pole, and the fourth pole is connected to the second pole;

[0010] The orthographic projection of the third pole on the fourth conductive layer coincides with the first pole, and the orthographic projection of the fourth pole on the fourth conductive layer coincides with the second pole.

[0011] Optionally, the first poles of different power devices are connected to form a first electrode portion extending in a first direction, the second poles of different power devices are connected to form a second electrode portion extending in the first direction, and the first electrode portion and the second electrode portion are alternately arranged at intervals; wherein, the first direction is the arrangement direction of at least two of the power devices.

[0012] Optionally, both ends of the first electrode portion are respectively connected to the third pole through first vias, and both ends of the second electrode portion are respectively connected to the fourth pole through second vias.

[0013] Optionally, the power device is a gallium nitride device;

[0014] The gate of the gallium nitride device is the control pole of the power device, the drain of the gallium nitride device is the first pole of the power device, and the source of the gallium nitride device is the second pole of the power device.

[0015] Optionally, the packaging method of the power device is flip-chip quad flat no-lead package FCQFN.

[0016] Optionally, the second pole is connected to the power ground, and the power ground is located in the second conductive layer;

[0017] The signal ground is connected to the power ground; the third conductive layer covers the driving chip.

[0018] Optionally, there is at least one overlapping area between the second conductive layer and the third conductive layer, and the signal ground and the power ground are connected in the overlapping area;

[0019] The second conductive layer does not cover the third conductive layer; or, the second conductive layer covers the area of the third conductive layer other than the grounding pins of the driving chip.

[0020] Optionally, the printed circuit board further includes a third via, and the signal ground and the power ground are connected through the third via;

[0021] The area of the overlapping area is larger than the opening area of one third via and smaller than the opening area of two third vias;

[0022] The printed circuit board further includes a fourth via, and the driving chip is connected to the signal ground through the fourth via.

[0023] Optionally, the printed circuit board further includes a first resistor, and the first resistor is connected between the driving chip and the control electrode; the first resistor is located on the fourth conductive layer, and the third conductive layer covers the first resistor.

[0024] In the technical solution of the embodiment of the present invention, by arranging the control electrode of the power device and the driving chip on the fourth conductive layer and arranging the signal ground on the third conductive layer, the driving loop formed by the output end of the driving chip, the control electrode, the second electrode of the power device, the signal ground and the grounding pin of the driving chip spans the third conductive layer and the fourth conductive layer, so that the driving loop can include a path perpendicular to the surface of the third conductive layer or the fourth conductive layer, thereby making the area of the driving loop smaller, which is beneficial to reducing the parasitic inductance of the printed circuit board and avoiding the driving loop from being interfered by power signals, thus improving the reliability of the printed circuit board.

[0025] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] Figure 1 is a schematic structural diagram of a power conversion circuit provided by an embodiment of the present invention;

[0028] Figure 2 is a schematic structural diagram of a printed circuit board provided by an embodiment of the present invention;

[0029] Figure 3 is a cross-sectional view of a printed circuit board provided by an embodiment of the present invention;

[0030] Figure 4 is a schematic structural diagram of another printed circuit board provided by an embodiment of the present invention;

[0031] Figure 5 is a schematic structural diagram of another printed circuit board provided by an embodiment of the present invention;

[0032] Figure 6It is a schematic structural diagram of another printed circuit board provided by an embodiment of the present utility model;

[0033] Figure 7 It is a schematic structural diagram of another printed circuit board provided by an embodiment of the present utility model. Detailed implementation manners

[0034] In order to enable those skilled in the art to better understand the solution of the present utility model, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0035] It should be noted that the terms "first", "second", etc. in the description and claims of the present utility model and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0036] This embodiment provides a printed circuit board, and this printed circuit board is a printed circuit board of a power conversion circuit. Figure 1 It is a schematic structural diagram of a power conversion circuit provided by an embodiment of the present utility model, Figure 2 It is a schematic structural diagram of a printed circuit board provided by an embodiment of the present utility model, Figure 3 It is a cross-sectional view of a printed circuit board provided by an embodiment of the present utility model. Refer to Figure 1 、 Figure 2 and Figure 3 , the printed circuit board includes: a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, and a fourth conductive layer M4 that are stacked; the printed circuit board includes at least two power devices 110, a driving chip 120, and a signal ground GND that are connected in parallel;

[0037] The first pole 111 and the second pole 112 of the power device 110 are located in the fourth conductive layer M4. The first pole 111 is connected to the first end of the first winding 211 of the transformer 210. The second end of the first winding 211 is connected to the power supply Vin. The second end of the first winding 211 is connected to the first end of the capacitor C1. The second end of the capacitor C1 is connected to the second pole 112.

[0038] The control pole 113 of the power device 110 and the driver chip 120 are located in the fourth conductive layer M4. The signal ground GND is located in the third conductive layer M3. The driver chip 120 is connected to the control pole 113. The second pole 112 is connected to the signal ground GND. The signal ground GND is connected to the driver chip 120 to form a drive loop.

[0039] Among them, the power device 110 can be a gallium nitride device, a MOS transistor or other devices, which is not limited here. The control pole 113 of the power device 110 can be a gate. For example, the first pole 111 of the power device 110 is a drain, and the second pole 112 is a source; or the first pole 111 of the power device 110 is a source, and the second pole 112 is a drain, which is not limited here. At least two power devices 110 are connected in parallel, which means that all the first poles 111 of the power devices 110 are connected together, all the second poles 112 of the power devices 110 are connected together, and all the control poles 113 of the power devices 110 are connected to the driver chip 120. By setting at least two power devices 110 to be connected in parallel, the current-carrying capacity of the power conversion circuit can be improved.

[0040] The transformer 210 can be a flyback transformer. The first winding 211 of the transformer 210 can be used as a power inductor. The first pole 111 of the power device 110 is connected to the first end of the first winding 211 of the transformer 210. The second end of the first winding 211 is connected to the power supply Vin. The second end of the first winding 211 is connected to the first end of the capacitor C1. The second end of the capacitor C1 is connected to the second pole 112 to form a power loop. The power loop can adjust the power or voltage of the power supply Vin so that the output power meets the load requirements.

[0041] Among them, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3 and the fourth conductive layer M4 can be copper layers, that is, each conductive layer is formed by laying copper. The signal ground GND is formed by laying copper.

[0042] Among them, the input end of the driver chip 120 receives the pulse width modulation signal P1, so that the driver chip 120 generates a drive signal according to the pulse width modulation signal P1 and outputs the drive signal to the control pole 113 of the power device 110, thereby controlling the conduction timing of the power device 110, and further controlling the output power or output voltage of the power device 110, so as to realize the conversion of the power or voltage of the power supply Vin.

[0043] Specifically, the control electrode 113 of the power device 110 and the driving chip 120 are located on the fourth conductive layer M4, the signal ground GND is located on the third conductive layer M3, and the driving chip 120, the control electrode 113, the second electrode 112, the signal ground GND and the driving chip 120 form a driving loop, so that the driving loop spans the third conductive layer M3 and the fourth conductive layer M4, and the driving loop can include a path perpendicular to the surface of the third conductive layer M3 or the fourth conductive layer M4, thereby making the area of the driving loop smaller, which is beneficial to reducing the parasitic inductance of the printed circuit board, avoiding interference of the driving loop by power signals, thereby improving the reliability of the printed circuit board, and can also reduce the loss of the driving loop, accelerate the switching speed of the power device 110, and improve the driving efficiency.

[0044] Moreover, by arranging the driving chip 120 on the fourth conductive layer M4 and arranging the signal ground GND on the third conductive layer M3, the signal ground GND is adjacent to the driving circuit, which can further reduce the parasitic inductance and enhance the anti-interference ability of the printed circuit board.

[0045] Among them, for example, the output terminal of the driving chip 120 is connected to the control electrode 113 of the power device 110, and the grounding terminal of the driving chip 120 is connected to the signal ground GND.

[0046] The technical solution of this embodiment, by arranging the control electrode of the power device and the driving chip on the fourth conductive layer and arranging the signal ground on the third conductive layer, makes the driving loop formed by the output terminal of the driving chip, the control electrode, the second electrode of the power device, the signal ground and the grounding pin of the driving chip span the third conductive layer and the fourth conductive layer, so that the driving loop can include a path perpendicular to the surface of the third conductive layer or the fourth conductive layer, thereby making the area of the driving loop smaller, which is beneficial to reducing the parasitic inductance of the printed circuit board, avoiding interference of the driving loop by power signals, and thus improving the reliability of the printed circuit board.

[0047] On the basis of the above technical solution, Figure 4 is a schematic structural diagram of another printed circuit board provided by an embodiment of the present invention. Optionally, referring to Figure 4 , the third electrode 114 of the power device 110 is located on the first conductive layer M1, the fourth electrode 115 of the power device 110 is located on the second conductive layer M2, the third electrode 114 is connected to the first electrode 111, and the fourth electrode 115 is connected to the second electrode 112;

[0048] The orthographic projection of the third electrode 114 on the fourth conductive layer M4 coincides with the first electrode 111, and the orthographic projection of the fourth electrode 115 on the fourth conductive layer M4 coincides with the second electrode 112.

[0049] Specifically, by providing the third pole 114 and the fourth pole 115, both the source and the drain of the power device 110 are of a two-layer structure, which can improve the current-carrying capacity of the power device 110, enhance the heat dissipation effect, avoid the problem of thermal failure of the power device 110, and is beneficial to further improving the reliability of the printed circuit board.

[0050] Based on the above technical solution, Figure 5 is a schematic structural diagram of another printed circuit board provided by an embodiment of the present invention. Optionally, referring to Figure 4 and Figure 5 , the first poles 111 of different power devices 110 are connected to form a first electrode portion 116 extending along the first direction X, the second poles 112 of different power devices 110 are connected to form a second electrode portion 117 extending along the first direction X, and the first electrode portion 116 and the second electrode portion 117 are alternately arranged at intervals; wherein, the first direction X is the arrangement direction of at least two power devices 110.

[0051] Specifically, the first pole 111 of the power device 110 is connected to the power supply Vin through a transformer 210, and the second pole 112 of the power device 110 is connected to the power ground, so that the current flows out from the first pole 111 of the power device 110 and can flow to the second pole 112 of the power device 110. In this way, the current directions on the first electrode portion 116 and the second electrode portion 117 are opposite, and the first electrode portion 116 and the second electrode portion 117 are alternately arranged, that is, the first electrode portion 116 and the second electrode portion 117 are adjacent, so the current directions on the adjacent first electrode portion 116 and second electrode portion 117 are opposite, thereby the magnetic field formed by the current on the first electrode portion 116 cancels out the magnetic field formed by the current on the second electrode portion 117, which is beneficial to reducing the parasitic inductance of the power loop, can reduce the loss of the power loop, and improve the power conversion efficiency.

[0052] Optionally, referring to Figure 4 and Figure 5 , both ends of the first electrode portion 116 are respectively connected to the third pole 114 through the first vias 131, and both ends of the second electrode portion 117 are respectively connected to the fourth pole 115 through the second vias 132.

[0053] Specifically, by providing the first vias 131 at both ends of the first electrode portion 116, the current on the first electrode portion 116 can flow to the first vias 131, and by providing the second vias 132 at both ends of the second electrode portion 117, the current on the second electrode portion 117 flows out from the second vias 132, so that the current directions on the first electrode portion 116 and the second electrode portion 117 are opposite, which is beneficial to reducing the parasitic inductance of the power loop.

[0054] Wherein, at least one first via hole 131 may be provided at each end of the first electrode portion 116. For example, two first via holes 131 are provided at each end of the first electrode portion 116, which can improve the current transmission and carrying capacity. Similarly, at least one second via hole 132 may be provided at each end of the second electrode portion 117. For example, two second via holes 132 are provided at each end of the second electrode portion 117, which can improve the current transmission and carrying capacity.

[0055] Wherein, if the third electrode 114 is in the first conductive layer M1, the first via hole 131 is a via hole penetrating through the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. If the fourth electrode 115 is in the second conductive layer M2, the second via hole 132 may be a via hole penetrating through the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4, or may be a via hole penetrating through the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. This embodiment does not make any limitations.

[0056] Based on the above technical solutions, optionally, the power device 110 is a gallium nitride device;

[0057] The gate of the gallium nitride device is the control electrode of the power device 110, the drain of the gallium nitride device is the first electrode 111 of the power device 110, and the source of the gallium nitride device is the second electrode 112 of the power device 110.

[0058] Specifically, the power device 110 is a gallium nitride device, that is, a gallium nitride transistor. The gallium nitride transistor is a high electron mobility transistor, which can be applied to high-frequency circuits, and the gallium nitride transistor has good heat dissipation performance, which can prevent the power device 110 from thermal failure and is beneficial to further improving the reliability of the printed circuit board.

[0059] Optionally, the packaging method of the power device 110 is flip chip quad flat no-leads package FCQFN.

[0060] Specifically, the quad flat no-leads package (QFN) has a small area, which is beneficial to reducing the area of the printed circuit board and has good heat dissipation performance. The flip chip quad flat no-leads package FCQFN has an even smaller area and less high-frequency attenuation, resulting in a smaller parasitic inductance of the power loop, which is beneficial to further improving the reliability of the printed circuit board.

[0061] Optionally, the second electrode 112 is connected to the power ground PGND, and the power ground PGND is located in the second conductive layer M2; the signal ground GND is connected to the power ground PGND; the third conductive layer M3 covers the driving chip 120.

[0062] Specifically, the first pole 111 of the power device 110 is connected to the power supply Vin through the transformer 210, and the second pole 112 of the power device 110 is connected to the power ground PGND, so that the current flows out from the first pole 111 of the power device 110 and can flow to the second pole 112 of the power device 110. In this way, the current directions on the first electrode portion 116 and the second electrode portion 117 are opposite.

[0063] By setting the power ground PGND in the second conductive layer M2, the fourth pole 114 can be reused as the power ground PGND, or the fourth pole 114 and the power ground PGND can be connected as a whole, so that the entire layer can be copper-plated to form the fourth pole 114 and the power ground PGND.

[0064] Optionally, referring to Figure 4 , there is at least one overlapping area 141 between the second conductive layer M2 and the third conductive layer M3, and the signal ground GND and the power ground PGND are connected in the overlapping area 141. For example, the number of overlapping areas 141 is the same as the number of power devices 110, that is, the overlapping areas 141 correspond one-to-one with the power devices 110, so that the electrodes (the second pole 112 and the fourth pole 115) of each power device 110 can be connected to the signal ground GND. In this way, it is convenient to connect the signal ground GND and the power ground PGND. For example, the area of the overlapping area 141 is small, so that the signal ground GND and the power ground PGND are connected at a single point, thereby reducing the mutual interference between the signal ground GND and the power ground PGND, that is, avoiding the mutual interference between the driving loop and the power loop, and improving the anti-interference ability of the printed circuit board.

[0065] In one embodiment, optionally, referring to Figure 4 , the second conductive layer M2 does not cover the third conductive layer M3. In this way, the area of the second conductive layer M2 is small, reducing the copper-plating area, which is beneficial to reducing costs.

[0066] In another embodiment, Figure 6 is a schematic structural diagram of another printed circuit board provided by an embodiment of the present invention, Figure 7 is a schematic structural diagram of another printed circuit board provided by an embodiment of the present invention. Optionally, referring to Figure 6 and Figure 7 , the second conductive layer M2 covers the area outside the grounding pin 121 of the driving chip 120 on the third conductive layer M3.

[0067] Among them, Figure 6 shows parts of the second conductive layer M2, the first conductive layer M1 and the fourth conductive layer M4, Figure 7 shows parts of the first conductive layer M1, the third conductive layer M3 and the fourth conductive layer M4. Combining Figure 6 and Figure 7It can be seen that the second conductive layer M2 covers the area on the third conductive layer M3 except for the ground pin 121 of the driving chip 120.

[0068] Specifically, the ground pin 121 of the driving chip 120 is connected to the third conductive layer M3, so that the ground pin 121 of the driving chip 120 is connected to the signal ground GND. The ground pin 121 of the driving chip 120 can be one or more. Figure 7 The case where there are multiple ground pins 121 is shown in [reference], but it is not limited. By setting the second conductive layer M2 to cover the area on the third conductive layer M3 except for the ground pin 121 of the driving chip 120, the second conductive layer M2 is larger. While improving the current-carrying capacity and enhancing the heat dissipation effect, it can ensure the single-point connection between the signal ground GND and the power ground PGND, thereby reducing the mutual interference between the signal ground GND and the power ground PGND, that is, avoiding the mutual interference between the driving loop and the power loop, and improving the anti-interference ability of the printed circuit board.

[0069] Optionally, referring to Figure 4 , the printed circuit board further includes a third via 133, and the signal ground GND and the power ground PGND are connected through the third via 133;

[0070] The area of the overlapping region 141 is larger than the opening area of one third via 133 and smaller than the opening area of two third vias 133.

[0071] Specifically, the third via 133 is located in the overlapping region 141, so that the signal ground GND and the power ground PGND are connected through the third via 133 in the overlapping region 141. And the area of the overlapping region 141 is larger than the opening area of one third via 133 and smaller than the opening area of two third vias 133, so that the area of the overlapping region 141 is small, ensuring the single-point connection between the signal ground GND and the power ground PGND, thereby reducing the mutual interference between the signal ground GND and the power ground PGND, that is, avoiding the mutual interference between the driving loop and the power loop, and improving the anti-interference ability of the printed circuit board.

[0072] Optionally, referring to Figure 4 , the printed circuit board further includes a fourth via 134, and the driving chip 120 is connected to the signal ground GND through the fourth via 134. That is, the ground pin 121 of the driving chip 120 is connected to the signal ground GND through the fourth via 134, which is convenient for the connection between the driving chip 120 and the signal ground GND.

[0073] Optionally, referring to Figure 4 and Figure 1, the printed circuit board further includes a first resistor R1. The first resistor R1 is connected between the driving chip 120 and the control electrode 113. The first resistor R1 is located in the fourth conductive layer M4, and the third conductive layer M3 covers the first resistor R1.

[0074] Specifically, the first resistor R1 has a current-limiting effect to prevent the current of the driving signal output by the driving chip 120 from being too large. By arranging the first resistor R1 in the fourth conductive layer M4, the driving circuit is located in the fourth conductive layer M4, and the third conductive layer M3 covers the first resistor R1, so that the third conductive layer M3 covers the driving circuit.

[0075] The above specific embodiments do not limit the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A printed circuit board, characterized in that, Including: A first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are stacked; the printed circuit board includes at least two power devices connected in parallel, a drive chip, and a signal ground; A first pole and a second pole of the power device are located on the fourth conductive layer. The first pole is connected to a first end of a first winding of a transformer. A second end of the first winding is connected to a power supply. The second end of the first winding is connected to a first end of a capacitor. A second end of the capacitor is connected to the second pole; A control pole of the power device and the drive chip are located on the fourth conductive layer. The signal ground is located on the third conductive layer; the drive chip is connected to the control pole. The second pole is connected to the signal ground. The signal ground is connected to the drive chip to form a drive loop.

2. The printed circuit board according to claim 1, characterized in that, A third pole of the power device is located on the first conductive layer. A fourth pole of the power device is located on the second conductive layer. The third pole is connected to the first pole. The fourth pole is connected to the second pole; A positive projection of the third pole on the fourth conductive layer coincides with the first pole. A positive projection of the fourth pole on the fourth conductive layer coincides with the second pole.

3. The printed circuit board according to claim 2, wherein, The first poles of different power devices are connected to form a first electrode portion extending in a first direction. The second poles of different power devices are connected to form a second electrode portion extending in the first direction. The first electrode portion and the second electrode portion are alternately arranged at intervals; wherein, the first direction is the arrangement direction of at least two of the power devices.

4. The printed circuit board according to claim 3, wherein Both ends of the first electrode portion are respectively connected to the third pole through first vias. Both ends of the second electrode portion are respectively connected to the fourth pole through second vias.

5. The printed circuit board according to claim 1, wherein The power device is a gallium nitride device; The gate of the gallium nitride device is the control pole of the power device. The drain of the gallium nitride device is the first pole of the power device. The source of the gallium nitride device is the second pole of the power device.

6. The printed circuit board according to claim 1, wherein The packaging method of the power device is flip-chip quad flat no-lead package FCQFN.

7. The printed circuit board according to claim 1, characterized in that, The second pole is connected to a power ground, and the power ground is located on the second conductive layer; The signal ground is connected to the power ground; the third conductive layer covers the drive chip.

8. The printed circuit board according to claim 7, characterized in that, There is at least one overlapping area between the second conductive layer and the third conductive layer. The signal ground and the power ground are connected in the overlapping area; 9. The printed circuit board according to claim 8, wherein The second conductive layer does not cover the third conductive layer; or, the second conductive layer covers the area outside the grounding pin of the drive chip on the third conductive layer. The printed circuit board further includes a third via. The signal ground and the power ground are connected through the third via; The area of the overlapping area is larger than the opening area of one third via and smaller than the opening area of two third vias; The printed circuit board further includes a fourth via. The drive chip and the signal ground are connected through the fourth via.

10. The printed circuit board according to any one of claims 1-9, characterized in that, The printed circuit board further includes a first resistor, and the first resistor is connected between the driving chip and the control electrode; the first resistor is located in the fourth conductive layer, and the third conductive layer covers the first resistor.

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