Wake-up circuit and wake-up device

Abstract

The utility model relates to the technical field of electronic circuits, and provides a wake-up circuit and a wake-up device wherein the wake-up circuit comprises a hysteresis comparison unit and a first switch unit; wherein the negative input end of the hysteresis comparison unit is connected with a wake-up signal input pin, and the positive input end of the hysteresis comparison unit is connected with a constant electricity output pin of target hardware; the output end of the hysteresis comparison unit is connected with the first input end of the first switch unit, and the output end of the first switch unit is connected with a wake-up detection pin; the wake-up detection pin is connected with a WAKE pin and / or a GPIO pin of the target hardware. According to the utility model, the hysteresis comparison unit is arranged, the hysteresis interval is set and the voltage comparison threshold value is configured according to the voltage threshold value of the wake-up pin of the target hardware, and the wake-up signal input by the wake-up signal input pin is judged, so that the false wake-up action caused by the jitter of the ignition signal is effectively prevented.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, and more particularly to a wake-up circuit and a wake-up device. Background Art

[0002] In conventional automotive electronic product hardware design, power supply, communication, and monitoring are all implemented through multiple circuits. This not only increases circuit design complexity but also challenges reliability, system cost, PCB space, and circuit power consumption. To simplify external circuitry, automotive electronic products primarily utilize highly integrated basic hardware systems called SBCs (System Basis Chips). The SBC provides constant power to the MCU. To optimize quiescent current consumption, when the device enters sleep mode, the SBC disables all functions except powering the MCU. To power the device back on, it wakes up via ignition signals such as the KL15 (Key Lock 15) hardwire signal, the IG_ON hardwire signal, and / or a CAN (CAN_INH) interrupt signal.

[0003] Common wake-up circuits generally use OR gate circuits, such as Figure 1 As shown in the figure, when the ignition signal or CAN interrupt signal voltage exceeds the voltage threshold of the SBC's WAKE pin, an OR gate generates a high signal, waking the SBC. Simultaneously, the IGN_DET signal is sent high to the MCU for detection, enabling full device operation. However, when the ignition signal is near the SBC's WAKE pin voltage threshold, jitter can easily cause the SBC to falsely wake up due to jitter. Furthermore, with the NXP FS23 series SBC, when the ignition signal is OFF, the MCU detects the IGN_DET pin output as low. The MCU notifies the SBC to enter sleep mode via SPI communication. However, due to the 100kΩ pull-down resistor inside the SBC's WAKE pin, the WAKE pin discharges slowly, remaining high. This results in a delay between the MCU notifying the SBC of sleep and the WAKE pin's status, preventing the SBC from entering sleep mode. This results in high quiescent current consumption. Utility Model Content

[0004] The present invention provides a wake-up circuit and a wake-up device to overcome the defect of the wake-up circuit in the prior art that the SBC may be mistakenly awakened due to the jitter of the ignition signal.

[0005] In order to solve the above technical problems, the technical solutions of the present utility model are as follows:

[0006] A wake-up circuit includes a hysteresis comparison unit and a first switch unit; wherein the negative input terminal of the hysteresis comparison unit is connected to the wake-up signal input pin, and the positive input terminal of the hysteresis comparison unit is connected to the constant power output pin of the target hardware; the output terminal of the hysteresis comparison unit is connected to the first input terminal of the first switch unit, and the output terminal of the first switch unit is connected to the wake-up detection pin; the wake-up detection pin is connected to the WAKE pin and / or GPIO (General Purpose Input / Output) pin of the target hardware.

[0007] In this technical solution, a hysteresis comparison unit is set to compare the voltage signal input to the wake-up signal input pin. When the voltage signal is less than or equal to the first threshold value configured by the hysteresis comparison unit, the hysteresis comparison unit outputs a high-level signal or a low-level signal, so that the first switch unit is cut off, the wake-up detection pin outputs a low-level signal, and the target hardware enters a sleep state; when the voltage signal is greater than or equal to the second threshold value configured by the hysteresis comparison unit, the hysteresis comparison unit outputs a low-level signal or a high-level signal, so that the first switch unit is turned on, and the wake-up detection pin outputs a high-level signal that meets the voltage threshold of the WAKE pin and / or GPIO pin of the target hardware, thereby waking up the target hardware.

[0008] As a preferred solution, the hysteresis comparison unit includes a hysteresis comparator and a voltage divider module; wherein:

[0009] The input end of the voltage divider module is connected to the wake-up signal input pin, and the output end of the voltage divider module is connected to the negative input end of the hysteresis comparator;

[0010] The positive input terminal of the hysteresis comparator is connected to the constant power output pin of the target hardware;

[0011] The output terminal of the hysteresis comparator is connected to the first input terminal of the first switch unit.

[0012] As a preferred solution, the voltage divider module includes resistors R1, R2, and R3 connected in series, and capacitors C1, C2, and C3 connected in series; wherein:

[0013] One end of the resistor R1 is electrically connected to the wake-up signal input pin as the input end of the voltage divider module;

[0014] One end of the resistor R3 is electrically connected to the resistor R2, and the other end of the resistor R3 is electrically connected to the negative input end of the hysteresis comparator as the output end of the voltage divider module;

[0015] One end of the capacitor C1 is electrically connected to one end of the resistor R1, and the other end of the capacitor C1 is electrically connected to one end of the capacitor C2;

[0016] The other end of the capacitor C2 is electrically connected to one end of the capacitor C3, and the other end of the capacitor C2 is grounded;

[0017] The other end of the capacitor C3 is electrically connected to the other end of the resistor R3.

[0018] As a preferred solution, the hysteresis comparison unit further includes a resistor R4, a resistor R5 and a resistor R6; wherein:

[0019] One end of the resistor R4 is electrically connected to the normal power output pin of the target hardware, and the other end of the resistor R4 is electrically connected to the positive input terminal of the hysteresis comparator;

[0020] The other end of the resistor R4 is electrically connected to one end of the resistor R5 , the other end of the resistor R5 is electrically connected to one end of the resistor R6 , and the other end of the resistor R6 is electrically connected to the first input end of the first switch unit.

[0021] As a preferred solution, the first switch unit includes a transistor Q1; wherein:

[0022] The base of the transistor Q1 is electrically connected to the output end of the hysteresis comparison unit as the first input end of the first switch unit;

[0023] The collector of the transistor Q1 is connected to the normal power output pin of the target hardware as the second input terminal of the first switch unit;

[0024] The emitter of the transistor Q1 is connected to the wake-up detection pin as the output end of the first switch unit;

[0025] The constant power output pin of the target hardware is electrically connected to one end of the resistor R7 , and the other end of the resistor R7 is electrically connected to the base of the transistor Q1 .

[0026] As a preferred solution, the wake-up circuit also includes a second switch unit, the first input end of the second switch unit is connected to the wake-up signal input pin, the second input end of the second switch unit is connected to the normal power output pin of the target hardware, and the output end of the second switch unit is connected to the wake-up pin of the target hardware.

[0027] As a preferred solution, the second switch unit includes a transistor Q2 and a diode D1, as well as resistors R8 and R9; wherein:

[0028] One end of the resistor R8 is electrically connected to the constant power output pin of the target hardware, and the other end of the resistor R8 is electrically connected to the base of the transistor Q2;

[0029] One end of the resistor R9 is electrically connected to the wake-up signal input pin, the other end of the resistor R9 is electrically connected to the collector of the transistor Q2, and the other end of the resistor R9 is electrically connected to the anode of the diode D1;

[0030] The cathode of the diode D1 is electrically connected to the wake-up pin of the target hardware;

[0031] The emitter of the transistor Q2 is grounded.

[0032] As a preferred solution, the second switch unit further includes a diode D2 and a resistor R10; wherein:

[0033] One end of the resistor R10 is electrically connected to the CAN interrupt signal pin, and the other end of the resistor R10 is electrically connected to the anode of the diode D2;

[0034] The cathode of the diode D2 is electrically connected to the wake-up pin of the target hardware.

[0035] As a preferred solution, the target hardware includes an NXP FS23 series system basis chip.

[0036] Furthermore, the present invention also provides a wake-up device, which includes the wake-up circuit provided by the present invention.

[0037] Compared with the prior art, the beneficial effects of the technical solution of the utility model are:

[0038] The utility model sets a hysteresis comparison unit, sets a hysteresis interval and configures a voltage comparison threshold according to the wake-up pin voltage threshold of the target hardware, judges the wake-up signal input by the wake-up signal input pin, and judges the wake-up signal when the voltage value of the wake-up signal is greater than or equal to the second threshold V configured by the hysteresis comparison unit. TH When the ignition signal is turned on, the hysteresis comparison unit outputs a low-level signal or a high-level signal to turn on the first switch unit, and the wake-up detection pin outputs a high-level signal that meets the voltage threshold of the WAKE pin and / or GPIO pin of the target hardware, thereby waking up the target hardware, thereby effectively preventing false wake-up actions caused by the jitter of the ignition signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 FIG. 1 is a circuit diagram of a wake-up circuit with an OR gate in the prior art.

[0040] Figure 2 FIG. 1 is a diagram illustrating an architecture of a wake-up circuit according to an embodiment of the present invention.

[0041] Figure 3 The figure is a circuit diagram of a wake-up circuit according to an embodiment of the present invention.

[0042] Figure 4 FIG. 4 is a circuit diagram of a second switch unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0044] The terms used in this utility model are for the purpose of describing specific embodiments only and are not intended to limit the utility model. As used in this utility model and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0045] It should be understood that although the terms first, second, third, etc. may be used in this utility model to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, first information can also be referred to as second information without departing from the scope of this utility model, and similarly, second information can also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when...", "when...", or "in response to determining."

[0046] The present invention is described in detail below with reference to the accompanying drawings and specific implementation methods.

[0047] Example 1

[0048] This embodiment proposes a wake-up circuit, such as Figure 2 FIG. 1 is a diagram showing the architecture of the wake-up circuit proposed in this embodiment.

[0049] The wake-up circuit proposed in this embodiment includes a hysteresis comparison unit and a first switch unit; wherein, the negative input end of the hysteresis comparison unit is connected to the wake-up signal input pin, and the positive input end of the hysteresis comparison unit is connected to the normal power output pin of the target hardware; the output end of the hysteresis comparison unit is connected to the first input end of the first switch unit, and the output end of the first switch unit is connected to the wake-up detection pin; the wake-up detection pin is connected to the WAKE pin and / or GPIO pin of the target hardware.

[0050] In this embodiment, a hysteresis comparison unit is set, and the hysteresis interval and voltage comparison threshold are set according to the wake-up pin voltage threshold of the target hardware. The hysteresis comparison unit compares the voltage signal input to the wake-up signal input pin. When the voltage signal is less than or equal to the first threshold V configured by the hysteresis comparison unit, the voltage comparison threshold is set. TL When the voltage signal is greater than or equal to the second threshold value V configured by the hysteresis comparison unit, the hysteresis comparison unit outputs a high level signal or a low level signal, the first switch unit is turned off, the wake-up detection pin outputs a low level signal, and the target hardware enters the sleep state; when the voltage signal is greater than or equal to the second threshold value V configured by the hysteresis comparison unit TH When the ignition signal is turned on, the hysteresis comparison unit outputs a low-level signal or a high-level signal to turn on the first switch unit, and the wake-up detection pin outputs a high-level signal that meets the voltage threshold of the WAKE pin and / or GPIO pin of the target hardware, thereby waking up the target hardware, thereby effectively preventing false wake-up actions caused by the jitter of the ignition signal.

[0051] Illustratively, the wake-up signal input pin in this embodiment is the IG_ON pin, and the input wake-up signal is an ignition signal.

[0052] Exemplarily, the wake-up detection pin in this embodiment is the IG_DET pin, and the output signal is a fixed voltage signal when an ignition signal is detected, which is used to wake up the target hardware by connecting to the WAKE pin of the target hardware, and to connect to the GPIO pin of the target hardware MCU. The MCU notifies the target hardware to sleep through SPI communication.

[0053] Illustratively, the hysteresis comparison unit in this embodiment may optionally adopt a hysteresis comparator, and its voltage hysteresis interval is set according to the application requirements of the target hardware.

[0054] Illustratively, the target hardware in this embodiment is a system basis chip.

[0055] For example, the target hardware in this embodiment includes an NXP FS23 series system basis chip, wherein the voltage threshold of the WAKE pin of the system basis chip is 2.97V, and the voltage signal output by the constant power output pin is 3.3V.

[0056] Further optionally, the first threshold V in the hysteresis comparison unit is set TL is 4.1V, the second threshold V TH is 4.3V.

[0057] When the wake-up signal input pin is on, the hysteresis comparator outputs a low or high signal, turning on the first switch unit. The wake-up detection pin then outputs a 3.3V high signal to the WAKE pin of the system base chip and the interrupt GPIO pin of the MCU, waking the system base chip and putting the entire device into operation. When the wake-up signal input pin is off, the hysteresis comparator outputs a high or low signal, turning off the first switch unit and causing the wake-up detection pin to output a low signal. Upon detecting the low signal, the interrupt GPIO pin of the MCU notifies the SBC to hibernate via SPI communication.

[0058] Among them, the WAKE pin and / or GPIO pin of the target hardware are all connected to the wake-up detection pin, which can avoid the high-resistance pull-down resistor configured inside the WAKE pin of the system basic chip, causing the WAKE pin status and the MCU's interrupt notification to be out of sync and delayed, thereby causing the system basic chip to be unable to enter the sleep state, and can avoid the whole machine consuming static current.

[0059] Example 2

[0060] This embodiment makes improvements based on the wake-up circuit proposed in embodiment 1. Figure 3 FIG. 1 is a circuit diagram of the wake-up circuit of this embodiment.

[0061] The wake-up circuit proposed in this embodiment includes a hysteresis comparison unit and a first switch unit; wherein, the negative input end of the hysteresis comparison unit is connected to the wake-up signal input pin, and the positive input end of the hysteresis comparison unit is connected to the normal power output pin of the target hardware; the output end of the hysteresis comparison unit is connected to the first input end of the first switch unit, and the output end of the first switch unit is connected to the wake-up detection pin; the wake-up detection pin is connected to the WAKE pin and / or GPIO pin of the target hardware.

[0062] Furthermore, the hysteresis comparison unit includes a hysteresis comparator and a voltage divider module; wherein:

[0063] The input end of the voltage divider module is connected to the wake-up signal input pin, and the output end of the voltage divider module is connected to the negative input end of the hysteresis comparator;

[0064] The positive input terminal of the hysteresis comparator is connected to the constant power output pin of the target hardware;

[0065] The output terminal of the hysteresis comparator is connected to the first input terminal of the first switch unit.

[0066] In this embodiment, the voltage divider module is used to configure the voltage hysteresis interval of the hysteresis comparison unit, which can be set according to the target hardware and its application scenario. TH With the first threshold VTL The difference is the voltage hysteresis range, V TL <V TH .

[0067] In this embodiment, the hysteresis comparator is used to compare the wake-up signal output from the wake-up signal input pin. When the voltage value of the wake-up signal is less than or equal to the first threshold value V configured by the hysteresis comparator, TL When the voltage value of the wake-up signal is greater than or equal to the second threshold value V configured by the hysteresis comparator, the hysteresis comparator outputs a high level signal or a low level signal, the first switch unit is turned off, the wake-up detection pin outputs a low level signal, and the target hardware enters the sleep state; when the voltage value of the wake-up signal is greater than or equal to the second threshold value V configured by the hysteresis comparator, the hysteresis comparator outputs a high level signal or a low level signal, ... TH When the hysteresis comparator outputs a low level signal or a high level signal, the first switch unit is turned on, and the wake-up detection pin outputs a high level signal that meets the voltage threshold of the WAKE pin and / or GPIO pin of the target hardware, thereby waking up the target hardware.

[0068] Furthermore, in an optional embodiment, the voltage divider module includes a resistor R1, a resistor R2, and a resistor R3 connected in series, and a capacitor C1, a capacitor C2, and a capacitor C3 connected in series; wherein:

[0069] One end of the resistor R1 is electrically connected to the wake-up signal input pin as the input end of the voltage divider module;

[0070] One end of the resistor R3 is electrically connected to the resistor R2, and the other end of the resistor R3 is electrically connected to the negative input end of the hysteresis comparator as the output end of the voltage divider module;

[0071] One end of the capacitor C1 is electrically connected to one end of the resistor R1, and the other end of the capacitor C1 is electrically connected to one end of the capacitor C2;

[0072] The other end of the capacitor C2 is electrically connected to one end of the capacitor C3, and the other end of the capacitor C2 is grounded;

[0073] The other end of the capacitor C3 is electrically connected to the other end of the resistor R3.

[0074] In this embodiment, by selecting appropriate resistance values of resistors R1, R2 and R3, when the input voltage changes, the voltage obtained by the voltage divider module can be within the first threshold value V TL and the second threshold V TH Switch between them to set different voltage hysteresis ranges.

[0075] Furthermore, in an optional embodiment, the hysteresis comparison unit further includes a resistor R4, a resistor R5, and a resistor R6; wherein:

[0076] One end of the resistor R4 is electrically connected to the normal power output pin of the target hardware, and the other end of the resistor R4 is electrically connected to the positive input terminal of the hysteresis comparator;

[0077] The other end of the resistor R4 is electrically connected to one end of the resistor R5 , the other end of the resistor R5 is electrically connected to one end of the resistor R6 , and the other end of the resistor R6 is electrically connected to the first input end of the first switch unit.

[0078] Among them, resistor R4 is used to adjust the voltage of the normal power signal input to the normal power output pin of the target hardware to adapt to the reference voltage requirement of the hysteresis comparator; resistors R5 and R6 further adjust the voltage of the normal power signal input to the normal power output pin of the target hardware.

[0079] In an optional embodiment, the first switch unit includes a transistor Q1; wherein:

[0080] The base of the transistor Q1 is electrically connected to the output end of the hysteresis comparison unit as the first input end of the first switch unit;

[0081] The collector of the transistor Q1 is connected to the normal power output pin of the target hardware as the second input terminal of the first switch unit;

[0082] The emitter of the transistor Q1 is connected to the wake-up detection pin as the output end of the first switch unit;

[0083] The constant power output pin of the target hardware is electrically connected to one end of the resistor R7 , and the other end of the resistor R7 is electrically connected to the base of the transistor Q1 .

[0084] Exemplarily, the hysteresis comparator is an inverting hysteresis comparator, and the transistor Q1 is a P-type transistor. A reference voltage is input to the non-inverting terminal of the hysteresis comparator, and a detection signal is input to the inverting terminal.

[0085] Exemplarily, the hysteresis comparator adopts TI's TLV7031QDCKRQ1 comparator; the transistor Q1 adopts S-LMBT3906LT1G.

[0086] When the input detection signal is higher than the second threshold V TH , the hysteresis comparator outputs a low-level signal, at this time the transistor Q1 is turned on, and the normal power input through the normal power output pin of the target hardware outputs a high-level signal to the wake-up detection pin to wake up the target hardware; when the input detection signal is lower than the first threshold V TL , the hysteresis comparator outputs a high-level signal, at this time the transistor Q1 is cut off, the wake-up detection pin outputs a low-level signal, and the target hardware enters the sleep state.

[0087] Example 3

[0088] This embodiment makes improvements based on the wake-up circuit proposed in Embodiment 1 or 2.

[0089] The wake-up circuit proposed in this embodiment includes a hysteresis comparison unit and a first switch unit; wherein, the negative input end of the hysteresis comparison unit is connected to the wake-up signal input pin, and the positive input end of the hysteresis comparison unit is connected to the normal power output pin of the target hardware; the output end of the hysteresis comparison unit is connected to the first input end of the first switch unit, and the output end of the first switch unit is connected to the wake-up detection pin; the wake-up detection pin is connected to the WAKE pin and / or GPIO pin of the target hardware.

[0090] Furthermore, the wake-up circuit also includes a second switch unit, a first input end of the second switch unit is connected to the wake-up signal input pin, a second input end of the second switch unit is connected to the normal power output pin of the target hardware, and an output end of the second switch unit is connected to the wake-up pin of the target hardware.

[0091] For example, Figure 4 FIG. 1 is a circuit diagram of the second switch unit of this embodiment.

[0092] It should be noted that, for example, in the NXP FS23 series system basis chip, when the VBOS pin of the system basis chip detects undervoltage, the system basis chip will enter the FALL SAFE state and enter the LPOFF state after 100ms. At this time, the system basis chip has no output, that is, its normal power output pin has no voltage output. At this time, the hysteresis comparator unit and the first switch unit cannot work normally, which leads to the inability to effectively detect the IG_ON signal and the inability to effectively wake up the system basis chip and the entire device.

[0093] The second switch unit added in this embodiment is used to maintain a normal wake-up function according to a hard-wired signal when the target hardware is in a sleep and undervoltage state.

[0094] Among them, when the target hardware is in sleep and undervoltage state, the normal power output pin of the target hardware has no signal output. At this time, the IG_ON signal input by the wake-up signal input pin activates and turns on the second switch unit, and wakes up the target hardware by connecting to the wake-up pin of the target hardware, effectively avoiding the problem of being unable to wake up due to the target hardware entering the LPOFF state, and ensuring the stability and reliability of the circuit.

[0095] In addition, the second switch unit added in this embodiment is independently provided to the wake-up module composed of the hysteresis comparison unit and the first switch unit, and does not affect the hysteresis interval setting value determination of the hysteresis comparison unit.

[0096] Furthermore, in an optional embodiment, the second switch unit includes a transistor Q2 and a diode D1, as well as a resistor R8 and a resistor R9; wherein:

[0097] One end of the resistor R8 is electrically connected to the constant power output pin of the target hardware, and the other end of the resistor R8 is electrically connected to the base of the transistor Q2;

[0098] One end of the resistor R9 is electrically connected to the wake-up signal input pin, the other end of the resistor R9 is electrically connected to the collector of the transistor Q2, and the other end of the resistor R9 is electrically connected to the anode of the diode D1;

[0099] The cathode of the diode D1 is electrically connected to the wake-up pin of the target hardware;

[0100] The emitter of the transistor Q2 is grounded.

[0101] Exemplarily, the transistor Q2 is an N-type transistor.

[0102] Among them, when the target hardware is in a sleep and undervoltage state, the normal power output pin of the target hardware has no signal output, and the transistor Q2 is cut off at this time; when the IG_ON signal is input, the diode D1 is turned on, and the wake-up pin WAKE2 of the target hardware outputs a high-level signal, thereby waking up the target hardware and making the target hardware output a normal power signal. The normal power output pin of the target hardware outputs a voltage signal normally, and the transistor Q2 is turned on. At this time, the second switch unit does not affect the operation of the hysteresis comparison unit and the first switch unit.

[0103] Furthermore, in an optional embodiment, the second switch unit further includes a diode D2 and a resistor R10; wherein:

[0104] One end of the resistor R10 is electrically connected to the CAN interrupt signal pin, and the other end of the resistor R10 is electrically connected to the anode of the diode D2;

[0105] The cathode of the diode D2 is electrically connected to the wake-up pin of the target hardware.

[0106] In this embodiment, the diode D2 is used as a switch element to connect the CAN interrupt signal pin to the wake-up pin of the target hardware, thereby being compatible with the CAN signal wake-up function.

[0107] Example 4

[0108] This embodiment provides a wake-up device, which includes the wake-up circuit provided in any one of Embodiments 1 to 3.

[0109] It can be understood that the wake-up circuit of this embodiment corresponds to any of the wake-up circuits proposed in the above embodiments 1 to 3. The options in the above embodiments 1 to 4 are also applicable to this embodiment, so they will not be described again here.

[0110] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. A person skilled in the art will be able to make other variations or modifications based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A wake-up circuit, characterized in that: It includes a hysteresis comparison unit and a first switch unit; wherein, the negative input end of the hysteresis comparison unit is connected to the wake-up signal input pin, and the positive input end of the hysteresis comparison unit is connected to the normal power output pin of the target hardware; the output end of the hysteresis comparison unit is connected to the first input end of the first switch unit, and the output end of the first switch unit is connected to the wake-up detection pin; the wake-up detection pin is connected to the WAKE pin and / or GPIO pin of the target hardware.

2. The wake-up circuit according to claim 1, wherein: The hysteresis comparison unit includes a hysteresis comparator and a voltage divider module; wherein: The input end of the voltage divider module is connected to the wake-up signal input pin, and the output end of the voltage divider module is connected to the negative input end of the hysteresis comparator; The positive input terminal of the hysteresis comparator is connected to the constant power output pin of the target hardware; The output terminal of the hysteresis comparator is connected to the first input terminal of the first switch unit.

3. The wake-up circuit according to claim 2, wherein: The voltage divider module includes resistors R1, R2, and R3 connected in series, and capacitors C1, C2, and C3 connected in series; wherein: One end of the resistor R1 is electrically connected to the wake-up signal input pin as the input end of the voltage divider module; One end of the resistor R3 is electrically connected to the resistor R2, and the other end of the resistor R3 is electrically connected to the negative input end of the hysteresis comparator as the output end of the voltage divider module; One end of the capacitor C1 is electrically connected to one end of the resistor R1, and the other end of the capacitor C1 is electrically connected to one end of the capacitor C2; The other end of the capacitor C2 is electrically connected to one end of the capacitor C3, and the other end of the capacitor C2 is grounded; The other end of the capacitor C3 is electrically connected to the other end of the resistor R3.

4. The wake-up circuit according to claim 2, wherein: The hysteresis comparison unit further includes a resistor R4, a resistor R5 and a resistor R6; wherein: One end of the resistor R4 is electrically connected to the normal power output pin of the target hardware, and the other end of the resistor R4 is electrically connected to the positive input terminal of the hysteresis comparator; The other end of the resistor R4 is electrically connected to one end of the resistor R5 , the other end of the resistor R5 is electrically connected to one end of the resistor R6 , and the other end of the resistor R6 is electrically connected to the first input end of the first switch unit.

5. The wake-up circuit according to claim 1, wherein: The first switch unit includes a transistor Q1; wherein: The base of the transistor Q1 is electrically connected to the output end of the hysteresis comparison unit as the first input end of the first switch unit; The collector of the transistor Q1 is connected to the normal power output pin of the target hardware as the second input terminal of the first switch unit; The emitter of the transistor Q1 is connected to the wake-up detection pin as the output end of the first switch unit; The constant power output pin of the target hardware is electrically connected to one end of the resistor R7 , and the other end of the resistor R7 is electrically connected to the base of the transistor Q1 .

6. The wake-up circuit according to any one of claims 1 to 5, characterized in that: The wake-up circuit also includes a second switch unit, a first input end of the second switch unit is connected to the wake-up signal input pin, a second input end of the second switch unit is connected to the normal power output pin of the target hardware, and an output end of the second switch unit is connected to the wake-up pin of the target hardware.

7. The wake-up circuit according to claim 6, characterized in that: The second switch unit includes a transistor Q2, a diode D1, and resistors R8 and R9; wherein: One end of the resistor R8 is electrically connected to the constant power output pin of the target hardware, and the other end of the resistor R8 is electrically connected to the base of the transistor Q2; One end of the resistor R9 is electrically connected to the wake-up signal input pin, the other end of the resistor R9 is electrically connected to the collector of the transistor Q2, and the other end of the resistor R9 is electrically connected to the anode of the diode D1; The cathode of the diode D1 is electrically connected to the wake-up pin of the target hardware; The emitter of the transistor Q2 is grounded.

8. The wake-up circuit according to claim 7, characterized in that: The second switch unit further includes a diode D2 and a resistor R10; wherein: One end of the resistor R10 is electrically connected to the CAN interrupt signal pin, and the other end of the resistor R10 is electrically connected to the anode of the diode D2; The cathode of the diode D2 is electrically connected to the wake-up pin of the target hardware.

9. The wake-up circuit according to any one of claims 1 to 5, characterized in that: The target hardware includes the NXP FS23 series system basis chip.

10. A wake-up device, characterized in that: The wake-up circuit comprises the wake-up circuit according to any one of claims 1 to 9.

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