Capacitor and semiconductor device

Abstract

The utility model provides a capacitor. The capacitor comprises a bottom capacitor pole plate, wherein the bottom capacitor pole plate comprises a rough upper surface of which the root mean square (RMS) surface roughness is at least 1.14; a capacitor dielectric layer on the bottom capacitor plate and contacting the rough upper surface of the bottom capacitor plate; and an upper capacitor plate on the capacitor dielectric layer. A semiconductor device includes a transistor on a substrate; a dielectric layer on the transistor; and a capacitor in the dielectric layer and including a bottom capacitor plate connected to the source region of the transistor and having a rough upper surface having a root mean square surface roughness of at least 1.14.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated circuit, and more particularly to a capacitor and a semiconductor device. Background Art

[0002] Semiconductor devices that utilize on-chip capacitors include, for example, dynamic random access memory (DRAM), voltage controlled oscillators (VCOs), phase-locked loops (PLLs), operational amplifiers (OP-AMPs), and switching / switched capacitors (SCs). These on-chip capacitors can also be used to decouple electrical noise generated by or transmitted from other components of the semiconductor device within digital and analog integrated circuits (ICs).

[0003] Capacitor structures used in ICs have evolved from the original parallel plate capacitor structure (having two conductive layers separated by a dielectric) to more complex capacitor designs that meet the high capacitance specifications of increasingly smaller devices. These more complex designs include, for example, metal-oxide-metal (MOM) capacitor designs and interdigitated finger MOM capacitor structures. Capacitors utilized in DRAM devices may include, for example, trench capacitors. In trench capacitors, the capacitor dielectric separates the capacitor plates within a trench. Utility Model Content

[0004] A capacitor according to an embodiment of the present invention includes a bottom capacitor plate, a capacitor dielectric layer, and an upper capacitor plate. The bottom capacitor plate includes a roughened upper surface having a root mean square (RMS) surface roughness of at least 1.14. The capacitor dielectric layer is positioned on the bottom capacitor plate and contacts the roughened upper surface of the bottom capacitor plate. The upper capacitor plate is positioned on the capacitor dielectric layer.

[0005] A semiconductor device according to an embodiment of the present invention includes a transistor, a dielectric layer, and a capacitor. The transistor is located on a substrate. The dielectric layer is located on the transistor. The capacitor is located in the dielectric layer and includes a bottom capacitor plate connected to a source region of the transistor and having a roughened upper surface with a root mean square (RMS) surface roughness of at least 1.14.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A A vertical cross-sectional view of a semiconductor device according to one or more embodiments is shown.

[0009] Figure 1B is a detailed vertical cross-sectional view of a lower corner region of a capacitor according to one or more embodiments.

[0010] Figure 1C is a horizontal cross-sectional view of a capacitor according to one or more embodiments.

[0011] Figure 2A is an intermediate structure after forming a gate structure and source / drain regions according to one or more embodiments.

[0012] Figure 2B is an intermediate structure after forming a first source / drain contact, a second source / drain contact, and a gate electrode contact according to one or more embodiments.

[0013] Figure 2C is an intermediate structure after forming a second dielectric layer and trenches according to one or more embodiments.

[0014] Figure 2D is an intermediate structure after forming the bottom capacitor plate according to one or more embodiments.

[0015] Figure 2E is an intermediate structure after forming a capacitor dielectric layer and an upper capacitor plate according to one or more embodiments.

[0016] Figure 2F is an intermediate structure after forming a third dielectric layer according to one or more embodiments.

[0017] Figure 3A method of manufacturing a semiconductor device according to one or more embodiments is illustrated.

[0018] Figure 4 is a detailed cross-sectional view of a portion of a capacitor having an alternative design according to one or more embodiments.

[0019] Figure 5 is a vertical cross-sectional view of a semiconductor device having a first alternative design according to one or more embodiments.

[0020] Figure 6 is a vertical cross-sectional view of a semiconductor device having a second alternative design according to one or more embodiments.

[0021] Figure 7 is a schematic diagram of a semiconductor device having a third alternative design according to one or more embodiments.

[0022] Figure 8 is a schematic diagram of a semiconductor device having a fourth alternative design according to one or more embodiments. DETAILED DESCRIPTION

[0023] The following disclosure provides many different embodiments or examples for implementing the different features of the provided objects. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed to be in direct contact and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself represent a relationship between the various embodiments and / or configurations discussed.

[0024] For ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one component or feature shown in the figures to another component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to be of the same material composition and having a thickness within the same thickness range. The term "source / drain region" may refer to the source or drain individually or collectively, depending on the context.

[0025] A typical DRAM device may include an array of memory cells, each of which may include a charge storage device (e.g., a capacitor) coupled to a charge access device (e.g., a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), etc.). Such a device may be referred to as a 1T1C device (one transistor, one capacitor device). The source electrode of the transistor may be connected to one plate of the storage capacitor. The drain electrode of the transistor may be connected to a conductive bit line. The gate electrode of the transistor may be connected to a conductive word line.

[0026] In operation, a logical 1 or a logical 0 can be written to or read from a memory cell of a DRAM device. To access or select a particular memory cell, the interdigitated word and bit lines of the transistors associated with the designated memory cell are energized to write or read the value stored on a capacitor coupled to an access / select transistor. During a write operation, the access transistor is turned on by applying a given potential to the word line, and the given charge applied to the bit line is then deposited on the capacitor plate and stored. Conversely, during a read operation, the word line again enables the access transistor, and the presence of charge on the capacitor can be sensed by appropriate circuitry and recognized as a 1 or 0.

[0027] Some DRAM devices may utilize planar storage capacitors. However, such DRAM devices may occupy a large wafer surface area. Other DRAM devices may use stacked capacitors to achieve higher capacitance with a reduced size. Stacked capacitors can be formed on top of transistors, enabling the construction of smaller cells without sacrificing storage capacity.

[0028] Some DRAM devices may use trench capacitors to achieve higher capacitance with a reduced size. Trench capacitors can be formed in trenches or cavities extending vertically into the substrate of the integrated circuit and can be formed by various etching processes. Such trench capacitors can increase the plate area and thus the capacitance by increasing the vertical extension of the metal plate surface rather than the horizontal extension. The first plate of such a trench capacitor can be defined by the surface of the inner wall of a doped region in the substrate that can form a trench. Although such inner wall forms the plate boundary, charge can also be stored in a depletion region formed below the wall surface and extending into the doped substrate. The opposing second plate of the trench capacitor (which can also be a storage plate) can be a conductive core that can be formed within the trench. An oxide layer can first be formed over the inner trench wall to use the oxide layer as a dielectric and insulate the first plate from the second plate.

[0029] Conventional DRAM devices may occupy a large amount of silicon substrate area. They may also require complex manufacturing processes that utilize high temperatures, resulting in high manufacturing costs. In addition, the capacitors used by DRAM devices for information storage may have relatively low capacitance. For example, a DRAM device that utilizes plate capacitors may require a large area and may not be able to reliably achieve a large capacitance. A DRAM device that utilizes finger capacitors may require a large area, have pitch limitations, and have low dielectric constant insulators. A DRAM device that utilizes trench capacitors may be limited by via size, via depth, and high-k dielectric thickness.

[0030] One or more embodiments of the present disclosure may include a capacitor having a capacitance that is significantly greater than that of conventional capacitors. The capacitor may include a bottom capacitor plate comprising a roughened upper surface having a root mean square (RMS) surface roughness of at least 1.14. The roughened upper surface may increase the surface area of the bottom capacitor plate, and the increased surface area may increase the capacitance of the capacitor. The capacitor may also include: a capacitor dielectric layer located on the bottom capacitor plate and contacting the roughened upper surface of the bottom capacitor plate; and an upper capacitor plate located on the capacitor dielectric layer.

[0031] One or more embodiments may further include a semiconductor device, such as a three-dimensional (3D) stacked DRAM device. The semiconductor device may include a transistor located on a substrate. The transistor may include, for example, a low-temperature processed select transistor. A dielectric layer comprising, for example, a high-k dielectric material may be formed on the transistor. The semiconductor device may further include the above-mentioned capacitor located in the dielectric layer and electrically coupled to the transistor. The capacitor may include, for example, a trench capacitor. In at least one embodiment, the capacitor may include a bottom capacitor plate connected to the first source / drain region of the transistor and having a rough upper surface having a root mean square (RMS) surface roughness of at least 1.14.

[0032] Semiconductor devices can utilize capacitors as information storage. These devices can include very simple structures that enable them to increase surface area (e.g., the surface area of the bottom capacitor plate). This significantly increases the capacitance of the capacitor, providing high performance.

[0033] Furthermore, compared to conventional methods, the method for manufacturing a semiconductor device can utilize a simple (e.g., easy) and inexpensive process and may not require any additional masks or additional processes. Specifically, one or more embodiments are fully compatible with conventional processes including back-end of line (BEOL) processes.

[0034] One or more of the embodiments may include a method of manufacturing a semiconductor device, such as a DRAM device. The method may include forming a capacitor having a bottom capacitor plate, a capacitor dielectric layer located on the bottom capacitor plate, and an upper capacitor plate located on the capacitor dielectric layer. The bottom capacitor plate and / or the upper capacitor plate may include a TiN layer. The roughened upper surface of the bottom capacitor plate may include the upper surface of the TiN layer. In at least one embodiment, the bottom capacitor plate and / or the upper capacitor plate may be formed by atomic layer deposition (aALD). In at least one embodiment, the bottom capacitor plate and / or the upper capacitor plate may be formed by plasma enhanced atomic layer deposition (PEALD).

[0035] The capacitor may include multiple TiN layers having the same or different RMS surface roughness. In at least one embodiment, the bottom capacitor plate may include a first TiN layer having a first RMS surface roughness (e.g., at least 1.14) and the upper capacitor plate may include a second TiN layer having a second RMS surface roughness that is the same as or different from the first RMS surface roughness (e.g., greater than or less than the first RMS surface roughness).

[0036] The TiN layer can be formed by PEALD to have a surface roughness that is greater than, for example, the surface roughness of a TiN layer formed by thermal atomic layer deposition (THALD) or physical vapor deposition (PVD). Thus, the surface area of the TiN layer formed by PEALD can be greater than the surface area of the TiN layer formed by THALD or PVD. Thus, a capacitor having a bottom capacitor plate including a TiN layer formed by PEALD has a capacitance that is greater than the capacitance of a capacitor including a TiN layer formed by THALD or PVD. In at least one embodiment, the capacitance of a capacitor including a TiN layer formed by PEALD can have a capacitance of 10.52 femtofarads or greater, compared to a capacitance of approximately 9.97 femtofarads or less when the TiN layer is formed by THALD.

[0037] One or more embodiments may include an embedded capacitor including a TiN layer formed by PEALD. In at least one embodiment, the bottom capacitor plate (e.g., a roughened electrode) of the embedded capacitor may include a TiN layer formed by PEALD. The embedded capacitor may be included in a 3D embedded transistor-capacitor structure, such as a semiconductor device (e.g., a DRAM device), for example.

[0038] One or more embodiments may be used, for example, in logic devices, memory devices, or any circuit requiring large capacitance, such as DRAM, electrostatic discharge (ESD) devices, and radio frequency (RF) devices. One or more embodiments may also be included, for example, in BEOL transistor-capacitor circuits, such as eDRAM, ESD devices, and RF devices.

[0039] With reference to the accompanying drawings, Figure 1A A vertical cross-sectional view of a semiconductor device 100 according to one or more embodiments is shown. The semiconductor device 100 may include, for example, a transistor 120 and a capacitor 160, which together constitute a 1-transistor / 1-capacitor (1T1C) memory cell or a DRAM cell in a DRAM device. The transistor 120 and the capacitor 160 may include BEOL devices formed in a BEOL process.

[0040] like Figure 1AAs shown in FIG, semiconductor device 100 may include front-end ofline (FEOL) device circuitry 12 and BEOL device circuitry 14 located above FEOL device circuitry 12. FEOL device circuitry 12 may be fabricated on and / or on a substrate (not shown), such as a semiconductor substrate, such as a silicon wafer. FEOL device circuitry 12 may include one or more transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) (not shown), in an active device region of the substrate. The semiconductor substrate may comprise any material known to be suitable for fabricating MOSFET circuitry, such as, but not limited to, Group IV materials (e.g., substantially pure silicon, substantially pure germanium, and SiGe alloys ranging from primarily Si to primarily Ge).

[0041] FEOL device circuitry 12 may also include one or more dielectric material layers 11 and one or more layers of interconnect metallization 10, formed within and electrically insulated from dielectric material layer 11. Interconnect metallization 10 may comprise any metal suitable for interconnecting FEOL and / or BEOL integrated circuits. Interconnect metallization 10 may comprise, for example, a predominantly Cu alloy, a predominantly W alloy, or a predominantly Al alloy. Dielectric material layer 11 may comprise any dielectric material known to be suitable for electrical insulation of monolithic ICs. In some embodiments, dielectric material layer 11 may comprise silicon and may contain at least one of oxygen and nitrogen. Dielectric material layer 11 may comprise, for example, SiO, SiN, or SiON. Dielectric material layer 11 may also be a low-K dielectric material (e.g., having a lower dielectric constant than SiO2).

[0042] like Figure 1A As further shown in FIG. 1 , BEOL device circuitry 14 may include transistor 120 and capacitor 160 of a DRAM cell. BEOL device circuitry 14 may include any number of metallization layers above FEOL device circuitry 12. Transistor 120 may be located in dielectric layer 101. Dielectric layer 101 may include a material substantially similar to that of dielectric material layer 11 in FEOL device circuitry 12. Note that, alternatively, the DRAM cell may be located in FEOL device circuitry 12 rather than in BEOL device circuitry 14.

[0043] Transistor 120 may include a field effect transistor, such as a MOSFET. In at least one embodiment, the transistor may include a low temperature processed select transistor for a DRAM cell. Transistor 120 may be formed on a layer of crystalline semiconductor material 102 (e.g., a semiconductor substrate or substrate) located in dielectric layer 101. Semiconductor material layer 102 may include at least a channel region of transistor 120. Semiconductor material layer 102 may have a microstructure associated with a seed structure (not shown) in dielectric layer 101.

[0044] The semiconductor material layer 102 may comprise a p-type, n-type, or intrinsic semiconductor material. The semiconductor material layer 102 may comprise a Group IV semiconductor material, such as silicon (Si), germanium (Ge), and alloys (e.g., SiGe, GeSn, and SiGeSn). The semiconductor material layer 102 may have a melt temperature of at least 50° C. Localized / rapid thermal techniques may be employed to generate a very high thermal gradient between the semiconductor material layer 102 and the underlying material to crystallize the semiconductor material of the semiconductor material layer 102 with minimal impact on the FEOL device circuitry 12 or the interconnect metallization 10. The thickness of the semiconductor material layer 102 may vary, but in one or more embodiments may be less than 50 nanometers, and advantageously less than 30 nanometers (e.g., in a range from 5 nanometers to 25 nanometers).

[0045] The transistor 120 may include a gate structure 121 located on the semiconductor material layer 102 and a pair of source / drain regions 128 adjacent to the gate structure 121 (e.g., located on opposite sides of the gate structure 121) in the semiconductor material layer 102. The gate structure 121 may include a gate insulating layer 122 (e.g., a gate oxide layer) located on a surface of the semiconductor material layer 102. The gate insulating layer 122 may include one or more metal oxides, such as (Al2O3, HfO2, MgO x and LaO x ) and / or mixed metal oxides (such as HfAlO x Additionally or alternatively, the gate insulating layer 122 may include a thermal oxide layer. The gate insulating layer 122 may have a thickness ranging from about 50 angstroms to 100 angstroms.

[0046] The gate structure 121 may further include a gate electrode 123 located on the gate insulating layer 122. The gate electrode 123 may include a conductive material, such as polysilicon, a silicide material, a metal material, or a metal composite material. The gate electrode 123 may also include alloy components such as C, Ta, W, Pt, and Sn. The gate electrode 123 may include a metal nitride (e.g., WN, TiN, or TaN) and may also include Al (e.g., TiAlN). In at least one embodiment, the gate electrode 123 may include a doped polysilicon layer (e.g., doped with arsenic, phosphorus, etc.). Other suitable conductive materials are also within the contemplated scope of the present disclosure. The gate electrode 123 may have a thickness in the range of from about 500 angstroms to 2000 angstroms.

[0047] The gate structure 121 may further include a silicide layer 125 located on the gate electrode 123. The silicide layer 125 may include a refractory metal silicide (e.g., tungsten silicide). The silicide layer 125 may also have a thickness ranging from approximately 500 angstroms to 2000 angstroms. The gate structure 121 may also include sidewall spacers 126 located on the sidewalls of the gate electrode 123 and the sidewalls of the silicide layer 125. The sidewall spacers 126 may include, for example, one or more layers of silicon oxide (e.g., SiO2) and / or silicon nitride (e.g., Si3N4), silicon oxynitride, or any known low-k material. Other suitable materials are also contemplated by the present disclosure.

[0048] Transistor 120 may further include source / drain regions 128 located in semiconductor material layer 102. In the case where semiconductor material layer 102 includes a p-type substrate, source / drain regions 128 may include n-type source / drain regions. Source / drain regions 128 may be doped with dopant ions such as arsenic and phosphorus. Source / drain regions 128 may include lightly doped extension regions (not shown) adjacent to gate structure 121 and located below sidewall spacers 126. A silicide layer (not shown) may be formed on the upper surface of source / drain regions 128 to reduce contact resistance.

[0049] Semiconductor device 100 may further include a first dielectric layer 131 located on semiconductor material layer 102 and above gate structure 121. First dielectric layer 131 may comprise a material substantially similar to dielectric material layer 11 in FEOL device circuitry 12. In at least one embodiment, first dielectric layer 131 may comprise an interlayer dielectric (ILD) and may be formed of a dielectric material such as silicon dioxide (SiO2). Other suitable dielectric materials are contemplated by the present disclosure. First dielectric layer 131 may have a thickness ranging from 3 nanometers to 20 nanometers.

[0050] The semiconductor device 100 may also include a contact metallization 130 that may electrically couple the transistor 120. The contact metallization 130 may include a first source / drain contact 132, a second source / drain contact 134, and a gate electrode contact 136. The first source / drain contact 132 may be connected to a source / drain region 128. The second source / drain contact 134 may be connected to another source / drain region 128. The gate electrode contact 136 may be connected to the gate electrode 123 through the silicide layer 125. In at least one embodiment, the first source / drain contact 132 may be connected to the source of the source / drain region 128, and the second source / drain contact 134 may be connected to the drain of the source / drain region 128. In at least one embodiment, the second source / drain contact 134 can connect the drain of the source / drain region 128 to a bit line (not shown) of the DRAM device, and the gate electrode contact 136 can connect the gate electrode 123 to a word line (not shown) of the DRAM device.

[0051] The contact metallization 130 may have any composition known to provide suitable contact with the semiconductor material. The contact metallization 130 may form a Schottky or ohmic junction with the source / drain semiconductor material of the source / drain region 128. The contact metallization 130 may comprise, for example, one or more metals or metal compounds. In some embodiments, the contact metallization 130 may comprise a metal nitride at the interface of the source / drain region 128 (i.e., in direct contact with the source / drain region 128). The metal nitride may include TiN, TaN, and WN. The contact metallization 130 may also or alternatively comprise a noble metal (e.g., Pt) at the interface of the source / drain region 128 (i.e., in direct contact with the source / drain region 128). Other suitable metal materials are also within the contemplation of the present disclosure.

[0052] Semiconductor device 100 may further include a second dielectric layer 151 disposed on first dielectric layer 131. An etch stop layer (not shown) comprising, for example, silicon carbide, silicon nitride, or a similar material may be disposed on first dielectric layer 131. In this case, second dielectric layer 151 may be disposed on the etch stop layer. Second dielectric layer 151 may comprise a material substantially similar to that of dielectric material layer 11 in FEOL device circuitry 12. Second dielectric layer 151 (e.g., an ILD layer) may be formed of a dielectric material such as silicon oxide. Other suitable dielectric materials are contemplated by the present disclosure. Second dielectric layer 151 may have a thickness ranging from 50 nanometers to 2500 nanometers.

[0053] The second dielectric layer 151 may include a trench 152 extending substantially perpendicularly (e.g., in the z-direction) to the surface of the semiconductor material layer 102. The trench 152 may have a substantially cylindrical shape extending axially perpendicularly to the surface of the semiconductor material layer 102. The depth of the trench 152 (e.g., in the z-direction) may be in a range from 50 nanometers to 2500 nanometers. The trench 152 may extend over the entire thickness of the second dielectric layer 151. That is, the depth of the trench 152 may be substantially equal to the thickness of the second dielectric layer 151. The width (e.g., diameter) of the trench 152 may be in a range from 20 nanometers to 200 nanometers.

[0054] The trench 152 may have a trench bottom 152a that is partially formed by the upper surface of the first dielectric layer 131 and partially formed by the upper surface of the first source / drain contact 132. The trench bottom 152a may have a substantially circular shape. Figure 1A As shown in FIG, the width of the trench 152 (and therefore the width of the trench bottom 152a) can be greater than the width of the first source / drain contact 132. The trench 152 can also include trench sidewalls 152b extending substantially vertically from the trench bottom 152a. The length of the trench sidewalls 152b (e.g., in the z-direction) can be substantially equal to the depth of the trench 152.

[0055] Capacitor 160 may be located in trench 152. Capacitor 160 may include a bottom capacitor plate 162, a capacitor dielectric layer 164 located on bottom capacitor plate 162, and an upper capacitor plate 166 located on capacitor dielectric layer 164. Capacitor 160 may substantially fill trench 152 and may therefore have a size and shape substantially similar to that of trench 152. Specifically, capacitor 160 may have a substantially cylindrical shape extending axially perpendicular to the surface of semiconductor material layer 102.

[0056] Capacitor 160 may have a length Lc ranging from 50 nanometers to 2500 nanometers and may be substantially equal to the thickness of second dielectric layer 151. Capacitor 160 may have a width Wc (e.g., diameter) ranging from 20 nanometers to 200 nanometers. In at least one embodiment, capacitor 160 may have a capacitance of at least 10.52 femtofarads. In at least one embodiment, capacitor 160 may be used as an information storage element in a DRAM cell.

[0057] Bottom capacitor plate 162 may include a bottom capacitor plate bottom portion 162a and a bottom capacitor plate sidewall portion 162b extending substantially perpendicularly to bottom capacitor plate bottom portion 162a. Bottom capacitor plate 162 may have a substantially uniform thickness across bottom capacitor plate bottom portion 162a and bottom capacitor plate sidewall portion 162b. In at least one embodiment, the thickness of bottom capacitor plate 162 may range from 2 nanometers to 150 nanometers. Bottom capacitor plate bottom portion 162a may be located on trench bottom 152a, and bottom capacitor plate sidewall portion 162b may be located on trench sidewall 152b.

[0058] Bottom capacitor plate bottom portion 162a can contact the upper surface of first source / drain contact 132. In at least one embodiment, an inner portion (e.g., an inner diameter portion) of bottom capacitor plate bottom portion 162a can contact the upper surface of first source / drain contact 132 and an outer portion (e.g., an outer diameter portion) of bottom capacitor plate bottom portion 162a can contact the upper surface of second dielectric layer 151.

[0059] It should be noted that in one or more embodiments, the bottom capacitor plate bottom portion 162a may not necessarily contact the upper surface of the first source / drain contact 132. One or more intermediate dielectric layers (e.g., intermetallic dielectric (IMD) layers) may be present between the first dielectric layer 131 and the second dielectric layer 151. In this case, the bottom capacitor plate bottom portion 162a may be electrically coupled to the upper surface of the first source / drain contact 132 via one or more metal layers in the one or more intermediate dielectric layers.

[0060] In at least one embodiment, the center point of the bottom capacitor plate bottom portion 162a can be substantially aligned with the center point of the upper surface of the first source / drain contact 132. That is, the bottom capacitor plate bottom portion 162a and the upper surface of the first source / drain contact 132 can be arranged concentrically. In at least one embodiment, the first source / drain contact 132 can be connected to the source of the source / drain region 128, and the bottom capacitor plate 162 is electrically coupled to the source through the first source / drain contact 132.

[0061] The bottom capacitor plate 162 may be formed from one or more layers of a conductive material, such as a metal or metal alloy. The conductive material may include, for example, Al, Ta, Ag, Cu, W, Co, Pd, Pt, Ni, Nb, other low-resistivity metal compositions, alloys thereof, or combinations thereof. In at least one embodiment, the bottom capacitor plate 162 may include a layer of TiN. Other suitable metal materials are also within the contemplation of the present disclosure. The bottom capacitor plate 162 may also include a roughened upper surface 162s. In at least one embodiment, the bottom capacitor plate 162 may include a layer of TiN, and the roughened upper surface 162s may include the upper surface of the layer of TiN. In at least one embodiment, the roughened upper surface may have a root mean square (RMS) surface roughness of at least 1.14.

[0062] Capacitor dielectric layer 164 may include a capacitor dielectric layer bottom portion 164a and a capacitor dielectric layer sidewall portion 164b extending substantially perpendicularly to capacitor dielectric layer bottom portion 164a. Capacitor dielectric layer 164 may also include a capacitor dielectric layer upper portion 164c located on the upper surface of second dielectric layer 151 outside trench 152. Capacitor dielectric layer upper portion 164c may also be formed on the end of bottom capacitor plate sidewall portion 162b. The length (in the x-direction) of capacitor dielectric layer upper portion 164c may be at least three times the thickness of bottom capacitor plate 162.

[0063] The capacitor dielectric layer 164 can have a substantially uniform thickness across the capacitor dielectric layer bottom portion 164a, the capacitor dielectric layer sidewall portion 164b, and the capacitor dielectric layer upper portion 164c. The thickness of the capacitor dielectric layer 164 can be less than the thickness of the bottom capacitor plate 162. In at least one embodiment, the thickness of the capacitor dielectric layer 164 can range from 2 nanometers to 20 nanometers. The capacitor dielectric layer bottom portion 164a can be located on the bottom capacitor plate bottom portion 162a, and the capacitor dielectric layer sidewall portion 164b can be located on the bottom capacitor plate sidewall portion 162b.

[0064] The capacitor dielectric layer 164 can be formed from one or more layers of dielectric material (e.g., a low-k dielectric material, a high-k dielectric material, etc.). The dielectric material can include, for example, hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, etc. Other suitable metal materials are also within the contemplation of the present disclosure. The capacitor dielectric layer 164 can also include a lower surface 164s, which can contact the roughened upper surface 162s of the bottom capacitor plate 162. The lower surface 164s of the capacitor dielectric layer 164 can be located on the capacitor dielectric layer bottom portion 164a and the capacitor dielectric layer sidewall portion 164b.

[0065] Upper capacitor plate 166 may include an upper capacitor plate bottom portion 166a and an upper capacitor plate sidewall portion 166b extending substantially perpendicularly from upper capacitor plate bottom portion 166a. Upper capacitor plate 166 may also include an upper capacitor plate upper portion 166c located outside trench 152 on capacitor dielectric layer upper portion 164c. An end of upper capacitor plate upper portion 166c may have an end substantially aligned with an end of capacitor dielectric layer upper portion 164c. The length (in the x-direction) of upper capacitor plate upper portion 166c may be substantially the same as the length of capacitor dielectric layer upper portion 164c.

[0066] The upper capacitor plate 166 can have a substantially uniform thickness across the upper capacitor plate bottom portion 166a, the upper capacitor plate sidewall portion 166b, and the upper capacitor plate upper portion 166c. In at least one embodiment, the thickness of the upper capacitor plate 166 can vary among the upper capacitor plate bottom portion 166a, the upper capacitor plate sidewall portion 166b, and the upper capacitor plate upper portion 166c. For example, the thickness of the upper capacitor plate bottom portion 166a may be different from (e.g., greater than or less than) the thickness of the upper capacitor plate sidewall portion 166b and / or the thickness of the upper capacitor plate upper portion 166c, the thickness of the upper capacitor plate sidewall portion 166b may be different from the thickness of the upper capacitor plate bottom portion 166a and / or the thickness of the upper capacitor plate upper portion 166c, and the thickness of the upper capacitor plate upper portion 166c may be different from the thickness of the upper capacitor plate bottom portion 166a and / or the thickness of the upper capacitor plate sidewall portion 166b.

[0067] In at least one embodiment, the thickness of upper capacitor plate 166 can be substantially the same as the thickness of bottom capacitor plate 162. In at least one embodiment, the thickness of upper capacitor plate 166 can be greater than the thickness of capacitor dielectric layer 164 and less than the thickness of bottom capacitor plate 162. In at least one embodiment, the thickness of upper capacitor plate 166 can be in a range from 2 nanometers to 150 nanometers. Upper capacitor plate bottom portion 166a can be located on capacitor dielectric layer bottom portion 164a and upper capacitor plate sidewall portion 166b can be located on capacitor dielectric layer sidewall portion 164b.

[0068] The upper capacitor plate 166 can be formed from one or more layers of a conductive material, such as a metal or metal alloy. The conductive material can include, for example, Al, Ta, Ag, Cu, W, Co, Pd, Pt, Ni, Nb, other low-resistivity metal compositions, alloys thereof, or combinations thereof. In at least one embodiment, the upper capacitor plate 166 can be formed from substantially the same material as the bottom capacitor plate 162. In at least one embodiment, the upper capacitor plate 166 can include a layer of TiN. Other suitable metal materials are also contemplated by the present disclosure.

[0069] Capacitor 160 may include multiple TiN layers having the same or different RMS surface roughness. In at least one embodiment, bottom capacitor plate 162 may include a first TiN layer having a first RMS surface roughness (e.g., at least 1.14) and upper capacitor plate 166 may include a second TiN layer having a second RMS surface roughness that is the same as or different from the first RMS surface roughness (e.g., greater than or less than the first RMS surface roughness).

[0070] Semiconductor device 100 may further include a third dielectric layer 171 located on second dielectric layer 151. Third dielectric layer 171 may comprise a material substantially similar to the dielectric material layer 11 in FEOL device circuitry 12. Third dielectric layer 171 (e.g., an ILD layer) may be formed of a dielectric material such as silicon oxide. Other suitable dielectric materials are contemplated within the present disclosure. Third dielectric layer 171 may have a thickness ranging from 50 nanometers to 2500 nanometers.

[0071] The third dielectric layer 171 may include a third dielectric layer protrusion 171p that protrudes downward into the capacitor 160. Specifically, a groove may be located in a central portion of the capacitor 160 located on the upper capacitor plate 166. The third dielectric layer protrusion 171p may protrude onto the upper capacitor plate 166 in the central portion of the capacitor 160 and fill the groove.

[0072] Figure 1B FIG is a detailed vertical cross-sectional view of the lower corner region of capacitor 160 according to one or more embodiments. Figure 1BAs shown in , capacitor 160 may include an interface between a roughened upper surface 162s of a bottom capacitor plate 162 and a lower surface 164s of a capacitor dielectric layer 164. The interface may have an interdigitated design in which a plurality of protrusions 164s-P of the lower surface 164s of the capacitor dielectric layer 164 respectively protrude into recessed portions 162s-R of the roughened upper surface 162s of the bottom capacitor plate 162. The recessed portions 162s-R may include one or more grooves (e.g., a plurality of grooves) in the roughened upper surface 162s. The interface may be located over substantially the entire roughened upper surface 162s of the bottom capacitor plate 162.

[0073] like Figure 1B As shown in FIG, the recessed portion 162s-R (and the plurality of protrusions 164s-P) may have an irregular configuration. That is, the grooves in the recessed portion 162s-R may have different depths and widths. The spacing between the grooves may also vary.

[0074] Furthermore, in at least one embodiment, the thickness of the capacitor dielectric layer 164 may be less than the depth of the recess 162s-R, and therefore, the recess 162s-R may not be filled. In this case, the upper capacitor plate 166 may also protrude into the one or more recesses of the recessed portion 162s-R. Furthermore, in at least one embodiment, the combined thickness of the capacitor dielectric layer 164 and the upper capacitor plate 166 may be less than the depth of the recess 162s-R, and the recess 162s-R may not be filled. In this case, the third dielectric layer protrusion 171p may protrude into the one or more recesses of the recessed portion 162s-R on the upper capacitor plate 166.

[0075] Figure 1C 1 is a horizontal cross-sectional view of a capacitor 160 according to one or more embodiments. For ease of understanding, the ends of the upper portion 164c of the capacitor dielectric layer and the ends (eg, coextensive ends) of the upper portion 166c of the upper capacitor plate are positioned at Figure 1C Indicated by dotted line.

[0076] like Figure 1C As shown in FIG, trench 152 may be filled with components of capacitor 160. In at least one embodiment, third dielectric layer protrusion 171p, upper capacitor plate sidewall portion 166b, capacitor dielectric layer sidewall portion 164b, and bottom capacitor plate sidewall portion 162b may all be formed concentrically. The end of capacitor dielectric layer upper portion 164c and the end of upper capacitor plate upper portion 166c may also be formed concentrically with trench 152 and the components of capacitor 160 located within trench 152.

[0077] Figures 2A to 2FSequential operations of a method of forming a semiconductor device (eg, a DRAM memory cell) are shown according to one or more embodiments. Figures 2A to 2F The method shown in FIG. 1 may illustrate the formation of one memory cell including transistor 120 and capacitor 160. However, the method is not limited to this configuration. The embodiment methods described herein may be used to form (e.g., simultaneously form) any number of DRAM memory cells.

[0078] Figure 2A is an intermediate structure after forming the gate structure 121 and the source / drain regions 128 according to one or more embodiments. A FEOL device circuitry 12 including an interconnect metallization 10 in a dielectric material layer 11 may be provided.

[0079] A dielectric layer 101 may be formed on the dielectric material layer 11 of the FEOL device circuitry 12. Dielectric layer 101 may be formed, for example, by depositing a layer of dielectric material (e.g., SiO2) on dielectric material layer 11. The dielectric material may be deposited by chemical vapor deposition (CVD), PVD, or other suitable deposition methods. In at least one embodiment, the layer of dielectric material may include a layer of SiO2 deposited by low-pressure chemical vapor deposition (LPCVD) using tetraethylorthosilicate (TEOS) as a reactive gas. The layer of dielectric material may be deposited to a thickness ranging from 3000 angstroms to 8000 angstroms. The upper surface of dielectric layer 101 may then be planarized by, for example, chemical / mechanical polishing (CMP) using a suitable polishing slurry.

[0080] A semiconductor material layer 102 (e.g., a semiconductor substrate, a silicon wafer, an SOI substrate, a doped semiconductor substrate, etc.) may be formed in a dielectric layer 101. The semiconductor material layer 102 may be formed, for example, by forming a BEOL crystalline seed crystal on the dielectric layer 101 (which may be located on the FEOL device circuitry 12 employing a single-crystalline substrate semiconductor). The BEOL crystalline seed crystal may be epitaxially grown onto the single-crystalline substrate semiconductor or may have a crystallinity independent of that of the single-crystalline substrate semiconductor. The BEOL crystalline seed crystal may comprise a first material having a higher melting temperature than a molten material formed on the BEOL crystalline seed crystal and on the dielectric layer 101. Through rapid melt growth, the molten material may be heated to a temperature sufficient to transform from a deposited state into a crystalline material derived from and thus associated with the BEOL crystalline seed crystal. The semiconductor material layer 102 may be composed of a crystalline material.

[0081] Then, a gate structure 121 and source / drain regions 128 may be formed on the semiconductor material layer 102. First, an insulating layer (e.g., corresponding to the gate insulating layer 122) may be formed on the semiconductor material layer 102. This may be done, for example, by depositing an insulating material (e.g., one or more metal oxides, such as Al2O3, HfO2, MgO x and LaO x ) and / or mixed metal oxides (such as HfAlO x ) or by thermally oxidizing the semiconductor material layer 102 to form the insulating layer. The insulating material can be deposited by CVD, PVD, or other suitable deposition techniques. The insulating layer can be formed to have a thickness ranging from 50 angstroms to 100 angstroms. Other suitable methods for forming the insulating layer are also within the contemplation of the present disclosure.

[0082] A suitably doped polysilicon layer (e.g., corresponding to gate electrode 123) may then be deposited on the insulating layer. The polysilicon layer may be deposited by CVD, PVD, or other suitable deposition methods. In at least one embodiment, the polysilicon layer may be deposited by LPCVD to a thickness in the range of 500 angstroms to 2000 angstroms. The polysilicon layer may then be suitably doped by an ion implantation process. In at least one embodiment, where transistor 120 comprises an N-channel FET, arsenic or phosphorus may be implanted.

[0083] A silicide layer (e.g., corresponding to silicide layer 125) may then be formed on the doped polysilicon layer. In at least one embodiment, the silicide layer may include tungsten silicide (WSi2). The silicide layer may be formed, for example, by reacting the surface of the polysilicon layer with tungsten hexafluoride (WF6) (e.g., deposited by chemical vapor deposition (CVD)) in the presence of silane (SiH4). The silicide layer may be formed to have a thickness ranging from 500 angstroms to 2000 angstroms.

[0084] Then, a photolithography process may be performed to pattern the insulating layer, the polysilicon layer, and the silicide layer. The photolithography process may include forming a patterned photoresist mask (not shown) on the silicide layer, and etching the silicide layer, the polysilicon layer, and the insulating layer through openings in the photoresist mask (e.g., wet etching, dry etching, etc.) to form the silicide layer 125, the gate electrode 123, and the gate insulating layer 122, respectively. The photoresist mask may then be removed by ashing, dissolving, or consuming the photoresist mask during the etching process.

[0085] Source / drain regions 128 may be formed in the semiconductor material layer 102 adjacent to the gate insulating layer 122. The source / drain regions 128 may be formed by performing another ion implantation process. The ion implantation process may include implanting dopant ions such as arsenic or phosphorus into the semiconductor material layer 102.

[0086] Then, sidewall spacers 126 may be formed on the sidewalls of the gate insulating layer 122, the sidewalls of the gate electrode 123, and the sidewalls of the silicide layer 125. The sidewall spacers 126 may be formed, for example, by depositing one or more layers of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), and / or oxynitride (e.g., silicon oxynitride) on the semiconductor material layer 102. The multilayer oxide, nitride, and / or oxynitride may be deposited by CVD, PVD, or other suitable deposition methods. In at least one embodiment, the multilayer oxide, nitride, and / or oxynitride may be deposited by LPCVD. The multilayer oxide, nitride, and / or oxynitride may then be anisotropically etched in a reactive ion etcher (RIE) to complete the formation of the gate structure 121.

[0087] Figure 2B The first dielectric layer 131 is an intermediate structure after forming the first source / drain contact 132, the second source / drain contact 134, and the gate electrode contact 136 according to one or more embodiments. A first dielectric layer 131 may be formed on the semiconductor material layer 102 and the gate structure 121. The first dielectric layer 131 may be formed, for example, by depositing a layer of dielectric material (e.g., SiO2) on the dielectric layer 101. The layer of dielectric material may be deposited by CVD, PVD, or other suitable deposition methods. In at least one embodiment, the layer of dielectric material may include the layer of SiO2 deposited by LPCVD using tetraethylorthosilicate (TEOS) as a reactive gas. The layer of dielectric material may be deposited to a thickness ranging from 3000 angstroms to 8000 angstroms. The upper surface of the first dielectric layer 131 may then be planarized by performing, for example, CMP using an appropriate polishing slurry.

[0088] An opening can then be formed in the first dielectric layer 131 to accommodate the contact metallization 130 including the first source / drain contact 132, the second source / drain contact 134, and the gate electrode contact 136. The opening can be formed, for example, by etching the first dielectric layer 131. The etching can be performed to expose the upper surface of the source / drain region 128 and the upper surface of the silicide layer 125. In at least one embodiment, the opening can be etched in the first dielectric layer 131 using a high-density plasma (HDP) etcher and an etchant gas mixture that selectively etches SiO2 of the first dielectric layer 131 to form a self-aligned contact (SAC). This selective etching can be achieved, for example, using a fluorine-based etchant gas mixture.

[0089] A conductive layer may then be formed on the first dielectric layer 131 and in the openings of the first dielectric layer 131. The conductive layer may include, for example, a metal material, polysilicon, or the like, and may fill the openings. In at least one embodiment, the conductive layer may include a metal material (e.g., a metal, a metal alloy, a metal compound, a metal nitride (e.g., TiN, TaN, WN, etc.)) and may be formed by depositing the metal material on the first dielectric layer 131 using CVD, plasma-enhanced CVD (PECVD), LPCVD, PVD, or ALD. The metal material may then be planarized, for example, by CMP, so that the upper surfaces of the contact metallization 130 (e.g., the first source / drain contacts 132, the second source / drain contacts 134, and the gate electrode contact 136) are coplanar with the upper surface of the first dielectric layer 131.

[0090] Figure 2C The second dielectric layer 151 and the trench 152 may be formed in an intermediate structure according to one or more embodiments. The process of forming the second dielectric layer 151 may be substantially similar to the process of forming the first dielectric layer 131.

[0091] A second dielectric layer 151 may be formed on the upper surface of the first dielectric layer 131 and the upper surface of the contact metallization 130. The second dielectric layer 151 may be formed, for example, by depositing a layer of dielectric material (e.g., SiO2) on the first dielectric layer 131. The dielectric material may be deposited by CVD, PVD, or other suitable deposition methods. In at least one embodiment, the layer of dielectric material may include a layer of SiO2 deposited by LPCVD using tetraethylorthosilicate (TEOS) as a reactive gas. The layer of dielectric material may be deposited to a thickness ranging from 50 nanometers to 2500 nanometers. The upper surface of the second dielectric layer 151 may then be planarized by, for example, performing CMP using a suitable polishing slurry.

[0092] Then, trenches 152 can be formed in the second dielectric layer 151 to accommodate the capacitors 160. The trenches 152 can be formed, for example, by etching the second dielectric layer 151. The etching can be performed to expose the upper surface of the first dielectric layer 131 and the upper surface of the contact metallization 130. In at least one embodiment, the second dielectric layer 151 can be etched until the upper surface of the first source / drain contact 132 and the upper surface of the first dielectric layer 131 are exposed. In at least one embodiment, the trenches 152 can be etched in the second dielectric layer 151 using a high-density plasma (HDP) etcher and an etchant gas mixture that selectively etches SiO2 in the second dielectric layer 151.

[0093] The trench 152 may be formed to have a depth and width (e.g., diameter) substantially the same as the length Lc and width Wc, respectively, of the capacitor 160. Specifically, the trench 152 may be formed to have a depth ranging from 50 nanometers to 2500 nanometers and substantially equal to the thickness of the second dielectric layer 151. The trench 152 may be formed to have a width (e.g., diameter) ranging from 20 nanometers to 200 nanometers.

[0094] Figure 2D The bottom capacitor plate 162 is an intermediate structure after forming the bottom capacitor plate 162 according to one or more embodiments. The bottom capacitor plate 162 can be formed by conformally forming (e.g., depositing) a conductive material on the second dielectric layer 151 and in the trench 152. The conductive material can conform to the surface of the trench bottom 152a and the trench sidewalls 152b to have a shape substantially the same as the shape of the trench 152 (e.g., a circular cylinder). The bottom capacitor plate 162 can be formed to form a bottom capacitor plate bottom portion 162a on the trench bottom 152a and a bottom capacitor plate sidewall portion 162b on the trench sidewalls 152b. The bottom capacitor plate 162 can be formed to have a substantially uniform thickness ranging from 2 nanometers to 150 nanometers.

[0095] The bottom capacitor plate 162 can be formed to include a roughened upper surface 162s on both the bottom capacitor plate bottom portion 162a and the bottom capacitor plate sidewall portion 162b. In at least one embodiment, the bottom capacitor plate 162 can be formed such that the roughened upper surface 162s has a root mean square (RMS) surface roughness of at least 1.14 on both the bottom capacitor plate bottom portion 162a and the bottom capacitor plate sidewall portion 162b. In at least one embodiment, the bottom capacitor plate 162 can be formed such that the roughened upper surface 162s has a recessed portion 162s-R on both the bottom capacitor plate bottom portion 162a and the bottom capacitor plate sidewall portion 162b.

[0096] The method of forming the bottom capacitor plate 162 may be selected to provide the bottom capacitor plate 162 having a roughened upper surface 162s with a recessed portion 162s-R and an RMS roughness of at least 1.14. In at least one embodiment, after forming (e.g., depositing) the conductive material, no additional processing may be required to provide the bottom capacitor plate 162 having a roughened upper surface 162s with a recessed portion 162s-R and an RMS roughness of at least 1.14. In at least one embodiment, the method may include CVD, such as PECVD, HDP-CVD, thermal CVD, atmospheric pressure chemical vapor deposition (APCVD), etc. In at least one embodiment, the method may include ALD, such as PEALD, thermal ALD, etc.

[0097] In at least one embodiment, bottom capacitor plate 162 may be formed by PEALD to provide a roughened upper surface 162s having a recessed portion 162s-R and an RMS roughness of at least 1.14. The PEALD method may utilize low processing temperatures (less than 250° C.) to form the TiN layer comprising bottom capacitor plate 162.

[0098] The PEALD method for forming the TiN layer can use argon (99.999%) as a carrier gas and a purge gas. In at least one embodiment, the steps (e.g., all steps) of the PEALD method can be performed in an ALD reaction chamber at 250°C under vacuum. The TiN layer can include one or more thin TiN films grown directly onto the surface of the second dielectric layer 151, the surface of the trench bottom 152a, and the surface of the trench sidewalls 152b.

[0099] The PEALD process can use tetrakis(dimethylamino)titanium(IV) (99%) (TDMAT) as a titanium precursor. TDMAT can be heated to 65°C to increase its vapor pressure. TDMAT can be exposed to the chamber for at least 1000 milliseconds, followed by a purge of at least 10 seconds under an argon-rich environment (e.g., at least 110 standard milliliters per minute (sccm) of argon). The ALD chamber can then be exposed to an NH3:Ar plasma for at least 20 seconds, followed by a purge of at least 10 seconds under at least 110 standard milliliters per minute (sccm) of argon. The NH3:Ar can include, for example, a 300-watt NH3:Ar plasma (10 sccm:100 sccm, respectively). This completes one cycle. The cycle can be repeated until the desired thickness (e.g., in the range of from 2 nm to 150 nm) is achieved.

[0100] The PEALD-deposited TiN layer can be conditioned using an optional conditioning step. The optional conditioning step can include post-deposition hydrogen plasma treatment of the TiN layer. In this optional conditioning step, after the TiN layer is deposited, the intermediate structure can be maintained inside an ALD chamber at 250° C. and repeatedly exposed to a hydrogen plasma (e.g., a 300-watt hydrogen plasma) equilibrated in argon for 5-second intervals. This can be repeated at least 600 times, exposing the TiN layer to the hydrogen plasma for a total of 50 minutes.

[0101] The conditioning step further modifies the properties of the TiN while maintaining a low thermal budget of 250°C. The conditioning step reduces surface oxygen and carbon contamination in the TiN layer. The conditioning step also significantly improves the metallic quality of the TiN layer. Specifically, the conditioning step reduces the resistivity of the TiN layer.

[0102] After depositing the TiN layer, a photolithography process can be used to remove the TiN layer from the upper surface of the second dielectric layer 151. The photolithography process can include forming a patterned photoresist mask (not shown) on the second dielectric layer 151 and etching the conductive material (e.g., TiN) through the openings in the photoresist mask (e.g., wet etching, dry etching, etc.). The photoresist mask can then be removed by ashing, dissolving, or consuming the photoresist mask during the etching process. Alternatively or additionally, a CMP step can be used to remove the conductive material and planarize the upper surface of the second dielectric layer 151 and the end of the bottom capacitor portion plate sidewall portion 162b.

[0103] Figure 2E The capacitor dielectric layer 164 is an intermediate structure after forming the capacitor dielectric layer 164 and the upper capacitor plate 166 according to one or more embodiments. The capacitor dielectric layer 164 can be formed by depositing a layer of dielectric material (e.g., hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide, etc.) on the upper surface of the second dielectric layer 151 and on the roughened upper surface 162s of the bottom capacitor plate 162 in the trench 152. The layer of dielectric material can be conformally formed on the roughened upper surface 162s of the bottom capacitor plate 162. In at least one embodiment, the layer of dielectric material can be formed such that a protrusion 164s-P of the surface 164s of the capacitor dielectric layer 164 is formed in a recess 162s-R of the roughened upper surface 162s of the bottom capacitor plate 162 (e.g., see FIG. 1 ). Figure 1B ).

[0104] The layer of dielectric material for the capacitor dielectric layer 164 can be formed, for example, by depositing the layer on the second dielectric layer 151 and in the trench 152. The layer of dielectric material can be deposited by CVD, PVD, or other suitable deposition methods. The layer of dielectric material can be deposited to have a substantially uniform thickness in the range of from 2 nm to 20 nm.

[0105] The upper capacitor plate 166 may be formed by depositing a layer of conductive material, such as TiN, a metal such as Al, Ta, Ag, Cu, W, Co, Pd, Pt, Ni, Nb, other low-resistivity metal compositions, alloys thereof, or combinations thereof, on the layer of dielectric material for the capacitor dielectric layer 164. The layer of conductive material may be deposited on the layer of dielectric material located in the trenches 152 and on the upper surface of the second dielectric layer 151. The layer of conductive material for the upper capacitor plate 166 may be conformally formed on the capacitor dielectric layer 164.

[0106] The layer of conductive material for upper capacitor plate 166 may be deposited by CVD, PVD, or other suitable deposition methods. The layer of conductive material may be deposited to have a substantially uniform thickness ranging from 2 nanometers to 150 nanometers.

[0107] A photolithography process can then be used to form the capacitor dielectric layer upper portion 164c and the upper capacitor plate upper portion 166c. The photolithography process can include forming a patterned photoresist mask (not shown) on the second dielectric layer 151. The layer of dielectric material for the capacitor dielectric layer 164 and the conductive layer for the upper capacitor plate 166 can then be etched (e.g., by wet etching, dry etching, etc.) through the openings in the photoresist mask. The photoresist mask can then be removed by ashing, dissolving, or by consuming the photoresist mask during the etching process. Alternatively or additionally, a CMP step can be used to remove the dielectric material and the conductive material.

[0108] Figure 2F is an intermediate structure after forming the third dielectric layer 171 according to one or more embodiments. The process of forming the third dielectric layer 171 may be substantially similar to the process of forming the second dielectric layer 151.

[0109] A third dielectric layer 171 may be formed on the upper surface of the second dielectric layer 151 and in the trench 152 on the upper capacitor plate 166. The third dielectric layer 171 may be formed, for example, by depositing a layer of dielectric material (e.g., SiO2) on the second dielectric layer 151. The layer of dielectric material may be deposited to form a third dielectric layer protrusion 171p on the upper capacitor plate 166. In at least one embodiment, the layer of dielectric material may fill the remaining space in the trench 152 above the upper capacitor plate 166.

[0110] The layer of dielectric material can be deposited by CVD, PVD, or other suitable deposition methods. In at least one embodiment, the layer of dielectric material can include a layer of SiO2 deposited by LPCVD using tetraethylorthosilicate (TEOS) as a reactive gas. The layer of dielectric material can be deposited to a thickness ranging from 50 nm to 2500 nm. The upper surface of the third dielectric layer 171 can then be planarized by performing, for example, CMP using an appropriate polishing slurry.

[0111] Figure 3 A method for manufacturing a semiconductor device (e.g., semiconductor device 100) according to one or more embodiments is shown. The method may include: step 310, forming a transistor on a substrate; step 320, forming a dielectric layer on the transistor; step 330, forming a trench in the dielectric layer; and step 340, forming a bottom capacitor plate of a capacitor in the trench by plasma enhanced atomic layer deposition (PEALD), such that the bottom capacitor plate has a rough upper surface and is connected to a source region of the transistor.

[0112] Figure 4 is a detailed cross-sectional view of a portion of a capacitor 160 having an alternative design according to one or more embodiments. Note that for ease of illustration, the recessed portion 162s-R is Figure 4 The recessed portion 162s-R may instead have a regular configuration. Figure 1B That is, the grooves in the recessed portion 162s-R may have different depths and widths. The spacing between the grooves may also vary.

[0113] exist Figure 4 In an alternative design, the width Wr of the groove 162s-R can be greater than the depth Dr of the groove 162s-R in the roughened upper surface 162s of the bottom capacitor plate 162. The depth Dr of the groove 162s-R can be greater than the thickness TD of the capacitor dielectric layer 164. In this case, at least a portion of the upper capacitor plate 166 can be located in the groove 162s-R on the capacitor dielectric layer 164.

[0114] In at least one embodiment, the depth Dr of the recess 162s-R may be greater than the combined thickness TD of the capacitor dielectric layer 164 and the thickness TU of the upper capacitor plate 166. In this case, at least a portion of the third dielectric layer protrusion 171p may be located in the recess 162s-R.

[0115] The width Wr of the recess 162s-R may also be greater than the thickness TD of the capacitor dielectric layer 164. In at least one embodiment, the width Wr of the recess 162s-R may be greater than twice the combined thickness TD of the capacitor dielectric layer 164 and the thickness TU of the upper capacitor plate 166.

[0116] Figure 5 FIG is a vertical cross-sectional view of a semiconductor device 100 having a first alternative design according to one or more embodiments. Figure 5 As shown in FIG, a second alternative design of the semiconductor device 100 may be substantially similar to Figure 1A However, in the first alternative design, with Figure 1A Compared to the configuration in , transistor 120 may have an inverted configuration in dielectric layer 101 .

[0117] In at least one embodiment, the components of transistor 120 in the first alternative design may be substantially the same as Figure 1A However, in a first alternative design, the gate structure 121 may be formed on the underside of the semiconductor material layer 102. The first source / drain contact 132 and the second source / drain contact 134 may contact the source / drain region 128 through the semiconductor material layer 102.

[0118] Figure 6 FIG is a vertical cross-sectional view of a semiconductor device 100 having a second alternative design according to one or more embodiments. Figure 6 As shown in FIG, in a second alternative design, semiconductor device 100 may include a memory segment 501 and a logic segment 502. In at least one embodiment, logic segment 502 may be formed adjacent to memory segment 501 in semiconductor device 100. In at least one embodiment, each of memory segment 501 and logic segment 502 may include FEOL device circuitry 12 and BEOL device circuitry 14.

[0119] Logical section 502 may include Figure 6 5. A plurality of logic devices (e.g., N-MOSFET devices, P-MOSFET devices, etc.) not shown in the figure are provided. The logic devices may be located in an active device region of a substrate (not shown) in a logic section 502. The logic section 502 may also include interconnect metallization 10 located in FEOL device circuitry 12 and BEOL device circuitry 14.

[0120] The memory segment 501 may include a plurality of DRAM cells 170 located in the BEOL device circuitry 14. The DRAM cells 170 may include transistors 120 (eg, select transistors) and capacitors 160 for information storage. Figure 6 As shown in FIG, DRAM cells 170 may be formed adjacent to each other in BEOL device circuitry 14.

[0121] In at least one embodiment, the capacitor dielectric layer upper portions 164c of the DRAM cells 170 can be electrically coupled together. In at least one embodiment, the capacitor dielectric layer upper portions 164c of the DRAM cells 170 can be integrally formed together as a single unit. In at least one embodiment, the capacitor dielectric layer upper portions 164c of the DRAM cells 170 can be formed simultaneously in the same processing step.

[0122] In at least one embodiment, the upper capacitor plate upper portions 166c of the DRAM cell 170 can be electrically coupled together. In at least one embodiment, the upper capacitor plate upper portions 166c of the DRAM cell 170 can be integrally formed together as a single unit. In at least one embodiment, the upper capacitor plate upper portions 166c of the DRAM cell 170 can be formed simultaneously in the same processing step.

[0123] Figure 7 FIG. 1 is a schematic diagram of a semiconductor device 100 having a third alternative design according to one or more embodiments. Figure 7 As shown in FIG, the semiconductor device 100 may include a system on chip (SOC) device including a memory segment 501 and a logic segment 502. In at least one embodiment, the semiconductor device 100 may include a logic chip combined with a DRAM.

[0124] In a third alternative design of semiconductor device 100, logic segment 502 may be located adjacent to memory segment 501. Logic segment 502 may be capable of performing processing operations (e.g., graphics processing operations) at high speed. Logic segment 502 may utilize the memory segment to store information (e.g., information used in the processing operations, information generated by the processing operations, etc.).

[0125] The DRAM portion 501 may include a memory array 602 including the plurality of DRAM cells 170. The DRAM cells 170 may include, for example, Figure 61 and 160. DRAM segment 501 may also include adjacent circuitry 610, including, for example, an X decoder 612, a Y decoder 614, and a sense amplifier 616. Semiconductor device 100 may also include an input / output (I / O) segment 630 adjacent to memory segment 501 and logic segment 502. I / O segment 630 may, for example, connect memory segment 501 and logic segment 502 to external circuitry (not shown).

[0126] Figure 8 FIG. 1 is a schematic diagram of a semiconductor device 100 having a fourth alternative design according to one or more embodiments. Figure 8 As shown in FIG, in a fourth alternative design, the bottom capacitor plate 162, the capacitor dielectric layer 164, and the upper capacitor plate 166 may substantially fill the trench 152. In this case, the third dielectric layer 171 may not be as thick as in FIG. Figure 1A In the fourth alternative design, the capacitor 160 may have a width Wc of less than about 50 nanometers (e.g., about 20 nanometers). In at least one embodiment, the bottom capacitor plate 162 may have a thickness of about 2 to 4 nanometers, the capacitor dielectric layer 164 may have a thickness of about 2 to 4 nanometers, and the upper capacitor plate 166 may have a thickness of about 2 to 4 nanometers. In this case, in the case where the capacitor 160 has a relatively small width (e.g., Wc=20), the trench 152 may be substantially filled with the bottom capacitor plate 162, the capacitor dielectric layer 164, and the upper capacitor plate 166.

[0127] Reference Figures 1A to 8 Capacitor 160 may include: a bottom capacitor plate 162 including a roughened upper surface 162s having a root mean square (RMS) surface roughness of at least 1.14; a capacitor dielectric layer 164 located on and contacting the roughened upper surface 162s of bottom capacitor plate 162; and an upper capacitor plate 166 located on capacitor dielectric layer 164. Bottom capacitor plate 162 may include a TiN layer, and the roughened upper surface 162s of bottom capacitor plate 162 may include an upper surface of the TiN layer. Capacitor 160 may have a capacitance of 10.52 femtofarads or greater. The roughened upper surface 162s of bottom capacitor plate 162 may include a recessed portion 162s-R, and capacitor dielectric layer 164 may be located within recessed portion 162s-R. The depth Dr of recessed portion 162s-R may be greater than the combined thickness of capacitor dielectric layer 164 and upper capacitor plate 166. The width Wr of the recessed portion 162 s -R may be greater than twice the combined thickness of the capacitor dielectric layer 164 and the upper capacitor plate 166 .

[0128] Refer again Figures 1A to 8 Semiconductor device 100 may include a transistor 120 located on a substrate; dielectric layers 131 and 151 located on transistor 120; and a capacitor 160 located in dielectric layers 131 and 151 and including a bottom capacitor plate 162 connected to source region 128 of transistor 120 and having a roughened upper surface 162s having a root mean square (RMS) surface roughness of at least 1.14. Capacitor 160 may further include a capacitor dielectric layer 164 located on bottom capacitor plate 162, wherein roughened upper surface 162s may include a recessed portion 162s-R, and capacitor dielectric layer 164 may be located within recessed portion 162s-R. Capacitor 160 may further include an upper capacitor plate 166 located on capacitor dielectric layer 164 and within recessed portion 162s-R. Dielectric layers 131 and 151 may include trenches 152 having a substantially cylindrical shape, and capacitor 160 may include trench capacitors having a substantially cylindrical shape in trenches 152 of dielectric layers 131 and 151. Trench 152 may include a trench bottom 152a and trench sidewalls 152b extending upward from trench bottom 152a, and bottom capacitor plate 162 may include a substantially cylindrical shape and may include a bottom capacitor plate bottom portion 162a in contact with trench bottom 152a and a bottom capacitor plate sidewall portion 162b in contact with trench sidewall 152b. Capacitor dielectric layer 164 may include a substantially cylindrical shape and may include a capacitor dielectric layer bottom portion 164a in contact with bottom capacitor plate bottom portion 162a and a capacitor dielectric layer sidewall portion 164b in contact with bottom capacitor plate sidewall portion 162b. The roughened upper surface 162s of the bottom capacitor plate 162 may contact the capacitor dielectric layer bottom portion 164a and the capacitor dielectric layer sidewall portion 164b. The upper capacitor plate 166 may include a substantially cylindrical shape and may include an upper capacitor plate bottom portion 166a in contact with the capacitor dielectric layer bottom portion 164a and an upper capacitor plate sidewall portion 166b in contact with the capacitor dielectric layer sidewall portion 164b. The semiconductor device 100 may also include a first contact 132 disposed in the dielectric layers 131 and 151 and connecting the source region 128 of the transistor 120 to the bottom capacitor plate bottom portion 162a.

[0129] Refer again Figures 1A to 8A method of manufacturing a semiconductor device 100 may include forming a transistor 120 on a substrate 102, forming dielectric layers 131 and 151 on the transistor 120, forming a trench 152 in the dielectric layers 131 and 151, and forming a bottom capacitor plate 162 of a capacitor 160 in the trench 152 by plasma-enhanced atomic layer deposition (PEALD), such that the bottom capacitor plate 162 has a roughened upper surface 162s and is connected to the source region 128 of the transistor. Forming the bottom capacitor plate 162 may include depositing a TiN layer in the trench, the roughened upper surface 162s of the bottom capacitor plate 162 may include the upper surface of the TiN layer, and the roughened upper surface 162s may have a root mean square (RMS) surface roughness of at least 1.14. The method may also include forming a capacitor dielectric layer 164 on the roughened upper surface 162s of the bottom capacitor plate 162. Forming the bottom capacitor plate 162 may include forming the roughened upper surface 162s to have a recessed portion 162s-R, and forming the capacitor dielectric layer 164 may include forming the capacitor dielectric layer 164 in the recessed portion 162s-R of the roughened upper surface 162s. The method may also include forming an upper capacitor plate 166 on the capacitor dielectric layer 164 and in the recessed portion 162s-R of the roughened upper surface 162s.

[0130] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A capacitor, characterized in that: include: a bottom capacitor plate comprising a roughened upper surface having a root mean square surface roughness of at least 1.14; a capacitor dielectric layer on the bottom capacitor plate and contacting the roughened upper surface of the bottom capacitor plate; as well as An upper capacitor plate is located on the capacitor dielectric layer.

2. The capacitor according to claim 1, wherein The bottom capacitor plate includes a TiN layer and the roughened upper surface of the bottom capacitor plate includes an upper surface of the TiN layer.

3. The capacitor according to claim 2, wherein: The capacitor has a capacitance of 10.52 femtofarads or greater.

4. The capacitor according to claim 1, wherein The roughened upper surface of the bottom capacitor plate includes a recessed portion and the capacitor dielectric layer is located within the recessed portion.

5. The capacitor according to claim 4, wherein The depth of the recessed portion is greater than the combined thickness of the capacitor dielectric layer and the upper capacitor plate.

6. The capacitor according to claim 5, characterized in that The width of the recessed portion is greater than twice the combined thickness of the capacitor dielectric layer and the upper capacitor plate.

7. A semiconductor device, characterized in that: include: transistors, located on the substrate; a dielectric layer located on the transistor; as well as A capacitor is located in the dielectric layer and includes a bottom capacitor plate connected to the source region of the transistor and having a rough upper surface having a root mean square surface roughness of at least 1.

14.

8. The semiconductor device according to claim 7, wherein The capacitor also includes a capacitor dielectric layer located on the bottom capacitor plate, the rough upper surface includes a recessed portion and the capacitor dielectric layer is located in the recessed portion, and the capacitor also includes an upper capacitor plate located on the capacitor dielectric layer and in the recessed portion.

9. The semiconductor device according to claim 7, wherein: The dielectric layer includes a trench having a substantially cylindrical shape and the capacitor includes a trench capacitor having a substantially cylindrical shape in the trench of the dielectric layer.

10. The semiconductor device according to claim 9, wherein The trench includes a trench bottom and trench sidewalls extending upward from the trench bottom, and the bottom capacitor plate includes a substantially cylindrical shape including a bottom capacitor plate bottom portion contacting the trench bottom and a bottom capacitor plate sidewall portion contacting the trench sidewall.

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