Layout of field sequence pixel circuit and display panel

Abstract

The utility model discloses a field sequence pixel circuit layout and a display panel, the layout comprises a first metal layer, a semiconductor layer, a first gate layer, a second metal layer, a middle metal layer and a third metal layer, and the first metal layer, the semiconductor layer, the first gate layer, the second metal layer, the middle metal layer and the third metal layer are sequentially arranged from bottom to top; the first metal layer is used for shading and forming a reset signal line; and the first metal layer, the semiconductor layer and the first gate layer are used for sharing top gates and bottom gates of the first transistor, the second transistor and the third transistor on the semiconductor layer. The field sequential display pixel driving circuit has the advantages that the problem that row pixel signals are difficult to detect in the field sequential display pixel driving circuit is solved, and whether all units in the pixel driving circuit work normally or not can be checked according to the pixel signals.

Description

Technical Field

[0001] The utility model relates to the technical field of pixel display, in particular to a layout of a field sequential pixel circuit and a display panel. Background Art

[0002] In field-sequential or color-sequential display driver technologies, the pixel circuit design uses a 3T2C structure. The layout shows that capacitors and MOSFETs occupy a large area, and the wiring is complex. A single pixel has as many as six signal lines, resulting in an aperture ratio that is over 30% lower than that of conventional display pixels. The increased number of pixel wiring in field-sequential displays further reduces the aperture ratio by over 10% in the layout design. This low aperture ratio results in low product brightness, low competitiveness, and poor market satisfaction, making it unable to meet the needs of high-end displays. Therefore, improving the pixel aperture ratio has become a focus of the industry.

[0003] Therefore, the present invention proposes a layout structure of a field sequential pixel circuit to solve the problem of reduced aperture ratio caused by complex wiring. Utility Model Content

[0004] The purpose of the utility model is to provide a layout of a field sequential pixel circuit and a display panel, which solves the problem of low aperture ratio caused by many vias and complex signal routing in the panel.

[0005] The purpose of the utility model is to realize a layout of a field sequential pixel circuit through the following technical solution, including: sequentially arranging a first metal layer, a semiconductor layer, a first gate layer, a second metal layer, an intermediate metal layer and a third metal layer;

[0006] A first metal layer is provided on the glass substrate, wherein the first metal layer includes a light shielding pattern and a reset signal line;

[0007] A semiconductor layer and a first gate layer are sequentially provided on the first metal layer, the first gate layer forms a gate metal pattern and corresponding signal lines, the first gate layer includes a top gate of the first transistor and a top gate of the second transistor, and the corresponding signal lines include a row gate signal line and a transfer signal line;

[0008] a second metal layer disposed on the first gate layer, and constituting the channel region, the first terminal, and the second terminal of the first transistor together with the semiconductor layer, and constituting the channel region, the first terminal, and the second terminal of the second transistor together with the semiconductor layer, and constituting the channel region, the first terminal, and the second terminal of the third transistor together with the semiconductor layer; the second metal layer further comprising a reference signal line;

[0009] The intermediate metal layer is provided on the second metal layer and forms a pre-storage capacitor with the second metal layer; the intermediate metal layer also includes a common signal line;

[0010] The third metal layer is arranged above the middle metal layer; the third metal layer includes a data signal line, and the data signal line is coupled to the first end of the first transistor and the second end of the second transistor respectively through a transfer hole and a jumper.

[0011] Furthermore, the layout of the field sequential pixel circuit further includes a transparent conductive layer disposed above the third metal layer. The transparent conductive layer includes a pixel electrode. One end of the pixel electrode is coupled to the second end of the second transistor.

[0012] Furthermore, the first metal layer and the semiconductor layer constitute a bottom gate of the third transistor.

[0013] Furthermore, a bottom gate of the third transistor is coupled to a reset signal line on the first metal layer.

[0014] Furthermore, the reset signal line and the reference signal line overlap in a vertical direction.

[0015] Furthermore, the size of the pre-storage capacitor is positively correlated with the area of the overlapping region between the middle metal layer and the second metal layer.

[0016] Furthermore, the corresponding signal line includes a row gate signal line and a transfer signal line, the top gate of the first transistor is coupled to the row gate signal line, and the top gate of the second transistor is coupled to the transfer signal line.

[0017] This embodiment further provides a display panel with field sequential pixels, comprising a display panel with a zig-zag arrangement, a source driver and a gate driver or a gate driving circuit connected to the display panel, and a timing controller connected to the gate driver or the gate driving circuit and the source driver;

[0018] The zig-zag display panel includes multiple rows of field sequential pixel circuits; two adjacent rows of field sequential pixel circuits form a group of pixel units, and the signals of the previous row of field sequential pixel circuits in each group of field sequential pixel circuits are input into the next row of field sequential pixel circuits.

[0019] Furthermore, the zig-zag arranged display panel comprises a plurality of data signal lines in a Z shape, a plurality of row gate signal lines, a plurality of rows of field sequential pixel circuits defined by the intersection of the plurality of data signal lines and the plurality of row gate signal lines, and a first transistor located at the intersection of the data signal line and the row gate signal line in each field sequential pixel circuit, wherein the first transistor of the odd column is coupled to the data signal line adjacent to its left side, and the first transistor of the even column is coupled to the data signal line adjacent to its right side.

[0020] The utility model has the following advantages:

[0021] (1) The present invention uses the first metal layer as a light-shielding pattern and also performs reset signal routing. In this case, the first metal layer not only performs light-shielding but also performs signal routing, thus overcoming the single function problem of the light-shielding metal layer. Routing the reset signal in the first metal layer allows the reset signal line and the reference signal line to overlap in the vertical direction, thus realizing signal line stacking. By stacking the signal lines below the display area, it is avoided to set up a separate frame space for the signal lines, thus saving the frame space occupied by the signal lines.

[0022] Secondly, the routing of the first metal layer is designed to stack the reset signal line below the reference signal line on the periphery of the semiconductor layer, reducing vias and jumpers, saving space, and greatly improving the aperture ratio.

[0023] (2) The utility model arranges multiple field sequential pixel circuits by adopting a Zig-zag routing method;

[0024] On the one hand, in the existing technology, column inversion is often used to connect multiple field-sequential pixel circuits. This can effectively suppress the problem of display flicker. However, there is no phase difference between the flicker waveforms of all sub-field-sequential pixel circuits on each column, which can easily cause vertical line flicker. The dot inversion method has obvious advantages in improving panel uniformity and avoiding screen crosstalk. However, the dot inversion driving mode consumes more power than other driving modes.

[0025] Therefore, the present invention adopts a Zig-zag wiring arrangement so that the column reversal can achieve the point reversal effect without the consumption of point reversal.

[0026] On the other hand, the present invention adopts the proposed layout structure and Zig-zag routing. Since the reset signal line is stacked below the reference signal line, the need for a large through-hole between the field sequential pixel circuits can be avoided, effectively reducing the aperture ratio reduction problem caused by the via problem generated in the arrangement of multiple field sequential pixel circuits, thereby greatly improving the aperture ratio and improving the panel picture quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a structural diagram of the field sequential pixel circuit of the utility model;

[0028] Figure 2 This is a layout diagram of the utility model; (Example 1)

[0029] Figure 3 This is a panel structure diagram of the prior art;

[0030] Figure 4 This is a schematic diagram of the Zig-zag routing method;

[0031] Figure 5This is a panel structure diagram of the present utility model; (Example 2). DETAILED DESCRIPTION

[0032] The present invention will be further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0033] It should be noted that the directions or positional relationships indicated by "left" and "right" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the utility model product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the utility model.

[0034] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions therein can be combined with each other. Example

[0035] See Figure 1~Figure 2 , a layout of a field sequential pixel circuit according to a specific embodiment of the present invention includes a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a pixel capacitor Clc, a third transistor T3, a row gate signal line Scan, a data signal line Data, a reset signal line Reset, a reference signal line Vref, a transfer signal line Tran, and a common signal line Com;

[0036] Among them, the row gate signal line Scan and the transfer signal line Tran are distributed in the horizontal direction in the layout of the field sequential pixel circuit, the data signal line Data and the reference signal line Vref are distributed in the vertical direction, and the reset signal line Reset is stacked and set directly below the reference signal line Vref, that is, the reset signal line Reset and the reference signal line Vref overlap in the vertical direction, which can save space; the vertical direction is the light output direction of the liquid crystal.

[0037] In this embodiment, the first source and drain of the first transistor T1 are coupled to the data signal line Data, and the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1; the first gate of the first transistor T1 is coupled to the row gate signal line Scan; and the other end of the pre-storage capacitor Cs1 is coupled to the common signal line Com.

[0038] Furthermore, the first source and drain of the second transistor T2 are coupled to the second source and drain of the first transistor T1, the gate of the second transistor T2 is coupled to the transfer signal line Tran, and the second source and drain of the second transistor T2 are coupled to one end of the pixel capacitor Clc; the other end of the pixel capacitor Clc is coupled to the common signal line Com; one end of the holding capacitor Cs2 is coupled to the second source and drain of the second transistor T2, and the other end is coupled to the common signal line Com.

[0039] Furthermore, the first source and drain of the third transistor T3 are coupled to the second source and drain of the second transistor T2 , the second source and drain of the third transistor T3 are coupled to the reference signal line Vref, and the gate of the third transistor T3 is coupled to the reset signal line Reset.

[0040] In order to make it easier to understand the technical solution of the pixel circuit layout of the present invention, a pixel circuit layout and a specific manufacturing process thereof are provided in the following embodiment, and the steps are as follows:

[0041] Step 1: forming a first metal layer 1 on a glass substrate, forming a light-shielding pattern on the first metal layer 1, and preparing a bottom gate of a third transistor T3 and a reset signal line Reset; the bottom gate of the third transistor T3 is coupled to the reset signal line Reset;

[0042] Step 2: an active layer pattern is formed on the semiconductor layer 2 above the first metal layer, and a channel region of the transistor is obtained by a heavy doping process using a flooding plate;

[0043] Step 3: forming a first gate layer 3 on the front surface of the semiconductor layer 2 and etching the same time to form a gate metal pattern Gate and corresponding signal lines, constituting the gate of the first transistor T1 and the gate of the second transistor T2. The corresponding signal lines include a row gate signal line Scan and a transfer signal line Tran.

[0044] Step 4: forming a first interlayer insulating layer on the entire surface of the gate metal pattern;

[0045] Step 5: A second metal layer 4 is provided on the first interlayer insulating layer. The second metal layer 4 and the semiconductor layer 2 constitute the channel region, the first terminal, and the second terminal of the first transistor T1. At the same time, the second metal layer 4 and the semiconductor layer 2 also constitute the channel region, the first terminal, and the second terminal of the second transistor T2, and the first terminal and the second terminal of the third transistor T3.

[0046] Step 6: Disposing a second interlayer insulating layer on the second metal layer 4;

[0047] Step 7: an intermediate metal layer 5 is provided on the second interlayer insulating layer, and the intermediate metal layer 5 is connected to the common electrode; the intermediate metal layer 5 and the second metal layer 4 together constitute a pre-storage capacitor Cs1;

[0048] Step 8: forming a third interlayer insulating layer on the entire surface of the intermediate metal layer 5;

[0049] Step 9: forming a third metal layer 6 and a data signal line (Data) in a vertical direction on the third interlayer insulating layer, and coupling them to the first end of the first transistor T1 and the second end of the second transistor T2 through a via process;

[0050] Step 10: forming a transparent conductive layer 7 on the entire surface of the third metal layer 6; forming a pixel electrode Clc on the transparent conductive layer 7, and coupling the pixel capacitor to the second end of the second transistor T2 through a transfer hole process.

[0051] This embodiment uses the first metal layer 1 as a light-shielding pattern and also provides routing for the reset signal Reset. In this case, the first metal layer 1 not only provides light-shielding but also provides signal routing, overcoming the single-function issue of the light-shielding metal layer. Routing the reset signal Reset on the first metal layer 1 allows the reset signal line Reset to overlap with the reference signal line Vref in the vertical direction, achieving signal line stacking. By stacking the signal lines below the display area, this avoids the need for separate frame space for the signal lines, saving frame space occupied by the signal lines.

[0052] Secondly, the routing of the first metal layer 1 is designed to stack the reset signal line Reset below the reference signal line Vref on the periphery of the semiconductor layer 2, reducing vias and jumpers, saving space, and greatly improving the aperture ratio. Example

[0053] See Figure 5 This embodiment also provides a display panel with field sequential pixels, including a display panel with a zig-zag arrangement, a source driver and a gate driver or a gate driving circuit connected to the display panel, and a timing controller connected to the gate driver or the gate driving circuit and the source driver.

[0054] The zig-zag display panel includes multiple rows of field sequential pixel circuits; two adjacent rows of field sequential pixel circuits form a group of pixel units, and the signals of the previous row of field sequential pixel circuits in each group of field sequential pixel circuits are input into the next row of field sequential pixel circuits.

[0055] In the prior art, column inversion is often used to connect multiple field-sequential pixel circuits. This can effectively suppress the problem of display flicker. However, there is no phase difference between the flicker waveforms of all sub-field-sequential pixel circuits on each column, which can easily cause vertical line flicker. The dot inversion method has obvious advantages in improving panel uniformity and avoiding screen crosstalk. However, the dot inversion driving mode consumes more power than other driving modes. Therefore, refer to Figure 4 As shown, the present invention adopts a Zig-zag wiring arrangement, so that the column reversal achieves the point reversal effect without the consumption of point reversal;

[0056] Furthermore, a zig-zag display panel includes a plurality of data signal lines Data in a Z shape, a plurality of row gate signal lines Scan, and a plurality of rows of field-sequential pixel circuits defined by the intersection of the plurality of data signal lines Data and the plurality of row gate signal lines Scan; and a first transistor T1 located at the intersection of the data signal line Data and the row gate signal line Scan in each field-sequential pixel circuit, wherein the first transistor T1 in odd-numbered columns is coupled to the data signal line Data adjacent to its left, and the first transistor T1 in even-numbered columns is coupled to the data signal line Data adjacent to its right;

[0057] See Figure 3 In the prior art, multiple pixel circuits need to be connected through multiple through-holes. However, the present invention adopts the proposed layout structure and Zig-zag routing. Since the reset signal line is stacked below the reference signal line, the need for a large through-hole between the field-sequential pixel circuits can be avoided. This effectively reduces the aperture ratio problem caused by the via holes generated in the arrangement of multiple field-sequential pixel circuits, thereby greatly improving the aperture ratio and improving the panel image quality.

[0058] The above embodiments merely represent preferred implementations, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art may make various modifications and improvements without departing from the present invention, and these modifications and improvements are all within the scope of protection of the present invention.

Claims

1. A layout of a field sequential pixel circuit, characterized in that: include: A first metal layer (1), a semiconductor layer (2), a first gate layer (3), a second metal layer (4), an intermediate metal layer (5) and a third metal layer (6) are sequentially provided; The first metal layer (1) is arranged on a glass substrate, and the first metal layer (1) includes a light shielding pattern and a reset signal line (Reset); A semiconductor layer (2) and a first gate layer (3) are sequentially arranged on the first metal layer (1); the first gate layer (3) forms a gate metal pattern and a corresponding signal line; the first gate layer (3) includes a top gate of a first transistor (T1) and a top gate of a second transistor (T2); The second metal layer (4) is arranged on the first gate layer (3), and together with the semiconductor layer (2) constitutes the channel region, the first end and the second end of the first transistor (T1), and together with the semiconductor layer (2) constitutes the channel region, the first end and the second end of the second transistor (T2), and together with the semiconductor layer (2) constitutes the channel region, the first end and the second end of the third transistor (T3); the second metal layer (4) also includes a reference signal line (Vref); The intermediate metal layer (5) is arranged on the second metal layer (4) and forms a pre-storage capacitor (Cs1) with the second metal layer (4); the intermediate metal layer (5) also includes a common signal line (Com); The third metal layer (6) is arranged on the middle metal layer (5); the third metal layer (6) includes a data signal line (Data), and the data signal line (Data) is coupled to the first end of the first transistor (T1) and the second end of the second transistor (T2) through a transfer hole and a jumper.

2. The layout of a field sequential pixel circuit according to claim 1, characterized in that: The layout of the field-sequential pixel circuit further includes a transparent conductive layer (7), which is arranged on the third metal layer (6), and the transparent conductive layer (7) includes a pixel electrode (Clc), and one end of the pixel electrode (Clc) is coupled to the second end of the second transistor (T2).

3. The layout of a field sequential pixel circuit according to claim 1, wherein: The first metal layer (1) and the semiconductor layer (2) form the bottom gate of the third transistor (T3).

4. The layout of a field sequential pixel circuit according to claim 3, wherein: The bottom gate of the third transistor (T3) is coupled to a reset signal line (Reset) on the first metal layer (1).

5. The layout of a field sequential pixel circuit according to claim 1, wherein: The reset signal line (Reset) overlaps with the reference signal line (Vref) in a vertical direction.

6. The layout of a field sequential pixel circuit according to claim 1, wherein: The size of the pre-storage capacitor (Cs1) is positively correlated with the area of the overlapping region between the middle metal layer (5) and the second metal layer (4).

7. The layout of a field sequential pixel circuit according to claim 1, wherein: The corresponding signal lines include a row gate signal line (Scan) and a transfer signal line (Tran), the top gate of the first transistor (T1) is coupled to the row gate signal line (Scan), and the top gate of the second transistor (T2) is coupled to the transfer signal line (Tran).

8. A display panel with field sequential pixels, using the layout of the field sequential pixel circuit according to any one of claims 1 to 7, characterized in that: It includes a display panel with a zig-zag arrangement, a source driver and a gate driver or a gate driving circuit connected to the display panel, and a timing controller connected to the gate driver or the gate driving circuit and the source driver; The zig-zag display panel includes multiple rows of field sequential pixel circuits; its characteristic is that two adjacent rows of field sequential pixel circuits form a group of pixel units, and the signal of the field sequential pixel circuit of the previous row in each group of field sequential pixel circuits is input into the field sequential pixel circuit of the next row.

9. The display panel with field sequential pixels according to claim 8, characterized in that: include: The zig-zag arrangement of the display panel comprises a plurality of data signal lines (Data) arranged in a Z shape, a plurality of row gate signal lines (Scan), a plurality of rows of field sequential pixel circuits defined by the intersection of the plurality of data signal lines (Data) and the plurality of row gate signal lines (Scan), and a first transistor (T1) located at the intersection of the data signal line (Data) and the row gate signal line (Scan) in each field sequential pixel circuit, wherein the first transistor (T1) in the odd-numbered columns is coupled to the data signal line (Data) adjacent to the left thereof, and the first transistor (T1) in the even-numbered columns is coupled to the data signal line (Data) adjacent to the right thereof.

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