Double-ROM (Read Only Memory) circuit structure of computer mainboard

Abstract

The utility model relates to a double-ROM (Read Only Memory) circuit structure of a computer mainboard. The double-ROM circuit structure of the computer mainboard comprises a CPU / bridge chip, a four-way SPDT analog switch, a logic device, a first ROM, a second ROM, a working state judgment circuit, a plurality of signal isolation circuits, an SPDT switching circuit and an offline burning interface. The working state judgment circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube, a first resistor and a diode; corresponding to a signal transmission channel between the off-line burner and the first ROM and between the off-line burner and the second ROM during burning, the plurality of signal isolation circuits are electrically connected between the off-line burning interface and corresponding pins of the first ROM and the second ROM so as to transmit corresponding signals in a signal isolation manner; and each signal isolation circuit comprises an NMOS (N-channel metal oxide semiconductor) tube and a second resistor. According to the double-ROM circuit structure of the computer mainboard, on the premise that the double-ROM function and the off-line burning function of the mainboard are guaranteed to be normal, signal stubs, introduced by the double-ROM design, of SPI signals are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic computers, in particular to a dual ROM circuit structure of a computer mainboard. Background Art

[0002] Read-only memory (ROM) operates in a non-destructive manner, allowing only reading but not writing. Once written, information is permanently stored, even if the power is removed. Computers typically contain a basic input / output system (BIOS) embedded in the ROM on the motherboard. Its primary functions include performing a power-on self-test, initializing various system modules, running basic input / output drivers, and booting the operating system.

[0003] SPI (Serial Peripheral Interface) is a serial peripheral interface specification commonly used to connect various peripheral devices, including ROMs. SPI operates in master and slave modes. An SPI communication system requires a master device and one or more slave devices. The master device provides the clock, while the slave device receives the clock. Read and write operations on the SPI interface are initiated by the master device. Multiple slave devices are managed through their respective chip select (CS) signals. The SPI interface generally uses four signal lines for communication: SDI (data input), SDO (data output), SCK (clock), and CS (chip select). The CS signal determines which slave device communicates with the master device.

[0004] With increasing demands for data security, many users require motherboard designs that allow the CPU / GPU / bridge to boot from two ROMs simultaneously, creating a redundant ROM. If one ROM fails, the redundant ROM can be used to boot from it, improving motherboard security and preventing the motherboard from becoming unbootable due to a ROM failure. However, conventional designs typically connect SPI signals, except for the CS signal, to the two ROMs using a "Y-type connection," allowing the CS signal to be used to select the desired ROM. This approach introduces a problem: in actual use, the signals from the two ROMs become stubs on the motherboard, compromising signal integrity and ultimately limiting SPI signal speed. This can lead to issues such as long boot times and failures in high and low temperature tests. Therefore, addressing the signal stub issue in dual ROM designs is crucial. Summary of the Invention

[0005] Therefore, the purpose of this utility model is to provide a dual ROM circuit structure of a computer mainboard to solve the signal stub problem in the dual ROM design.

[0006] To achieve the above object, the utility model provides a dual ROM circuit structure of a computer motherboard, comprising: a CPU / bridge chip, a four-way SPDT analog switch, a logic device, a first ROM, a second ROM, a working state judgment circuit, multiple signal isolation circuits, an SPDT switch circuit, and an offline burning interface;

[0007] The first group of signal channels of the four-way SPDT analog switch is electrically connected to the CPU / bridge chip, the second group of signal channels is electrically connected to the first ROM, and the third group of signal channels is electrically connected to the second ROM; the logic device is electrically connected to the four-way SPDT analog switch to input a selection signal to the four-way SPDT analog switch, and the four-way SPDT analog switch connects the first group of signal channels to one of the second group of signal channels and the third group of signal channels according to the selection signal;

[0008] The working status judgment circuit includes a PMOS transistor, a first resistor, and a diode; the gate of the PMOS transistor inputs a mainboard power-on status signal via the first resistor, the source inputs a power-on status signal from the offline programming interface, and the drain is electrically connected to the isolation control signal; the anode of the diode is electrically connected to the source of the PMOS transistor, and the cathode is electrically connected to the gate of the PMOS transistor;

[0009] Corresponding to the signal transmission channels between the offline programmer and the first and second ROMs during programming, the multiple signal isolation circuits are electrically connected between the offline programming interface and the corresponding pins of the first and second ROMs to transmit corresponding signals through signal isolation. Each of the signal isolation circuits includes an NMOS transistor and a second resistor. The gate of the NMOS transistor inputs the isolation control signal, the source is used to electrically connect to the first and second ROMs, and the drain is used to electrically connect to the offline programming interface. The isolation control signal is electrically connected to the source via the second resistor. For the chip select signal isolation circuit corresponding to the chip select signal transmission channel during programming among the multiple signal isolation circuits, the source of the NMOS transistor in the chip select signal isolation circuit is electrically connected to the input end of the SPDT switch circuit, and the two output ends of the SPDT switch circuit are electrically connected to the first and second ROMs, respectively.

[0010] Wherein, the logic device is EC, CPLD or MCU.

[0011] Wherein, the four-way SPDT analog switch is RS2233YTSS16.

[0012] Among them, the SPDT switch circuit is a jumper structure.

[0013] The model of the PMOS tube is ZM240P03M.

[0014] The resistance of the first resistor is 4.7 kilo-ohms.

[0015] The model of the diode is SM340AF.

[0016] The model of the NMOS tube is LBSS139WT1G.

[0017] The resistance of the second resistor is 2.2 kilo-ohms.

[0018] Wherein, the mainboard power-on status signal is a 1.8V power supply on the mainboard.

[0019] In summary, the dual-ROM circuit structure of the computer motherboard of the present invention reduces the signal stubs of the SPI signal introduced by the dual-ROM design while ensuring the normal dual-ROM function and offline burning function of the motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following detailed description of the specific embodiments of the present invention in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present invention apparent.

[0021] Figure 1 This is a circuit diagram of a preferred embodiment of the dual ROM circuit structure of a computer motherboard of the utility model;

[0022] Figure 2 This is a circuit connection diagram of a four-way SPDT analog switch in a preferred embodiment of the dual ROM circuit structure of a computer motherboard of the utility model;

[0023] Figure 3 This is a working state judgment circuit diagram of a preferred embodiment of the dual ROM circuit structure of a computer motherboard of the utility model;

[0024] Figure 4 This is a schematic diagram of a signal isolation circuit in a preferred embodiment of a dual ROM circuit structure of a computer motherboard of the present invention;

[0025] Figure 5 This is a schematic diagram of a chip select signal isolation circuit and an SPDT switch circuit in a preferred embodiment of a dual ROM circuit structure of a computer motherboard of the present invention;

[0026] Figure 6 This is a circuit connection diagram of an offline burning interface in a preferred embodiment of a dual ROM circuit structure of a computer motherboard of the utility model;

[0027] Figure 7This is a circuit connection diagram of the ROM in a preferred embodiment of the dual ROM circuit structure of the computer motherboard of the utility model. DETAILED DESCRIPTION

[0028] See also Figures 1 to 7 ,in, Figure 1 This is a circuit diagram of a preferred embodiment of the dual ROM circuit structure of a computer motherboard of the utility model. Figure 2 For this purpose, the circuit connection diagram of the four-way SPDT analog switch in the preferred embodiment is as follows: Figure 3 For this reason, the working state judgment circuit diagram in the preferred embodiment is: Figure 4 For this purpose, the signal isolation circuit diagram in the preferred embodiment is as follows: Figure 5 For this purpose, the schematic diagram of the chip select signal isolation circuit and the SPDT switch circuit in the preferred embodiment particularly shows the signal isolation circuit for the chip select signal. Figure 6 For this purpose, the circuit connection diagram of the offline programming interface in the preferred embodiment is as follows: Figure 7 For this purpose, the circuit connection diagram of the ROM in the preferred embodiment is shown.

[0029] like Figure 1 As shown, the dual ROM circuit structure of the computer motherboard of the present invention mainly includes: CPU / bridge chip, four-way SPDT analog switch, logic device, first ROM, second ROM, working status judgment circuit, multiple signal isolation circuits, SPDT switch circuit, and offline burning interface (header).

[0030] The first group of signal channels of the four-way SPDT analog switch is electrically connected to the CPU / bridge chip, the second group of signal channels is electrically connected to ROM1, and the third group of signal channels is electrically connected to ROM2. The logic device is electrically connected to the four-way SPDT analog switch to input a selection signal to the select pin of the four-way SPDT analog switch. The four-way SPDT analog switch connects the first group of signal channels to one of the second and third groups of signal channels based on the selection signal, with only one channel being connected at a time, thereby avoiding signal stubs. The logic device can be an EC, CPLD, or MCU.

[0031] Combine Figure 2 and Figure 7In this preferred embodiment, the four-way SPDT analog switch U45 is model RS2233YTSS16. Its functional principle is shown in Table 1 below. U45's function is to control the SPI signal via the EC_ROM_SELECT selection signal from the logic device on its S pin, transmitting it to ROM1 and ROM2 respectively (U45's S pin is equivalent to the IN pin in the function table). U23 and U25 are two ROMs, respectively. This design avoids the signal stubs that occur when the SPI signal is directly connected to the two ROMs. Instead, only one SPI signal is connected at a time, thus avoiding signal stubs.

[0032] Table 1. RS2233YTSS16 chip function table

[0033]

[0034] Combine Figure 3 In this preferred embodiment, the working status determination circuit includes a PMOS transistor Q1, a first resistor R38, and a diode PD7. The PMOS transistor is ZM240P03M, the first resistor has a resistance of 4.7 kilo-ohms, and the diode is SM340AF. The gate of the PMOS transistor receives the motherboard power-on status signal via the first resistor, the source receives the offline programming interface power-on status signal, and the drain is electrically connected to the isolation control signal VCC_MOS. The anode of the diode is electrically connected to the source of the PMOS transistor, and the cathode is electrically connected to the gate of the PMOS transistor. In this preferred embodiment, the motherboard power-on status signal is the 1.8V power supply on the motherboard (see Figure 7 ).

[0035] PMOS transistor Q1, diode PD7, resistor R38, and resistor R35 (0 ohm) form a working status judgment circuit. This circuit distinguishes between the offline programmer status and the motherboard power-on status. There are three states: 1. When the motherboard is powered on and the offline programmer is not connected, the corresponding offline programming interface is not powered. At this time, the motherboard power-on status signal VCC_SPI, which reflects the motherboard power-on status, is powered, while the offline programming interface power-on status signal VCC_HEADER, which reflects the offline programming interface power-on status, is not powered. Therefore, Q1 is not conducting, and due to the unidirectional conduction principle of the diode, the isolation control signal VCC_MOS is not powered. 2. When the motherboard is not powered and the offline programmer is connected, the motherboard power-on status signal VCC_SPI is not powered, and VCC_HEADER is not powered. The ER offline programming interface power-on status signal has power, and VGS = -1.8V, which meets the Q1 on-voltage requirement. Therefore, Q1 is on, so the isolation control signal VCC_MOS voltage is approximately the VCC_HEADER offline programming interface power-on status signal voltage. 3. The mainboard is powered on and the offline programmer is connected. Both the VCC_SPI mainboard power-on status signal and the VCC_HEADER offline programming interface power-on status signal have power, but Q1's VGS = 0V, which does not meet the on-voltage requirement. Therefore, the isolation control signal VCC_MOS also has power.

[0036] Then, for the signal stubs attached to the offline burning interface, combine Figure 4 and Figure 5 As can be seen, corresponding to the signal transmission channels between the offline programmer and ROM1 and ROM2 during programming, multiple signal isolation circuits are electrically connected between the offline programming interface and the corresponding pins of ROM1 and ROM2 to transmit the corresponding signals through signal isolation. In this preferred embodiment, the four signal isolation circuits correspond to SPI_CLK_MOS, SPI_MOSI_MOS, SPI_MISO_MOS, and the chip select signal SPI_CS#_MOS. Each signal isolation circuit has the same circuit structure but is only designed for different signals.

[0037] Each of the signal isolation circuits includes an NMOS tube and a second resistor; the gate of the NMOS tube inputs the isolation control signal VCC_MOS, the source is used to be electrically connected to ROM1 and ROM2, and the drain is used to be electrically connected to the offline burning interface, and the isolation control signal VCC_MOS is electrically connected to the source via the second resistor; for the chip select signal isolation circuit corresponding to the chip select signal transmission channel during burning among the multiple signal isolation circuits, the source of the NMOS tube in the chip select signal isolation circuit is electrically connected to the input end of the SPDT switch circuit, and the two output ends of the SPDT switch circuit are electrically connected to ROM1 and ROM2 respectively.

[0038] In this preferred embodiment, the SPDT switch circuit is as follows Figure 5 In the jumper structure shown, the model of the NMOS tube is LBSS139WT1G, and the resistance of the second resistor is 2.2 kilo-ohms.

[0039] The isolation control signal VCC_MOS is connected to the following NMOS transistors Q2, Q8, Q10, and Q11, specifically model LBSS139WT1G. Therefore, only when the motherboard is powered off and an offline programmer is plugged in does the VCC_MOS isolation control signal become energized, turning on the NMOS transistors and simultaneously pulling up the SPI signal through the second resistor. Otherwise, the circuitry behind the dual ROM is isolated by the NMOS transistors and becomes inoperative. This method reduces signal stubs from the dual ROM to the offline programming interface, ensuring signal integrity.

[0040] See also Figure 5 , J_BIOSW1 and the jumper structure matched with BIOS_W1 act as a switch. By selecting the offline programming interface J1 ( Figure 6 ) to the chip select (CS) signal on the dual ROM chip select pins CS1 / CS2 ( Figure 1 ) to perform offline programming of ROM1 / ROM2 respectively. For example, when SPI_CS#_ROM1 is connected to SPI_CS#_H, ROM1 will be programmed. This ensures that the offline programming function is normal.

[0041] See also Figure 6 In this preferred embodiment, the circuit connection of the offline programming interface J1 can be configured according to the conventional configuration.

[0042] See also Figure 7 In this preferred embodiment, the circuit connection diagram of the dual ROM U23 and U25 is connected to the rest of the dual ROM circuit structure of the present invention according to the signal relationship, wherein the mainboard power-on status signal VCC_SPI is the 1.8 volt power supply on the mainboard.

[0043] In summary, the dual-ROM circuit structure of the computer motherboard of the present invention reduces the signal stubs introduced by the dual-ROM design of the SPI signal, improves the signal quality, and speeds up the SPI rate by adding circuits and switches while ensuring the normal dual-ROM function and offline burning function of the motherboard.

[0044] As described above, for ordinary technicians in this field, various other corresponding changes and modifications can be made according to the technical solution and technical concept of the utility model, and all these changes and modifications should fall within the scope of protection of the claims attached to the utility model.

Claims

1. A dual ROM circuit structure for a computer motherboard, characterized in that: include: CPU / bridge chip, four-way SPDT analog switch, logic device, first ROM, second ROM, working status judgment circuit, multiple signal isolation circuits, SPDT switch circuit, and offline burning interface; The first group of signal channels of the four-way SPDT analog switch is electrically connected to the CPU / bridge chip, the second group of signal channels is electrically connected to the first ROM, and the third group of signal channels is electrically connected to the second ROM; the logic device is electrically connected to the four-way SPDT analog switch to input a selection signal to the four-way SPDT analog switch, and the four-way SPDT analog switch connects the first group of signal channels to one of the second group of signal channels and the third group of signal channels according to the selection signal; The working status judgment circuit includes a PMOS transistor, a first resistor, and a diode; the gate of the PMOS transistor inputs a mainboard power-on status signal via the first resistor, the source inputs a power-on status signal from the offline programming interface, and the drain is electrically connected to the isolation control signal; the anode of the diode is electrically connected to the source of the PMOS transistor, and the cathode is electrically connected to the gate of the PMOS transistor; Corresponding to the signal transmission channels between the offline programmer and the first and second ROMs during programming, the multiple signal isolation circuits are electrically connected between the offline programming interface and the corresponding pins of the first and second ROMs to transmit corresponding signals through signal isolation. Each of the signal isolation circuits includes an NMOS transistor and a second resistor. The gate of the NMOS transistor inputs the isolation control signal, the source is used to electrically connect to the first and second ROMs, and the drain is used to electrically connect to the offline programming interface. The isolation control signal is electrically connected to the source via the second resistor. For the chip select signal isolation circuit corresponding to the chip select signal transmission channel during programming among the multiple signal isolation circuits, the source of the NMOS transistor in the chip select signal isolation circuit is electrically connected to the input end of the SPDT switch circuit, and the two output ends of the SPDT switch circuit are electrically connected to the first and second ROMs, respectively.

2. The dual ROM circuit structure of a computer motherboard according to claim 1, wherein: The logic device is EC, CPLD or MCU.

3. The dual ROM circuit structure of a computer motherboard according to claim 1, wherein: The four-way SPDT analog switch is RS2233YTSS16.

4. The dual ROM circuit structure of a computer motherboard according to claim 1, wherein: The SPDT switch circuit is a jumper structure.

5. The dual ROM circuit structure of a computer motherboard according to claim 1, wherein: The model of the PMOS tube is ZM240P03M.

6. The dual ROM circuit structure of a computer mainboard according to claim 5, wherein: The resistance of the first resistor is 4.7 kilo-ohms.

7. The dual ROM circuit structure of a computer mainboard according to claim 5, wherein: The model of the diode is SM340AF.

8. The dual ROM circuit structure of a computer mainboard according to claim 1, wherein: The model of the NMOS tube is LBSS139WT1G.

9. The dual ROM circuit structure of a computer mainboard according to claim 8, wherein: The resistance of the second resistor is 2.2 kilo-ohms.

10. The dual ROM circuit structure of a computer mainboard according to claim 1, wherein: The mainboard power-on status signal is a 1.8V power supply on the mainboard.

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