Dual-power control circuit

Abstract

The utility model relates to the technical field of electronics, in particular to a dual-power control circuit. The dual power supply control circuit comprises a triode, a field effect transistor, a first diode, a second diode, a first resistor and a second resistor. The dual power supply comprises a first control power supply and a second control power supply. The first control power supply is connected with the anode of the first diode; the second control power supply is connected with the anode of the second diode; cathodes of the first diode and the second diode are connected with a base of the triode; the collector electrode of the triode is connected with the first end of the first resistor; the second end of the first resistor and the grid electrode of the field effect transistor are connected with the first end of the second resistor; the second end of the second resistor and the source electrode of the field effect transistor are connected with the working power supply; the drain electrode of the field effect transistor serves as the output voltage end of the control circuit. According to the utility model, the on-off of a certain working power supply is controlled by dual power supplies together, and the stability and reliability of the whole controller power supply system are ensured.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, and more particularly to a dual power supply control circuit. Background Art

[0002] As a development trend in modern vehicle architecture, zone control modules (ZCMs) face the complex situation of multiple power supply systems jointly regulating a single voltage. Among them, more and more ZCMs have been integrated with wireless functions, such as Bluetooth technology. The Bluetooth chip is a 3.3V power supply system, and the high level of the control signal it outputs is set to 3.3V. In contrast, the microcontroller (MCU) is based on a 5V power supply system, and the high level of the control signal it outputs is 5V. In some application scenarios, the Bluetooth chip and the MCU need to coordinate to control the switching of a specific power supply, thereby powering other units such as a logic chip.

[0003] In the prior art, the following specific circuit structure is usually adopted to achieve dual power supply control. Figure 1 The schematic diagram of a dual-power supply control circuit from the prior art is disclosed. In this circuit, a first control voltage Vcc10 (i.e., the 3.3V power supply for the Bluetooth chip) and a second control voltage Vcc20 (i.e., the 5V power supply for the MCU) are used via transistor T0 to control the on / off state of the working power supply VQ0. Transistor T0's emitter is directly connected to VQ0, while its collector serves as the output voltage terminal Vs0 of the control circuit, maintaining a constant 5V voltage on VQ0.

[0004] The above circuit needs to meet the following four key requirements:

[0005] Requirement 1: When the first control voltage Vcc10 is at a high level (3.3V), the transistor T0 is expected to be turned off and not conduct, so that the output voltage terminal Vs0 is not energized.

[0006] Requirement 2: When the first control voltage Vcc10 is at a low level (0V), the transistor T0 is expected to be turned on, so that the output voltage terminal Vs0 is energized and outputs 5V to supply power to the logic chip.

[0007] Requirement 3: When the second control voltage Vcc20 is at a high level (5V), the transistor T0 is also expected to be turned off and not conduct, so that the output voltage terminal Vs0 is not energized.

[0008] Requirement 4: If the second control voltage Vcc20 is at a low level (0V), the transistor T0 is expected to be turned on so that the output voltage terminal Vs0 is powered and outputs 5V to supply power to the logic chip.

[0009] After in-depth analysis, it was discovered that the above circuit design has a significant flaw, namely, requirement 1 cannot be met. Specifically, when the first control voltage Vcc10 is at a high level (3.3V), the voltage at the right side of transistor T0, namely test point P1, is 4V. Due to the forward voltage drop of the diode (approximately 0.7V), the base potential of transistor T0 is 4V. At this time, the emitter voltage is 5V, and the emitter voltage is 1V higher than the base voltage, meeting the transistor conduction condition (emitter voltage is at least 0.7V higher than the base voltage). Therefore, regardless of whether Vcc10 is at a high or low level, transistor T0 will be turned on, resulting in the output voltage terminal Vs0 always being energized. Consequently, effective control of transistor T0 and output voltage terminal Vs0 by the first control voltage Vcc10 cannot be achieved.

[0010] In view of this, it is urgent to develop a new dual-power control circuit to ensure that the two control power supplies can work together to control the on-off of a certain working power supply, especially in the application scenario of the regional control module. Utility Model Content

[0011] The purpose of the utility model is to provide a dual power supply control circuit to solve the problem in the prior art that two control power supplies are difficult to jointly control the on and off of a certain working power supply in the application scenario of a regional control module.

[0012] In order to achieve the above object, the utility model provides a dual power supply control circuit, including a transistor, a field effect transistor, a first diode, a second diode, a first resistor and a second resistor:

[0013] The dual power supply includes a first control power supply and a second control power supply;

[0014] The first control power supply is connected to the anode of the first diode, and the second control power supply is connected to the anode of the second diode;

[0015] The cathode of the first diode is connected to the base of the transistor, and the cathode of the second diode is connected to the base of the transistor;

[0016] The emitter of the transistor is grounded, and the collector of the transistor is connected to the first end of the first resistor;

[0017] The second end of the first resistor is connected to the first end of the second resistor;

[0018] The second end of the second resistor is connected to the working power supply;

[0019] The gate of the field effect tube is connected to the first end of the second resistor;

[0020] The source of the field effect tube is connected to the second end of the second resistor;

[0021] The drain of the field effect tube serves as the output voltage terminal of the control circuit.

[0022] In some embodiments, when the first control power supply outputs a high level, the transistor and the field effect tube are both in a conducting state, and the drain of the field effect tube outputs a voltage;

[0023] When the first control power supply outputs a low level, the transistor and the field effect tube are both in a non-conducting state, and the drain of the field effect tube has no voltage output;

[0024] When the second control power supply outputs a high level, the transistor and the field effect tube are both in a conducting state, and the drain of the field effect tube outputs a voltage;

[0025] When the second control power supply outputs a low level, both the transistor and the field effect transistor are in a non-conducting state, and the drain of the field effect transistor has no voltage output.

[0026] In some embodiments, a resistance ratio of the first resistor to the second resistor is set to a specified value.

[0027] In some embodiments, the dual power supply control circuit,

[0028] In some embodiments, the first capacitor is further included:

[0029] The first end of the first capacitor is connected to the first end of the second resistor;

[0030] The second end of the first capacitor is connected to the second end of the second resistor.

[0031] In some embodiments, the first diode and the second diode are integrated into the same package.

[0032] In some embodiments, the high level of the first control power supply is 3.3V, and the low level is 0V;

[0033] The high level of the second control power supply is 5V, and the low level is 0V.

[0034] In some embodiments, the field effect transistor is a P-type MOS transistor.

[0035] In some embodiments, the maximum drain-source voltage of the field effect transistor is -20V;

[0036] The gate-source threshold voltage of the field effect tube is -1V;

[0037] The maximum drain current of the field effect transistor is -3.2A.

[0038] In some embodiments, the maximum collector-emitter voltage of the transistor is 50V;

[0039] The maximum collector current of the transistor is 100mA;

[0040] The internal resistance of the transistor is 10KΩ.

[0041] In some embodiments, the first capacitor has a capacitance of 22 nF, a tolerance of 10%, a rated voltage of 100 V, and a package size of 0603.

[0042] The utility model provides a dual-power supply control circuit, which realizes that two control power supplies jointly control the on and off of a certain working power supply in the application scenario of the regional control module, fully meeting the power supply demand. At the same time, by adding a soft-start switching capacitor, the voltage drop is significantly reduced, avoiding the risk of voltage drop of the front-end working power supply, thereby ensuring the stability and reliability of the power supply system of the entire controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other features, properties and advantages of the present invention will become more apparent through the following description in conjunction with the accompanying drawings and embodiments, in which the same reference numerals represent the same features throughout, wherein:

[0044] Figure 1 A schematic diagram of a dual power supply control circuit in the prior art is disclosed;

[0045] Figure 2 The present invention discloses a dual power supply control circuit schematic diagram according to an embodiment of the present invention;

[0046] Figure 3 A simulation diagram of high and low level control waveforms of a first control power supply according to an embodiment of the present invention is disclosed;

[0047] Figure 4 A simulation diagram of high and low level control waveforms of the second control power supply according to an embodiment of the present invention is disclosed;

[0048] Figure 5 A simulation diagram of a voltage drop waveform of a working power supply according to an embodiment of the present invention is disclosed;

[0049] Figure 6 A simulation diagram after adding a soft start switch according to an embodiment of the present invention is disclosed;

[0050] Figure 7 A partial enlarged view of a simulation after adding a soft start switch according to an embodiment of the present invention is disclosed. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] Figure 2 The schematic diagram of the dual power supply control circuit according to an embodiment of the present invention is disclosed. Figure 2 As shown, the utility model proposes a dual power supply control circuit, including a transistor T1, a field effect transistor T2, a first diode D1, a second diode D2, a first resistor R1 and a second resistor R2:

[0053] The dual power supply includes a first control power supply Vcc1 and a second control power supply Vcc2;

[0054] The first control power supply Vcc1 is connected to the anode of the first diode D1, and the second control power supply Vcc2 is connected to the anode of the second diode D2;

[0055] The cathode of the first diode D1 is connected to the base B of the transistor T1, and the cathode of the second diode D2 is connected to the base B of the transistor T1;

[0056] The emitter E of the transistor T1 is grounded, and the collector C of the transistor T1 is connected to the first end of the first resistor R1;

[0057] The second end of the first resistor R1 is connected to the first end of the second resistor R2;

[0058] The second end of the second resistor R2 is connected to the working power supply VQ1;

[0059] The gate G of the field effect transistor T2 is connected to the first end of the second resistor R2;

[0060] The source electrode S of the field effect transistor T2 is connected to the second end of the second resistor R2;

[0061] The drain D of the field effect transistor T2 serves as the output voltage terminal Vs1 of the control circuit.

[0062] Furthermore, when the first control power supply Vcc1 outputs a high level, the transistor T1 and the field effect transistor T2 are both in a conducting state, and the drain of the field effect transistor T2 outputs a voltage;

[0063] When the first control power supply Vcc1 outputs a low level, the transistor T1 and the field effect transistor T2 are both in a non-conducting state, and the drain of the field effect transistor T2 has no voltage output;

[0064] When the second control power supply Vcc2 outputs a high level, the transistor T1 and the field effect transistor T2 are both in a conducting state, and the drain of the field effect transistor T2 outputs a voltage;

[0065] When the second control power supply Vcc2 outputs a low level, the transistor T1 and the field effect transistor T2 are both in a non-conducting state, and the drain of the field effect transistor T2 has no voltage output.

[0066] The first resistor R1 and the second resistor R2 serve as voltage divider resistors, and their resistance ratio is set to a specified value. In this embodiment, the first resistor R1 is 10 kΩ, the second resistor R2 is 100 kΩ, and their resistance ratio is set to 1:10.

[0067] In this embodiment, the first diode D1 and the second diode D2 are integrated into the same package. In other embodiments, the first diode D1 and the second diode D2 can also be selected as independent components.

[0068] like Figure 2 In the embodiment shown, the rear end of the output voltage terminal Vs1 of the control circuit can be connected to an RC parallel circuit, wherein one end of the RC parallel circuit is connected to the output voltage terminal Vs1 and the other end is grounded, thereby attenuating high-frequency signals and achieving a filtering effect.

[0069] In this embodiment, the field effect transistor T2 is a P-type MOS transistor, and the corresponding parameters are:

[0070] The maximum drain-source voltage VDS max of the field effect tube is -20V;

[0071] The gate-source threshold voltage of the field effect tube is -1V (i.e., the TYP value of VGSth is -1V);

[0072] The maximum drain current ID of the field effect transistor is -3.2A.

[0073] The maximum VDS (drain-source voltage) is the maximum drain-source voltage that the PMOS transistor can withstand. In this embodiment, -20V means that the PMOS transistor can withstand a maximum voltage of -20V between the drain and source. Since the source of a PMOS transistor is typically grounded (or connected to a higher voltage), a negative drain-source voltage is normal.

[0074] VGSth (gate-source threshold voltage) is the threshold voltage at which the PMOS transistor turns on. When the voltage difference between the gate voltage (VG) and the source voltage (VS) reaches this value, the PMOS transistor begins to conduct. For PMOS transistors, VGSth is a negative value. In this embodiment, the TYP value is -1V, which means that the PMOS transistor begins to conduct when the gate voltage is 1V lower than the source voltage.

[0075] ID (drain current) is the maximum drain current a PMOS transistor can carry under specific operating conditions (usually after the gate and source voltages are determined). In this example, ID is -3.2A, meaning the PMOS transistor can carry a maximum current of negative 3.2A. Note that the current here is negative because the current in a PMOS transistor flows in the opposite direction to that in an NMOS transistor.

[0076] In this embodiment, the corresponding parameters of transistor T1 are:

[0077] The maximum collector-emitter voltage VCEO max is 50V;

[0078] The maximum collector current ID max of the transistor is 100mA;

[0079] The internal resistance of the transistor is 10KΩ.

[0080] VCEO max (maximum collector-emitter voltage) is the maximum voltage that the transistor can withstand between the collector and emitter. In this embodiment, the maximum value is 50V, which means that the voltage between the collector and emitter of the transistor cannot exceed 50V to avoid device damage.

[0081] ID max (maximum collector current) is the maximum collector current that the transistor can safely carry. In this embodiment, the maximum value is 100mA, which means that when the collector current is operated below this value, the transistor can operate normally without overheating or damage.

[0082] Internal resistance usually refers to the internal resistance or characteristic resistance of a transistor in certain states, which can be the small AC signal resistance between the collector and emitter.

[0083] The utility model proposes a dual power supply control circuit, and its working logic is described as follows:

[0084] The high level of the first control power supply Vcc1 is 3.3V, and the low level is 0V. The high level of the second control power supply Vcc2 is 5V, and the low level is 0V. The working power supply VQ1 is 5V.

[0085] When the first control power supply Vcc1 is at a high level (i.e., 3.3V), the potential at test point P2, to the right of first diode D1, is approximately 2.6V. At this point, the base of transistor T1 is 2.6V higher than its emitter, satisfying the conduction condition that the potential difference between the base and emitter of transistor T1 is greater than 0.7V. Therefore, transistor T1 is turned on. Consequently, the potential at test point P3 is pulled down to approximately 0V. Simultaneously, due to the voltage divider effect of second resistor R2 and first resistor R1, the potential at test point P4, gate (G) of field-effect transistor T2, is 0.45V. Therefore, field-effect transistor T2 is turned on, and output voltage terminal Vs1 is energized.

[0086] Conversely, when the first control power supply Vcc1 is at a low level (approximately 0V), transistor T1 does not meet the conduction condition and therefore does not conduct. At this point, the potential at test point P3 or P4 is approximately 5V, and the gate (G) potential of field-effect transistor T2 also reaches 5V, equal to its source (S) potential. VGS is approximately 0V, thus not meeting the conduction condition. Therefore, field-effect transistor T2 does not conduct, and output voltage terminal Vs1 is de-energized.

[0087] Similarly, when the second control power supply Vcc2 is in a high level state (about 5V), the circuit action also makes the transistor T1 turned on, the potential of the gate (G pole) test point P4 of the field effect transistor T2 is 0.45V, the gate (G pole) potential of the field effect transistor T2 is 0.45V, and then the field effect transistor T2 is turned on, and the output voltage terminal Vs1 is energized.

[0088] When the second control power supply Vcc2 is at a low level (approximately 0V), transistor T1 does not meet the conduction condition and is therefore not conducting. The test point P4 is approximately 5V, and the gate (G) potential of field effect transistor T2 is 5V. Field effect transistor T2 does not meet the conduction condition and is not conducting, and the output voltage terminal Vs1 is powered off.

[0089] It can be seen that the dual power supply control circuit proposed in the present invention can effectively control the power-on and power-off states of the output voltage terminal Vs1 through the first control power supply Vcc1 and the second control power supply Vcc2.

[0090] Figure 3 The simulation diagram of the high and low level control waveforms of the first control power supply according to an embodiment of the present invention is disclosed, as shown in FIG. Figure 3 As shown, the red line in the figure corresponds to the first control power supply Vcc1 (alternating high and low levels), the yellow line represents the working power supply VQ1 (constant 5V voltage), and the blue line represents the voltage change of the output voltage terminal Vs1 of the control circuit.

[0091] As can be clearly seen in the figure, when the first control power supply Vcc1 is at a high level (i.e., 3.3V), the output voltage Vs1 (shown by the blue line) is correspondingly 5V. When the first control power supply Vcc1 drops to a low level (i.e., 0V), the output voltage Vs1 drops to 0V. This simulation result accurately reflects the logical relationship between the first control power supply Vcc1 and the output voltage Vs1.

[0092] Figure 4 The simulation diagram of the high and low level control waveforms of the second control power supply according to an embodiment of the present invention is disclosed. Figure 4 As shown, the red line in the figure corresponds to the second control power supply Vcc2 (alternating high and low levels), the yellow line represents the working power supply VQ1 (constant 5V voltage), and the blue line represents the voltage change of the output voltage terminal Vs1 of the control circuit.

[0093] As can be clearly seen from the figure, when the second control power supply Vcc2 is at a high level (i.e., 5V), the output voltage terminal Vs1, shown by the blue line, is correspondingly 5V. When the second control power supply Vcc2 drops to a low level (i.e., 0V), the output voltage terminal Vs1 drops to 0V. This simulation result accurately reflects the logical relationship between the second control power supply Vcc2 and the output voltage Vs1.

[0094] Figure 5 The simulation diagram of the voltage drop waveform of the working power supply according to an embodiment of the present invention is disclosed. Figure 5 As shown, when the output voltage terminal Vs1 of the control circuit faces an excessively large capacitance of the subsequent load, it is easy to trigger the voltage drop of the working power supply VQ1 at the moment when the field effect transistor T2 is turned on.

[0095] like Figure 5 As shown, the working power supply VQ1, represented by the yellow line, experiences voltage drops under certain conditions (when the red line of the first control power supply Vcc1 is high). In the regional control module, the working power supply VQ1 is crucial for powering the microcontroller MCU. If the voltage drops significantly, falling far below the 4.7V threshold, the power management chip generating the working power supply VQ1 will enter failure mode, adversely affecting the entire microcontroller's power supply system.

[0096] In order to effectively address the above problems, the dual power supply control circuit designed in this utility model specifically introduces a first capacitor C1 and configures it in parallel with the second resistor R2:

[0097] The first end of the first capacitor C1 is connected to the first end of the second resistor R2;

[0098] The second end of the first capacitor C1 is connected to the second end of the second resistor R2.

[0099] The first capacitor C1 acts as a soft-start switch. Specifically, without the first capacitor C1, FET T2 turns on immediately (0 μs). However, once the first capacitor C1 is added, the turn-on time of FET T2 is extended to approximately 50 μs, achieving a delayed (or slow) turn-on effect for FET T2.

[0100] In this embodiment, the first capacitor C1 has the following parameters:

[0101] The capacitance value is 22nF with a tolerance of 10%, the rated voltage is 100V, and the package size is 0603.

[0102] 0603 is the package size of a capacitor. According to the international standard package size notation, the 0603 package refers to the physical dimensions of the capacitor being 0.06 inches by 0.03 inches (approximately 1.6 mm by 0.8 mm). This is a common package specification for surface mount (SMD) capacitors.

[0103] Figure 6 and Figure 7 The simulation diagram and the partial enlarged diagram of the simulation after adding the soft start switch according to an embodiment of the present invention are disclosed respectively. Figure 6 and Figure 7 As shown, the present invention proposes a simulation waveform of a dual power supply control circuit after adding the first capacitor C1. It can be observed that although the yellow curve of the working power supply VQ1 has a slight decrease, the decrease is significantly reduced, and the minimum voltage value of the working power supply VQ1 is always maintained above 4.8V.

[0104] As a result, the power management chip responsible for generating the operating power supply VQ1 avoids triggering a fail-safe mode due to low voltage, ensuring the stability of the product's power supply system and normal functioning.

[0105] The dual power supply control circuit provided by the utility model has the following beneficial effects:

[0106] 1) This solves the problem of multiple power rails (such as 5V and 3.3V) in a regional controller jointly controlling a switching circuit, which cannot meet the full power supply requirements. For example, when the high level is 3.3V, the power supply to the subsequent load cannot be effectively shut down;

[0107] 2) To further optimize the performance of the control circuit, a soft-start switch capacitor was added to significantly reduce voltage drop, avoiding the risk of voltage drop in the front-end working power supply VQ1, thereby ensuring the stability and reliability of the entire controller power supply system;

[0108] 3) Compared with adding a voltage stabilization circuit to the front-end working power supply VQ1, the soft start switch capacitor solution adopted has significant cost advantages and achieves significant cost reduction.

[0109] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0110] Those skilled in the art will appreciate that information, signals, and data may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips cited throughout the foregoing description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0111] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0112] As used in this application and the claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not intended to refer to the singular but may include the plural. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements.

[0113] The above embodiments are provided for persons familiar with the art to implement or use the present invention. Personnel familiar with the art may make various modifications or changes to the above embodiments without departing from the utility model concept of the present invention. Therefore, the scope of protection of the present invention is not limited to the above embodiments, but should be the maximum scope of the innovative features mentioned in the claims.

Claims

1. A dual power supply control circuit, characterized in that: It includes a transistor, a field effect transistor, a first diode, a second diode, a first resistor and a second resistor: The dual power supply includes a first control power supply and a second control power supply; The first control power supply is connected to the anode of the first diode, and the second control power supply is connected to the anode of the second diode; The cathode of the first diode is connected to the base of the transistor, and the cathode of the second diode is connected to the base of the transistor; The emitter of the transistor is grounded, and the collector of the transistor is connected to the first end of the first resistor; The second end of the first resistor is connected to the first end of the second resistor; The second end of the second resistor is connected to the working power supply; The gate of the field effect tube is connected to the first end of the second resistor; The source of the field effect tube is connected to the second end of the second resistor; The drain of the field effect tube serves as the output voltage terminal of the control circuit.

2. The dual power supply control circuit according to claim 1, characterized in that: When the first control power supply outputs a high level, the transistor and the field effect tube are both in a conducting state, and the drain of the field effect tube outputs a voltage; When the first control power supply outputs a low level, the transistor and the field effect tube are both in a non-conducting state, and the drain of the field effect tube has no voltage output; When the second control power supply outputs a high level, the transistor and the field effect tube are both in a conducting state, and the drain of the field effect tube outputs a voltage; When the second control power supply outputs a low level, both the transistor and the field effect transistor are in a non-conducting state, and the drain of the field effect transistor has no voltage output.

3. The dual power supply control circuit according to claim 1, wherein: The resistance ratio of the first resistor to the second resistor is set to a specified value.

4. The dual power supply control circuit according to claim 1, wherein: Also included is a first capacitor: The first end of the first capacitor is connected to the first end of the second resistor; The second end of the first capacitor is connected to the second end of the second resistor.

5. The dual power supply control circuit according to claim 1, wherein: The first diode and the second diode are integrated in the same package.

6. The dual power supply control circuit according to claim 1, characterized in that: The high level of the first control power supply is 3.3V, and the low level is 0V; The high level of the second control power supply is 5V, and the low level is 0V.

7. The dual power supply control circuit according to claim 1, characterized in that: The field effect tube is a P-type MOS tube.

8. The dual power supply control circuit according to claim 7, characterized in that: The maximum drain-source voltage of the field effect tube is -20V; The gate-source threshold voltage of the field effect tube is -1V; The maximum drain current of the field effect transistor is -3.2A.

9. The dual power supply control circuit according to claim 1, wherein: The maximum collector-emitter voltage of the transistor is 50V; The maximum collector current of the transistor is 100mA; The internal resistance of the transistor is 10KΩ.

10. The dual power supply control circuit according to claim 4, characterized in that: The first capacitor has a capacitance value of 22 nF, a tolerance of 10%, a rated voltage of 100 V, and a package size of 0603.

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