Photonic element

Abstract

The present disclosure provides a photonic element comprising a first terminal comprising silicon and a second terminal comprising polysilicon. The first terminal is configured as a first three-dimensional structure, extends along a first direction, and has a first U-shaped portion in a first cross-sectional plane perpendicular to the first direction. Similarly, the second terminal is configured as a second three-dimensional structure, extends along the first direction, and has a second U-shaped portion in the first cross-sectional plane. The photonic element further includes a capacitor dielectric layer disposed between the first terminal and the second terminal, and a cladding dielectric layer surrounding the first terminal and the second terminal. The first U-shaped portion and the second U-shaped portion are arranged in an interlocking configuration with an overlapping region configured as an optical transmission line in which the first direction is a light propagation direction.

Description

Technical Field

[0001] The embodiments of the utility model relate to a photonic element, and in particular to a photonic element with an interlocking configuration. Background Art

[0002] Many computing applications use optical signals for secure, high-speed data transmission. Various emerging technologies are also being developed that provide the ability to perform computing operations directly on optical signals. Silicon photonics is a promising technology field that uses semiconductor device processing technology to provide systems that include integrated electronic and photonic components. These components can be used for light generation, routing, modulation, processing, and detection. Together, these functions form an optical analog to electronic integrated circuit (IC), and therefore can constitute a photonic integrated circuit (PIC). Summary of the Invention

[0003] An embodiment of the present disclosure provides a photonic element, comprising a first terminal comprising silicon and a second terminal comprising polysilicon. The first terminal is configured as a first three-dimensional structure, extending along a first direction and having a first U-shaped portion in a first cross-sectional plane perpendicular to the first direction. Similarly, the second terminal is configured as a second three-dimensional structure, extending along the first direction and having a second U-shaped portion in the first cross-sectional plane. The above-mentioned photonic element further comprises a capacitor dielectric layer arranged between the first terminal and the second terminal, and a coating dielectric layer surrounding the first terminal and the second terminal. The first U-shaped portion and the second U-shaped portion are arranged in an interlocking configuration, and the interlocking configuration includes an overlapping area, so that in the overlapping area, the first terminal and the second terminal further overlap in a second cross-sectional plane perpendicular to the first cross-sectional plane. Further, the overlapping area is configured as an optical transmission line, in which the first direction is the direction of light propagation.

[0004] In one embodiment, the silicon of the first terminal further includes a p-type dopant; and the polysilicon of the second terminal further includes an n-type dopant.

[0005] In one embodiment, each of the first terminal, the second terminal, and the capacitor dielectric layer includes a length along the light propagation direction, and the length is in a range of 150 micrometers to 300 micrometers.

[0006] In one embodiment, the optical transmission line comprises a width in the first cross-sectional plane, the width being between 400 nm and 500 nm; and

[0007] The optical transmission line includes a thickness located in the first cross-sectional plane, and the thickness is between 150 nanometers and 250 nanometers.

[0008] In one embodiment, each of the first terminal and the second terminal includes a plurality of connection layers, and each of the connection layers has a thickness between 50 nanometers and 80 nanometers.

[0009] In one embodiment, the capacitor dielectric layer comprises a thickness in a range of 2 nm to 7 nm.

[0010] In one embodiment, the first terminal, the second terminal, and the capacitor dielectric layer are configured as a semiconductor-insulator-semiconductor capacitor, and in response to a potential difference between 0 volts and 6 volts applied between the first terminal and the second terminal, the capacitance per unit length of the semiconductor-insulator-semiconductor capacitor in the direction of light propagation is in a range from 1 femtofarad / micrometer to 20 femtofarads / micrometer.

[0011] An embodiment of the present disclosure provides a photonic element comprising a first terminal comprising a p-type semiconductor and a second terminal comprising an n-type semiconductor. The first terminal may be configured as a first three-dimensional structure extending along a first direction and having a first overlapping portion in a first cross-sectional plane perpendicular to the first direction. Similarly, the second terminal may be a second three-dimensional structure extending along the first direction and having a second overlapping portion in a first cross-sectional plane perpendicular to the first direction. The photonic element further comprises a capacitor dielectric layer disposed between the first terminal and the second terminal, and a cladding dielectric layer surrounding the first terminal and the second terminal. The first overlapping portion and the second overlapping portion are arranged in an interlocking configuration, the interlocking configuration comprising an overlapping region such that, in the overlapping region, the first terminal and the second terminal further overlap in a second cross-sectional plane perpendicular to the first cross-sectional plane. Each of the first overlapping portion and the second overlapping portion may be folded an integer (m) times such that the overlapping region may comprise an alternating stack of m+1 first folded segments of the first terminal and m+1 second folded segments of the second terminal, where m is greater than or equal to 1. The overlapping region may further be configured as an optical transmission line, wherein the first direction is the direction of light propagation.

[0012] In one embodiment, m is greater than or equal to 2.

[0013] In one embodiment, the first terminal further comprises p-type silicon; and the second terminal further comprises n-type polysilicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The aspects of the present disclosure can be better understood from the following detailed description and accompanying drawings. It should be emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased to provide clarity and understanding.

[0015] Figure 1 is a schematic illustration of the various components that can be used in a photonic computing system.

[0016] Figure 2A A top-down view of an electro-optic modulator that can be used in photonic computing systems.

[0017] Figure 2B A top-down view of an optical switch that could be used in photonic computing systems.

[0018] Figure 2C A vertical cross-sectional view of a silicon waveguide.

[0019] Figure 2D is a vertical cross-sectional view of an electro-optic modulator having a pn junction.

[0020] Figure 3A is a vertical cross-sectional view of a photonic component with an optical transmission line according to various embodiments.

[0021] Figure 3B According to various embodiments, Figure 3A Further vertical cross-sectional view of the photonic element.

[0022] Figure 4A is a vertical cross-sectional view of another photonic component having an optical transmission line according to various embodiments.

[0023] Figure 4B According to various embodiments, Figure 4A Further vertical cross-sectional view of the photonic element.

[0024] Figure 5 is a vertical cross-sectional view of an intermediate structure that can be used to form a photonic device according to various embodiments.

[0025] Figure 6 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0026] Figure 7 is a vertical cross-sectional view of another intermediate structure that may be used to form a photonic device according to various embodiments.

[0027] Figure 8 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0028] Figure 9is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0029] Figure 10 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0030] Figure 11 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0031] Figure 12 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0032] Figure 13 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0033] Figure 14 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0034] Figure 15 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0035] Figure 16 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0036] Figure 17 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0037] Figure 18 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0038] Figure 19 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0039] Figure 20 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0040] Figure 21 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0041] Figure 22is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0042] Figure 23 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0043] Figure 24 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0044] Figure 25 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0045] Figure 26 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0046] Figure 27 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0047] Figure 28 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0048] Figure 29 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0049] Figure 30 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0050] Figure 31 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0051] Figure 32 is a vertical cross-sectional view of another intermediate structure that can be used to form a photonic device according to various embodiments.

[0052] Figure 33 is a flowchart illustrating operations of a method of forming a photonic component, according to various embodiments.

[0053] Description of reference numerals:

[0054] 100: Integrated Photonic Computing Systems

[0055] 102: Photon Source

[0056] 104: Waveguide

[0057] 106: Photodetector

[0058] 108: Optical Modulator

[0059] 110: Photon Processing Components

[0060] 200a: Electro-optical modulator

[0061] 200b: Optical switch

[0062] 200c: Silicon waveguide

[0063] 200d: Electro-optical modulator

[0064] 202a: Input waveguide

[0065] 202a1: First input waveguide

[0066] 202a2: Second input waveguide

[0067] 202b: Output waveguide

[0068] 202b1: First output waveguide

[0069] 202b2: Second output waveguide

[0070] 204a1: First waveguide segment

[0071] 204a2: Second waveguide segment

[0072] 204b1: Third waveguide segment

[0073] 204b2: Fourth waveguide segment

[0074] 206a: First modulator section

[0075] 206b: Second modulator section

[0076] 208a: First 50 / 50 beam splitter

[0077] 208b: Second 50 / 50 beam splitter

[0078] 210: Core part

[0079] 212: Dielectric layer

[0080] 212a: Lower part

[0081] 212b: Upper part

[0082] 214: Central area

[0083] 216: Dashed Line

[0084] 218a: First electrode

[0085] 218b: Second electrode

[0086] 300: Photonic components

[0087] 301: Substrate

[0088] 302a: First terminal

[0089] 302b: Second terminal

[0090] 304: Capacitor dielectric layer

[0091] 306a: First U-shaped portion

[0092] 306a1: First folded section

[0093] 306a2: Second folded section

[0094] 306a3: Third folded section

[0095] 306b: Second U-shaped portion

[0096] 306b1: First folded section

[0097] 306b2: Second folded section

[0098] 306b3: Third folded section

[0099] 308: Overlapping area

[0100] 309: Optical transmission line

[0101] 310: Electric field distribution

[0102] 312a: first electrode

[0103] 312b: Second electrode

[0104] 314a: first heavily doped semiconductor region

[0105] 314b: Second heavily doped semiconductor region

[0106] 316: Length

[0107] 318: Width

[0108] 320: thickness

[0109] 322a: thickness

[0110] 322b: thickness

[0111] 324: Thickness

[0112] 400: Photonic components

[0113] 500,600: intermediate structure

[0114] 602: p-type semiconductor

[0115] 604: Patterned photoresist

[0116] 700-900: intermediate structure

[0117] 902: n-type semiconductor

[0118] 1000-1300: intermediate structure

[0119] 1302a: First surface

[0120] 1302b: Second surface

[0121] 1400-1600: Intermediate structure

[0122] 1602a: First vertical edge portion

[0123] 1602b: Second vertical edge portion

[0124] 1700-2700: intermediate structure

[0125] 2702: Through hole

[0126] 2800: Intermediate structure

[0127] 2802: Silicon contact area

[0128] 2900,3000: intermediate structure

[0129] 3002: Opening

[0130] 3100: Intermediate structure

[0131] 3102: Through hole

[0132] 3200: Intermediate structure

[0133] 3202: Conductive materials

[0134] 3204: Self-Aligned Silicide

[0135] 3300: Method

[0136] 3302-3306: Operation

[0137] B-B', C-C', D-D': cross section DETAILED DESCRIPTION

[0138] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of the various components and arrangements of the present disclosure are described below to simplify the description. Of course, these examples are not intended to limit the present disclosure. For example, if a description includes a first feature formed on or above a second feature, it may include an embodiment in which the first feature and the second feature are formed in direct contact, and it may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. The purpose of this repetition is to simplify and clarify, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0139] Furthermore, this disclosure may use spatially relative terms, such as "below," "beneath," "below," "above," "above," and similar terms, to describe the relationship of one element or feature to other elements or features in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference numeral is assumed to be of the same material composition and have a thickness within the same thickness range.

[0140] Optical phase and amplitude modulators play an important role in photonic computing systems. An electro-optic modulator is a device with optical properties (e.g., index of refraction and absorption coefficient) that can be varied as a function of an applied electrical potential. Such an electro-optic modulator can be used to convert an electronic signal applied to the modulator into an optical signal in which data can be encoded based on time-dependent modulation of the optical signal. Various embodiments disclosed herein can provide advantages over correlative modulators by producing a larger optical phase shift for a given applied voltage than can be produced by a correlative modulator. Furthermore, various embodiments disclosed herein can provide smaller devices with reduced optical insertion loss relative to other correlative modulators. In this regard, various embodiments of the optical modulator may include a first terminal and a second terminal having an interlocking configuration including a stacked structure, the stacked structure comprising alternating connected layers of the first terminal and the second terminal. The stacked structure may improve modulation efficiency due to increased overlap between the optical mode electric field and the charge carriers of the first terminal and the second terminal, resulting in sub-1V phase modulation.

[0141] The photonic element in the embodiment may include a first terminal formed of silicon and a second terminal formed of polysilicon. The first terminal may be configured as a first three-dimensional structure, the first three-dimensional structure extending along a first direction and having a first U-shaped portion in a first cross-sectional plane perpendicular to the first direction. Similarly, the second terminal may be configured as a second three-dimensional structure, the second three-dimensional structure extending along the first direction and having a second U-shaped portion in the first cross-sectional plane. The photonic element may further include a capacitor dielectric layer arranged between the first terminal and the second terminal, and a cladding dielectric layer surrounding the first terminal and the second terminal. The first U-shaped portion and the second U-shaped portion may be arranged in an interlocking configuration, the interlocking configuration having an overlapping area, and the overlapping area is configured as an optical transmission line, in which the first direction is the optical propagation direction.

[0142] According to further embodiments, a photonic element may include a first terminal comprising a p-type semiconductor and a second terminal comprising an n-type semiconductor. The first terminal may be configured as a first three-dimensional structure, the first three-dimensional structure extending along a first direction and having a first overlapping portion in a first cross-sectional plane perpendicular to the first direction. Furthermore, the second terminal may be configured as a second three-dimensional structure, the second three-dimensional structure extending along the first direction and having a second overlapping portion in a first cross-sectional plane perpendicular to the first direction. The photonic element may further include a capacitor dielectric layer disposed between the first terminal and the second terminal, and a cladding dielectric layer surrounding the first terminal and the second terminal.

[0143] The first overlapping portion and the second overlapping portion can be arranged in an interlocking configuration, the interlocking configuration having an overlapping region such that in the overlapping region, the first terminal and the second terminal further overlap in a second cross-sectional plane perpendicular to the first cross-sectional plane. Further, each of the first overlapping portion and the second overlapping portion can be folded an integer (m) times such that the overlapping region includes an alternating stack of m+1 first folded segments of the first terminal and m+1 second folded segments of the second terminal, where m is greater than or equal to 1. The overlapping region can be configured as an optical transmission line, in which the first direction is a direction of light propagation.

[0144] In one embodiment, a method for forming a photonic device may include forming a plurality of alternating layers of a first conductivity-type semiconductor and a second conductivity-type semiconductor over a substrate, and a capacitor dielectric layer separating adjacent alternating layers. The method may further include, after the deposition process of each alternating layer is completed, performing an etching operation to reduce the width of each alternating layer. The method may also include, for each subsequent layer of a given conductivity-type semiconductor, forming a vertical edge portion of the given conductivity-type semiconductor, the vertical edge portion connecting the subsequent layer to the previously deposited thin layer of the given conductivity-type semiconductor.

[0145] The forming method may further include forming a plurality of first terminals connected to the semiconductor layer of the first conductivity type, thereby forming a first terminal having a first overlapping portion in a first cross-sectional plane perpendicular to the first direction. Similarly, the forming method may further include forming a plurality of second terminals connected to the semiconductor layer of the second conductivity type, thereby forming a second terminal having a second overlapping portion in the first cross-sectional plane. The forming method may further include arranging the first overlapping portion and the second overlapping portion in an interlocking configuration, the interlocking configuration having an overlapping portion such that, in the overlapping portion, the first terminal and the second terminal further overlap in a second cross-sectional plane perpendicular to the first cross-sectional plane.

[0146] Figure 1 is a schematic diagram of an integrated photonic computing system 100 according to various embodiments. System components may include a generating device, also referred to as a photon source 102 (e.g., a laser or light emitting diode (LED), a routing device, which may include a plurality of waveguides 104 configured to route optical signals, and a detector, which may include one or more optical detectors 106, configured to detect optical signals and convert received optical signals into output electronic signals. Additional components may include a modulation device, which may include one or more optical modulators 108 and a photonic processing component 110. The photonic processing component 110 may be configured to perform logic operations on the modulated optical signals provided by the optical modulators 108. The one or more optical modulators 108 may be configured to apply amplitude and / or phase modulation to the input optical signal generated by the photon source 102. As described below with reference to Figure 3A and Figure 3B As described in more detail, the photonic element 300 of the embodiment can be used as an improved optical modulator 108 in the integrated photonic system 100 .

[0147] One or more optical modulators 108 can take an input electronic signal and modulate the input optical signal to apply amplitude and / or phase modulation in response to the input electronic signal. In this manner, one or more optical modulators 108 can be used to convert data provided in the form of an electronic signal into data encoded in a photon signal. Similarly, one or more photodetectors 106 can convert the processed photon signal back into an output electronic signal.

[0148] Figure 2A The top view of the electro-optic modulator 200a is shown. The electro-optic modulator 200a can be used in a photonic computing system. The cross section C-C' indicates the definition of Figure 2C The vertical plane of the vertical cross-section shown, while the section D-D' indicates the definition Figure 2D The vertical cross-sectional view is shown in a vertical plane. The electro-optic modulator 200a may include an input waveguide 202a and an output waveguide 202b. The input waveguide 202a may be configured to receive an input optical signal, while the output waveguide 202b may be configured to provide an output signal, wherein the output signal is a modulated version of the input optical signal. As shown, the input waveguide 202a may branch into a first waveguide segment 204a1 and a second waveguide segment 204a2. Thus, the input waveguide 202a, the first waveguide segment 204a1, and the second waveguide segment 204a2 may function as a beam splitter.

[0149] The input signal received by the input waveguide 202a can be split into two optical signals (i.e., two copies of the input optical signal), which can be carried by a first waveguide segment 204a1 and a second waveguide segment 204a2, respectively. The first optical signal carried by the first waveguide segment 204a1 can be provided to a first modulator section 206a, and the second optical signal carried by the second waveguide segment 204a2 can be provided to a second modulator section 206b. The first modulator section 206a and the second modulator section 206b can modify the amplitude and / or phase of the corresponding first and second optical signals.

[0150] The modified first optical signal is transmitted along the third waveguide segment 204b1, and the modified second optical signal is transmitted along the fourth waveguide segment 204b2, and can then be combined to form an output optical signal provided to the output waveguide 202b. In this regard, the third waveguide segment 204b1 can be optically coupled to the first modulator section 206a, and the fourth waveguide segment 204b2 can be optically coupled to the second modulator section 206b. The third waveguide segment 204b1 and the fourth waveguide segment 204b2 can then be optically coupled to the output waveguide 202b. In this manner, the third waveguide segment 204b1, the fourth waveguide segment 204b2, and the second waveguide 202b can act as a beam combiner. Each of the first modulator section 206a and the second modulator section 206b can modulate the corresponding first and second optical signals based on the electro-optic effect. In this regard, each of the first modulator portion 206a and the second modulator portion 206b may include a material having electro-optical properties. Such an electro-optical material may have optical properties (e.g., refractive index and absorption coefficient) that can be varied as a function of an applied electrical bias (i.e., a voltage difference).

[0151] Figure 2B is a top view of an optical switch 200b, which can be used in a photonic computing system. Section C-C' indicates the definition Figure 2C The vertical plane of the vertical cross-section shown, while the section D-D' indicates the definition Figure 2D The vertical plane of the vertical cross-sectional view shown. The optical switch 200b may include a first input waveguide 202a1, a second input waveguide 202a2, a first output waveguide 202b1, and a second output waveguide 202b2. Each of the first input waveguide 202a1, the second input waveguide 202a2, the first output waveguide 202b1, and the second output waveguide 202b2 may be configured to support a single-mode or multi-mode beam carrying an optical signal. In an exemplary embodiment, the optical switch 200b may be implemented as a Mach-Zehnder interferometer integrated with a first 50 / 50 beam splitter 208a and a second 50 / 50 beam splitter 208b. Figure 2B As shown, each of the first input waveguide 202a1 and the second input waveguide 202a2 can be optically coupled to a first 50 / 50 beam splitter 208a (also known as a directional coupler). The first 50 / 50 beam splitter 208a can receive the first optical signal from the first input waveguide 202a1 and the second optical signal from the second input waveguide 202a2.

[0152] Through evanescent coupling, the first 50% of the first optical signal can be guided into the first waveguide segment 204a1, and the second 50% of the first optical signal can be guided into the second waveguide segment 204a2. Simultaneously, the first 50% of the second optical signal can be guided into the first waveguide segment 204a1, and the second 50% of the second optical signal can be guided into the second waveguide segment 204a2. In this regard, the first and second optical signals can be evenly distributed between the first and second waveguide segments 204a1, 204a2.

[0153] The first modulator portion 206a and the second modulator portion 206b can receive signals from the first waveguide segment 204a1 and the second waveguide segment 204a2, respectively, and can be used to adjust the amplitude and / or phase of the received signals. In this regard, each of the first modulator portion 206a and the second modulator portion 206b can include an electro-optical material having optical properties (e.g., refractive index and absorption coefficient) that can be changed as a function of an applied electrical bias voltage. As such, in some embodiments, the phase of the optical signal propagated by the first modulator portion 206a and the second modulator portion 206b can be controllably changed by applying a predetermined bias voltage.

[0154] After propagating through the first 50 / 50 beam splitter 208a, the signals propagating through the first waveguide segment 204a1 and the second waveguide segment 204a2 can have a well-defined phase relationship relative to each other (e.g., in-phase, 180° out-of-phase, etc.). Thus, the first modulator section 206a and the second modulator section 206b can introduce a predetermined phase difference between the signals received from the first waveguide segment 204a1 and the second waveguide segment 204a2, respectively. The signal propagating through the first modulator section 206a can then be provided as an output to the third waveguide segment 204b1, and the signal propagating through the second modulator section 206b can then be provided as an output to the fourth waveguide segment 204b2. The corresponding signals received from the third waveguide segment 204b1 and the fourth waveguide segment 204b2 can then be provided to the second 50 / 50 beam splitter 208b.

[0155] Next, a second 50 / 50 beam splitter can be used to send the first 50% of the signals received from the third waveguide segment 204b1 to the first output waveguide 202b1 and the second 50% of the signals received from the third waveguide segment 204b1 to the second output waveguide 202b2. Simultaneously, the first 50% of the signals received from the fourth waveguide segment 204b2 can be sent to the first output waveguide 202b1, and the second 50% of the signals received from the fourth waveguide segment 204b2 can be sent to the second output waveguide 202b2.

[0156] The relative phase between the signals propagating in the third waveguide segment 204b1 and the fourth waveguide segment 204b2 can determine which signals appear in the first output waveguide 202b1 and the second output waveguide 202b2. Due to the phenomena of constructive and destructive interference, the signal can be switched so that it appears only in the first output waveguide 202b1 (e.g., the beams can be in-phase) or only in the second output waveguide 202b2 (e.g., the beams can be out of phase). Thus, by applying certain predetermined bias voltages to the first modulator section 206a and the second modulator section 206b, the optical switch 200b can provide a switching function, as the optical signal can be directed to either the first output waveguide 202b1 or the second optical waveguide 202b2 as a function of the bias voltages applied to the first modulator section 206a and the second modulator section 206b. Although both arms of the Mach-Zehnder interferometer are shown as including phase adjustment portions (ie, first modulator portion 206a and second modulator portion 206b), other embodiments may include a Mach-Zehnder interferometer having a phase adjustment device in only a single arm.

[0157] although Figure 2B An embodiment of a Mach-Zehnder interferometer is shown in FIG, but the embodiments may not be limited to this particular switch architecture. Various other phase adjustment devices may be included within the scope of the present disclosure, including ring resonator designs, Mach-Zehnder modulators, generalized Mach-Zehnder modulators, etc. In some embodiments, the optical phase shifter devices described herein may be used within a quantum computing system. Alternatively, these optical phase shifter devices may be used in other types of optical systems. For example, in various embodiments, other computing, communication and / or technology systems may utilize photonic phase shifters to guide optical signals (e.g., single photons or continuous wave (CW) optical signals) within a system or network, and the phase shifter architecture described herein may be used in these systems.

[0158] Figure 2Cis a vertical cross-sectional view of the silicon waveguide 200c. As described above, Figure 2C The vertical plane of the drawings shown is drawn by Figure 2A and Figure 2B The silicon waveguide 200c may include a core portion 210 and a cladding portion (e.g., a cladding dielectric layer 212). Each of the core portion 210 and the cladding portion (e.g., the cladding dielectric layer 212) may be configured to be transparent to a particular wavelength of light (e.g., infrared radiation). The core portion 210 and the cladding portion (e.g., the cladding dielectric layer 212) may be formed using semiconductor device manufacturing processes, as described in more detail below.

[0159] The core portion 210 can be configured to have a higher refractive index than the refractive index of the cladding portion (e.g., the cladding dielectric layer 212). For example, the core portion 210 can be formed of doped or undoped silicon (e.g., a refractive index of 3.88), while the cladding portion (e.g., the cladding dielectric layer 212) can be formed of silicon oxide (e.g., a refractive index of 1.46). Due to total internal reflection (TIR) caused by the higher refractive index of the core portion 210 relative to the cladding portion (e.g., the cladding dielectric layer 212), light can preferentially propagate within the core portion 210. For example, an optical mode can propagate within the core portion 210 and can have an electric field distribution confined to the central region 214 of the core portion. Figure 2C The particular shape of the core portion 210 shown is by way of example only, and in other applications the core portion 210 may have various other shapes.

[0160] Figure 2D is a vertical cross-sectional view of an exemplary electro-optic modulator 200d having a pn junction. As described above, Figure 2D The vertical plane of the drawings shown is drawn by Figure 2A and Figure 2B The electro-optical modulator 200d may include a device similar to that previously described with reference to Figure 2C The silicon waveguide 200c has a core portion 210 and a cladding portion (e.g., a cladding dielectric layer 212). As a result, the optical mode can propagate within the core portion 210 and can have an electric field distribution confined to the central region 214 of the core portion. Figure 2CIn contrast to silicon waveguide 200c, core portion 210 of electro-optic modulator 200d can have a doping profile that exhibits an electro-optic effect. For example, central region 214 of electro-optic modulator 200d can be doped to form a pn junction. For example, central region 214 can include p-type dopants on a first side of central region 214 (e.g., to the left of dashed line 216) and n-type dopants on a second side of central region 214 (e.g., to the right of dashed line 216).

[0161] The electro-optic modulator 200d may further include a first electrode 218a and a second electrode 218b. A potential difference (i.e., a voltage difference or bias) applied between the first electrode 218a and the second electrode 218b may change the distribution of charge carriers within the central region 214. Based on the free carrier dispersion effect in silicon, the optical properties of the central region 214 can be changed by changing the carrier distribution by applying a bias. For example, in a forward bias, carriers may be injected into the pn junction, thereby reducing the size of the depletion region. In a reverse bias, carriers may be depleted, thereby increasing the size of the depletion region. In one configuration, the electro-optic modulator 200d may be operated in a reverse bias (i.e., depletion mode) to have a low concentration of free carriers, so that the central region 214 exhibits relatively low optical absorption.

[0162] According to various embodiments, Figure 3A is a vertical cross-sectional view of a photonic element 300 having an optical transmission line 309, and Figure 3B for Figure 3A A further vertical cross-sectional view of the photonic element is defined as Figure 3B The plane of the vertical cross-section is Figure 3A The photonic element 300 may include a first terminal 302a formed of silicon and a second terminal 302b formed of polysilicon. A cladding dielectric layer 212 may be formed over the substrate 301 and may be formed to surround the first terminal 302a and the second terminal 302b.

[0163] The capacitor dielectric layer 304 may be disposed between the first terminal 302a and the second terminal 302b. In some embodiments, the capacitor dielectric layer 304 may be formed of the same material as the cladding dielectric layer 212. Alternatively, it may be formed of a different material than the cladding dielectric layer 212. For example, in some embodiments, the cladding dielectric layer 212 and the capacitor dielectric layer 304 may each be formed of silicon oxide. In other embodiments, the cladding dielectric layer 212 may be silicon dioxide, while the cladding dielectric layer 212 may be a high-k dielectric material. In other embodiments, various other dielectric materials may be used for the capacitor dielectric layer 304 and the cladding dielectric layer 212.

[0164] The first terminal 302a may be formed along a first direction (ie, along Figure 3B In this exemplary embodiment, the first direction is directed to Figure 3A plane (i.e., the xz plane) and is displayed as Figure 3B Similarly, the second terminal 302b can be formed into a second three-dimensional structure extending along the first direction (ie, along the y-axis). Figure 3A As shown, the first terminal can be configured to Figure 3A The first U-shaped portion 306a is provided in a plane perpendicular to the first direction (ie, the y direction). Similarly, the second terminal 302b can be configured to have a second U-shaped portion 306b in the first cross-sectional plane.

[0165] as Figure 3A As further shown, the first U-shaped portion 306a and the second U-shaped portion 306b can be arranged in an interlocking configuration having an overlapping region 308 such that in the overlapping region, the first terminal 302a and the second terminal 302b further overlap in a second cross-sectional plane (i.e., a yz plane) perpendicular to the first cross-sectional plane, as shown in FIG. Figure 3B In this regard, the first U-shaped portion 306a may include a first folded segment 306a1 and a second folded segment 306a2. Similarly, the second U-shaped portion 306b may further include a first folded segment 306b1 and a second folded segment 306b2.

[0166] The overlapping region 308 can be configured as an optical transmission line 309 in which the first direction (i.e., the y-direction) is the direction of light propagation. In this regard, the size, spacing, and relative optical properties (i.e., dielectric constant and absorption constant) of the first terminal 302a, the second terminal 302b, and the capacitor dielectric layer 304 can be configured to allow the propagation of an optical mode (i.e., an electromagnetic wave) that propagates along the first direction (i.e., the y-direction) and has an electric field distribution 310 in a first cross-sectional plane (i.e., the xz plane) that spatially overlaps the first terminal 302a and the second terminal 302b. In this way, the overlapping region 308 is similar to the previously described method with reference to FIG. Figure 2C In this regard, in photonic circuits (e.g., see Figure 2A The optical mode propagating in the silicon waveguide 200c in Figure 3A and Figure 3B The optical transmission line 309 is formed by the overlapping area 308 of the photonic elements 300.

[0167] The properties of the optical mode propagating in the optical transmission line 309 can be controlled by changing the optical properties of the first terminal 302a and the second terminal 302b. In this regard, the first terminal 302a, the second terminal 302b and the capacitor dielectric layer 304 can be configured as a semiconductor-insulator-semiconductor capacitor that exhibits an electro-optical effect. Figure 2D As described above, due to the free carrier dispersion effect in silicon and polysilicon, the optical properties of the first terminal 302a and the second terminal 302b can be changed by applying a potential difference (i.e., a voltage difference or bias) between the first terminal 302a and the second terminal 302b. When the potential difference is applied, carriers of opposite signs can be established on both sides of the capacitor dielectric layer 304. For example, the silicon of the first terminal 302a can have a p-type doping effect, and the polysilicon of the second terminal 302b can have an n-type doping effect. As a result, in response to the applied potential difference, a positive charge density can be generated on the surface of the first terminal 302a, and a negative charge density can be generated on the surface of the second terminal 302b.

[0168] like Figure 3AAs shown, the first terminal 302a can be electrically connected to the first electrode 312a via the first heavily doped semiconductor region 314a, and the second terminal 302b can be electrically connected to the second electrode 312b via the second heavily doped semiconductor region 314b. The presence of the first heavily doped semiconductor region 314a and the second heavily doped semiconductor region 314b can allow ohmic contacts to be formed between the first electrode 312a and the first terminal 302a, and between the second electrode 312b and the second terminal 302b. In this way, the voltage applied to the first electrode 312a and the second electrode 312b can be used to control the optical properties of the optical transmission line 309 by causing changes in the charge density formed on the first terminal 302a and the second terminal 302b.

[0169] The magnitude of the positive and negative charge densities at the first and second terminals 302a, 302b, respectively, depends on the magnitude of the applied potential difference (i.e., the voltage difference between the first and second electrodes 312a, 312b). The electro-optical effect resulting from free carrier dispersion depends on the magnitude of the positive and negative charge densities at the first and second terminals 302a, 302b. Thus, the optical properties of the optical transmission line 309 can be controlled by controlling the applied potential difference between the first and second terminals 302a, 302b. In this regard, in response to a first potential difference V1 applied between the first and second terminals 302a, 302b, the optical transmission line 309 can have a first effective refractive index n1, and in response to a second potential difference V2 applied between the first and second terminals 302a, 302b, the optical transmission line 309 can have a second effective refractive index n2. Therefore, the characteristics of the propagating optical mode can be controlled by applying a specific potential difference V=V1-V2 between the first terminal 302a and the second terminal 302b, as described in more detail below.

[0170] Generally speaking, the phase of an optical mode propagating in optical transmission line 309 depends on the effective refractive index and the distance traveled by the optical mode. Therefore, for a sufficiently long propagation distance, a predetermined phase shift of the optical mode can be achieved when a predetermined potential difference V is applied. The efficiency of a phase modulator can be quantified by specifying the voltage-times-distance product, Vπ·Lπ, where the voltage-times-distance product, Vπ·Lπ, specifies the applied voltage, Vπ, and the propagation distance, Lπ, at which the phase of the optical mode can shift by π radians (i.e., 180°). This product means that, for a given propagation distance, Lπ, a phase shift of π radians can be achieved by applying a voltage (i.e., a potential difference) of Vπ. Similarly, for an applied voltage, Vπ, a phase shift of π radians can be achieved when the optical mode propagates a distance, Lπ. Therefore, the smaller the value of the voltage-times-distance product, Vπ·Lπ, the better the phase modulator. In this sense, the voltage times distance product Vπ·Lπ can be used as a figure of merit to compare the relative performance of various optical phase modulators.

[0171] According to some embodiments, Figure 3A and Figure 3B The photonic element 300 can have a voltage times distance product Vπ·Lπ of less than 0.1 volt centimeters (V·cm). This means that the photonic element 300 has a voltage times distance product Vπ·Lπ of less than 0.1 volt centimeters (V·cm). Figure 3A The photonic element 300 with a length of, for example, 300 microns (ie, Lπ≈300 microns) (i.e., Lπ≈300 microns) can cause a phase shift of π radians when a voltage of Vπ≈3.3 V is applied.

[0172] As another example, a photonic element 300 having a voltage multiplied by distance product Vπ·Lπ of 0.06 V·cm and a length along the propagation direction of Lπ≈150 microns can be controlled to produce a phase shift of π radians when a voltage of Vπ≈4.0 V is applied. Thus, according to various embodiments, the photonic element 300 can be configured such that each of the first terminal 302a, the second terminal 302b, and the capacitor dielectric layer 304 has a length 316 along the light propagation direction (e.g., see FIG. 3 ). Figure 3B ), the length 316 is in the range of about 150 microns to about 300 microns. The photonic element 300 can be configured to act as an optical modulator that can induce a phase shift of π radians by applying a voltage between 1V and 6V.

[0173] The optical properties of the photonic element 300 may depend on the material properties of the various components and the dimensions of the various components. In this regard, the dimensions of the optical transmission line 309 may be comparable to or smaller than the wavelength of the optical mode that can propagate on the optical transmission line 309. Figure 1 ) typically has a wavelength of one of 850 nm, 1300 nm, or 1550 nm. Consequently, components of the optical transmission line 309 can have dimensions comparable to or smaller than these wavelengths. In an exemplary embodiment, the photonic element 300 can include an optical transmission line 309 having a width 318 in a first cross-sectional plane (i.e., the xz plane) between 400 nm and 500 nm, and a thickness 320 in the first cross-sectional plane between 150 nm and 250 nm.

[0174] As described above, the photonic device 300 can be designed to support an optical mode (i.e., an electromagnetic wave) that propagates along a first direction (i.e., the y-direction) and has an electric field distribution 310 in a first cross-sectional plane (i.e., the xz plane) that spatially overlaps the first terminal 302a and the second terminal 302b. An electric field distribution 310 with increased spatial overlap between the first terminal 302a and the second terminal 302b can provide increased efficiency (e.g., a lower quality factor Vπ·Lπ) for the photonic device 300, compared to other embodiments with reduced spatial overlap. In this regard, the thickness of each connecting layer of the first terminal 302a and the second terminal 302b can be selected to be less than the wavelength of the propagating optical mode. According to some embodiments, the first terminal 302a can include multiple connecting layers (a first folded segment 306a1 and a second folded segment 306a2), each of which can have a thickness 322a between 50 nm and 80 nm. Similarly, the second terminal 302b may include a plurality of connecting layers (a first folded segment 306b1 and a second folded segment 306b2), each of which may also have a thickness 322b between 50 nm and 80 nm. In various embodiments, the capacitor dielectric layer 304 may be selected to have a thickness 324 in the range of approximately 2 nm to 7 nm.

[0175] As described above, the overlapping region 308 forming the optical transmission line 309 can function as a semiconductor-insulator-semiconductor capacitor structure. In certain embodiments, in response to a potential difference between 0V and 6V applied between the first terminal and the second terminal, this capacitor structure can have a capacitance per unit length in the direction of light propagation ranging from approximately 1 fF (femtofarad) / micrometer to approximately 20 fF / micrometer. The use of thin layers (first folded segment 306a1, second folded segment 306a2, first folded segment 306b1, second folded segment 306b2) provides these capacitance values and can allow the photonic element 300 to operate efficiently with relatively low light absorption relative to a control example element having thicker thin layers. For example, in certain embodiments, the optical transmission line 309 of the photonic element 300 can exhibit an optical insertion loss of less than 0.5 dB relative to a silicon waveguide structure.

[0176] According to various embodiments, Figure 4A is a vertical cross-sectional view of another photonic element 400 having an optical transmission line 309, and Figure 4B for Figure 4A A further vertical cross-sectional view of the photonic element 400 is defined as follows: Figure 4B The plane of the vertical cross-section is Figure 4A The photonic element 400 may be similar to Figure 3A and Figure 3B In this regard, the photonic element 400 may include a p-type semiconductor 602 (see Figure 6 ) formed by the first terminal 302a, and the n-type semiconductor 902 (see Figure 9 Each of the first terminal 302a and the second terminal 302b can be configured as a three-dimensional structure. The three-dimensional structure is arranged along the first direction (ie, into Figure 4A The plane and Figure 4B The first terminal 302a and the second terminal 302b may extend along the y-axis and have an overlapping portion (i.e., within the overlapping region 308) in a first cross-sectional plane (i.e., the xz plane) perpendicular to the first direction (i.e., the y-axis). The corresponding overlapping portions of the first terminal 302a and the second terminal 302b may be arranged in an interlocking configuration within the overlapping region 308, such that, in the overlapping region, the first terminal 302a and the second terminal 302b are further aligned in a second cross-sectional plane (i.e., the xz plane) perpendicular to the first cross-sectional plane. Figure 4B overlap in the yz plane).

[0177] as Figure 3A and Figure 3B The photonic element 300, Figure 4A and Figure 4BThe photonic element 400 may further include a capacitor dielectric layer 304 disposed between the first terminal 302a and the second terminal 302b, and a cladding dielectric layer 212 surrounding the first terminal 302a and the second terminal 302b. Figure 3A and Figure 3B The photonic element 300, Figure 4A and Figure 4B The overlapping region 308 of the photonic element 400 can be further configured as an optical transmission line 309, in which a first direction (i.e., the y-axis) is the direction of light propagation. For example, the sizes, spacing, and relative optical properties (i.e., dielectric constant and absorption constant) of the first terminal 302a, the second terminal 302b, and the capacitor dielectric layer 304 can allow propagation of an optical mode (i.e., an electromagnetic wave) that propagates along the first direction (i.e., the y-direction) and has an electric field distribution 310 in a first cross-sectional plane (i.e., the xz plane) that spatially overlaps the first terminal 302a and the second terminal 302b.

[0178] However, unlike Figure 3A and Figure 3B The overlapping region 308 of the photonic element 300 may have additional structures. In this regard, Figure 4A and Figure 4B As shown, within the overlapping region 308, each of the first terminal 302a and the second terminal 302b can be folded twice to have three overlapping sections. Figure 4B As shown, the first terminal 302a may have a first folded section 306a1, a second folded section 306a2, and a third folded section 306a3. Similarly, the second terminal 302b may have a first folded section 306b1, a second folded section 306b2, and a third folded section 306b3.

[0179] In further embodiments, the overlap region 308 may include various numbers of folded segments. For example, each of the first terminal 302a and the second terminal 302b may be folded an integer number (m) of times (not shown), such that the overlap region 308 includes an alternating stack of m+1 first folded segments of the first terminal 302a and m+1 second folded segments of the second terminal 302b. In these embodiments, the integer m may be greater than or equal to 1. Figure 4A and Figure 4B The photonic element 400 of the embodiment is an example of m = 2. Various other embodiments may have m = 3, 4, 5, etc.

[0180] The overlapping region 308 can be configured as an optical transmission line 309 that supports an optical mode having an electric field distribution 310 in a first cross-sectional plane (i.e., xz plane) that spatially overlaps with each of the m+1 first folded segments of the first terminal 302a and each of the m+1 second folded segments of the second terminal 302b. Figure 3A and Figure 3B In an embodiment of the photonic element 300, the first terminal 302a may include p-type silicon (e.g., p-type semiconductor 602), and the second terminal may include n-type polysilicon (e.g., n-type semiconductor 902). In other embodiments, various other semiconductor materials (e.g., oxide semiconductors) may be used. Various dimensions may be optimized to have a relative Figure 3A and Figure 3B The photonic element 400 can have similar or improved performance to the embodiment of the photonic element 300. For example, in some embodiments, the photonic element 400 can have a voltage times length product Vπ·Lπ (representing a 180° phase shift of an optical mode propagating in an optical transmission line) of less than 0.1 V-cm and an optical insertion loss of less than 0.5 dB relative to a silicon waveguide structure.

[0181] Figure 5 FIG2 is a vertical cross-sectional view of an intermediate structure 500 that can be used to form a photonic device (e.g., photonic devices 300 and 400) according to various embodiments. The intermediate structure 500 can include a cladding dielectric layer 212 formed over a substrate 301. The substrate 301 can include a bulk semiconductor substrate, such as a silicon substrate, in which a semiconductor material layer extends continuously from a top surface of the substrate 301 to a bottom surface of the substrate 301, or a semiconductor-on-insulator layer, including a semiconductor material layer as a top semiconductor layer overlying a buried insulator layer (e.g., a silicon oxide layer).

[0182] The capping dielectric layer 212 can be formed of a suitable dielectric material, such as silicon dioxide (SiO2), silicon nitride (SiN, Si3N4), silicon carbide (SiC), undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Other dielectric materials are also contemplated by the present disclosure. The capping dielectric layer 212 can be deposited by a conformal deposition process (e.g., low-pressure chemical vapor deposition (CVD)) or a self-planarizing deposition process (e.g., spin coating). Other conformal deposition processes may include plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), sputtering, laser ablation, etc. Excess material of the deposited capping dielectric layer 212 may be removed from above the top surface of the intermediate structure 500 by a planarization process, such as chemical mechanical planarization (CMP).

[0183] Figure 6 FIG2 is a vertical cross-sectional view of a further intermediate structure 600 that can be used to form a photonic element (e.g., photonic elements 300 and 400), according to various embodiments. The intermediate structure 600 can be formed by depositing a blanket layer of silicon (e.g., a p-type semiconductor 602) over the capping dielectric layer 212, and then forming a patterned photoresist 604 over the blanket layer of silicon (e.g., a p-type semiconductor 602). The blanket layer of silicon (e.g., a p-type semiconductor 602) can be formed by performing an epitaxial growth process using a technique such as CVD. The blanket layer of silicon (e.g., a p-type semiconductor 602) can be further doped using an in-situ doping process.

[0184] In-situ doping during the CVD deposition of an epitaxial silicon layer enables the fabrication of thin, highly doped layers of crystalline silicon with high dopant activation. This process does not add ion implantation-mediated damage to the silicon crystal structure, which could result in enhanced dopant diffusion, additional optical losses, and other complications during epitaxial overgrowth. Compared to ion implantation, in-situ doping allows for better control of dopant layer thickness, particularly for boron, for which forming highly doped shallow wells using ion implantation techniques is particularly challenging. Furthermore, in-situ doped silicon does not require dopant activation, so thermal exposure after deposition of the in-situ doped layer is limited to subsequent silicon deposition (below 800°C). In this way, a blanket layer of silicon (e.g., p-type semiconductor 602) can be formed as a crystalline layer that is uniformly deposited at a deposition rate of approximately 5 nm / min using CVD using disilane (Si2H6) as a precursor at 800°C. Dopants, such as for p-type doping, can be added by introducing diborane (B2H6). A blanket layer of silicon (eg, p-type semiconductor 602 ) may be deposited to have a thickness between 50 nm and 80 nm.

[0185] The patterned photoresist 604 can be formed by depositing a blanket layer of photoresist (not shown) over a blanket layer of silicon (e.g., p-type semiconductor 602). The blanket layer of photoresist can then be patterned using photolithography techniques to form the patterned photoresist 604. The patterned photoresist 604 can then serve as an etch mask during a subsequent etching process that can be performed to etch the blanket layer of silicon (e.g., p-type semiconductor 602).

[0186] Figure 7 FIG. 7 is a vertical cross-sectional view of a further intermediate structure 700 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. In this regard, the photonic element 700 can be formed by using Figure 6 The patterned photoresist 604 is used as an etching mask to selectively perform an anisotropic etching process on the capping dielectric layer 212 to Figure 6 In this regard, the anisotropic etching process can reduce the width of the blanket layer of silicon (eg, p-type semiconductor 602), such as Figure 7 The obtained p-type doped silicon layer can form the aforementioned reference Figure 3B and Figure 4B The first folded section 306a1 of the first terminal 302a is shown in FIG. After the anisotropic etching process, the patterned photoresist 604 may be removed, for example, by ashing or dissolving with a solvent.

[0187] Figure 8 FIG. 8 is a vertical cross-sectional view of a further intermediate structure 800 that can be used to form a photonic device (e.g., photonic device 300, 400) according to various embodiments. Figure 7 The intermediate structure 700 is formed into the intermediate structure 800. In this regard, a blanket layer of dielectric material (not shown) can be deposited over the intermediate structure 700 by performing a compliant deposition process such as CVD or a self-planarizing deposition process (e.g., spin coating). Other compliant deposition processes can include PECVD, ALD, PVD, HDPCVD, MOCVD, sputtering, laser ablation, etc. Excess material of the deposited capping dielectric layer 212 can be removed from above the top surface of the intermediate structure 800 by a planarization process, such as CMP.

[0188] Figure 9 FIG. 8 is a vertical cross-sectional view of a further intermediate structure 900 that can be used to form a photonic element (e.g., photonic element 300, 400) according to various embodiments. A blanket layer of polysilicon (e.g., n-type semiconductor 902) can be deposited over the intermediate structure 800 and a patterned photoresist 604 can be formed over the blanket layer of polysilicon (e.g., n-type semiconductor 902) to form a photoresist layer. Figure 8 The intermediate structure 800 is formed into an intermediate structure 900. The blanket layer of polycrystalline silicon (e.g., n-type semiconductor 902) can be deposited using CVD or a low-temperature CVD (LPCVD) process. For example, in the LPCVD process, silane gas can be used as a precursor and can dissociate into silicon and hydrogen at a pressure between 25 Pa (Pascals) and 150 Pa and a temperature of approximately 600°C. The silane gas can be introduced in the form of 100% silane or 20% to 30% silane diluted with nitrogen. Like the blanket layer of silicon (e.g., p-type semiconductor 602), the blanket layer of polycrystalline silicon (e.g., n-type semiconductor 902) can be deposited using an in-situ doping process. In this regard, n-type dopants such as phosphorus can be introduced by combining silane with phosphine gas (PH3) in the LPCVD reaction chamber. In this manner, a blanket layer of polysilicon (eg, n-type semiconductor 902 ) may be deposited as n-type polysilicon.

[0189] The patterned photoresist 604 can be formed by depositing a photoresist blanket layer (not shown) over a blanket layer of polysilicon (e.g., n-type semiconductor 902). The photoresist blanket layer can then be patterned using photolithography techniques to form the patterned photoresist 604. The patterned photoresist 604 can then serve as an etch mask during a subsequent etching process that can be performed to etch the blanket layer of polysilicon (e.g., n-type semiconductor 902).

[0190] Figure 10 is a vertical cross-sectional view of a further intermediate structure 1000 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 9 The patterned photoresist 604 is used as an etching mask to selectively perform an anisotropic etching process on the capping dielectric layer 212 to Figure 9 In this regard, the anisotropic etching process can reduce the Figure 9 The width of the blanket layer of polysilicon (eg, n-type semiconductor 902) is shown. The obtained n-type doped polysilicon layer can form the aforementioned Figure 3B and Figure 4B The first folded section 306b1 of the second terminal 302b. After the anisotropic etching process, the patterned photoresist 604 can be removed, for example, by ashing or dissolving with a solvent. Figure 10 As shown, the thin layer of the dielectric layer 212 formed between the first folded section 306a1 of the first terminal 302a and the first folded section 306b1 of the second terminal 302b can play the role previously described with reference to FIG. Figure 3A The capacitor dielectric layer 304.

[0191] Figure 11 FIG. 1 is a vertical cross-sectional view of a further intermediate structure 1100 that can be used to form a photonic device (e.g., photonic device 300, 400) according to various embodiments. An additional cladding dielectric layer 212 can be formed above the intermediate structure 1000 to Figure 10 The intermediate structure 1000 is formed into an intermediate structure 1100. In this regard, a blanket layer of dielectric material (not shown) can be deposited over the intermediate structure 1000 by performing a compliant deposition process such as CVD or a self-planarizing deposition process (e.g., spin coating). Other compliant deposition processes can include PECVD, ALD, PVD, HDPCVD, MOCVD, sputtering, laser ablation, etc. Excess material of the deposited capping dielectric layer 212 can be removed from above the top surface of the intermediate structure 1100 by a planarization process, such as CMP.

[0192] Figure 12 FIG. 1 is a vertical cross-sectional view of a further intermediate structure 1200 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 11 A patterned photoresist 604 is formed above the intermediate structure 1100 to Figure 11 The intermediate structure 1100 is formed into the intermediate structure 1200. The patterned photoresist 604 can be formed by depositing a photoresist blanket layer (not shown) over the blanket layer of the capping dielectric layer 212. The photoresist blanket layer can then be patterned using photolithography techniques to form the patterned photoresist 604. The patterned photoresist 604 can then serve as an etch mask during a subsequent etching process that can be performed to etch the unmasked portions of the capping dielectric layer 212, as described below. Figure 13 Shown in more detail.

[0193] Figure 13 FIG. 1 is a vertical cross-sectional view of a further intermediate structure 1300 that can be used to form a photonic device (e.g., photonic device 300, 400) according to various embodiments. An anisotropic etching process can be performed to remove portions of the capping dielectric layer 212 that are not masked by the patterned photoresist 604 to remove the photoresist 604. Figure 12 The intermediate structure 1200 forms the intermediate structure 1300. Figure 13 As shown, the etching process may produce a stair-step structure in which the capping dielectric layer 212 is divided into a lower portion 212 a having a first surface 1302 a and an upper portion 212 b having a second surface 1302 b .

[0194] Figure 14 is a vertical cross-sectional view of a further intermediate structure 1400 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 13 A blanket layer of silicon (eg, p-type semiconductor 602) is deposited over the intermediate structure 1300 to Figure 13 In this regard, a blanket layer of silicon (eg, p-type semiconductor 602) may be deposited using a CVD process, and an in-situ doping process may be used to introduce p-type dopants, as previously described with reference to FIG. Figure 6As described in more detail in the figure, a blanket layer of silicon (p-type semiconductor 602) can be deposited on both the first surface 1302a and the second surface 1302b. Thus, the blanket layer of silicon (e.g., p-type semiconductor 602) can contact the first folded segment 306a1 of the first terminal 302a to be formed later and can form an integral structure with the first folded segment 306a1. Furthermore, the portions of the encapsulating dielectric layer 212 formed both above and below the first folded segment 306b1 of the second terminal 302b can serve as corresponding portions of the capacitor dielectric layer 304, as shown in the figure.

[0195] Figure 15 is a vertical cross-sectional view of a further intermediate structure 1500 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 14 A patterned photoresist 604 is formed above the intermediate structure 1400 to Figure 14 The intermediate structure 1400 is formed into the intermediate structure 1500. The patterned photoresist 604 can be formed by depositing a photoresist blanket layer (not shown) over the blanket layer of silicon (e.g., p-type semiconductor 602). The photoresist blanket layer can then be patterned using photolithography techniques to form the patterned photoresist 604. The patterned photoresist 604 can then serve as an etch mask during a subsequent etching process that can be performed to etch the blanket layer of silicon (e.g., p-type semiconductor 602).

[0196] Figure 16 FIG. 1 is a vertical cross-sectional view of a further intermediate structure 1600 that can be used to form a photonic device (e.g., photonic devices 300 and 400) according to various embodiments. Figure 15 The portion masked by the patterned photoresist 604 is Figure 15 The intermediate structure 1500 is formed into the intermediate structure 1600. Then, the patterned photoresist 604 can be removed by ashing or dissolving with a solvent. As shown in the figure, the remaining portion of the blanket layer of silicon (e.g., p-type semiconductor 602) formed above the second surface 1302b can form the second folded section 306a2 of the first terminal 302a to be formed later, as described above with reference to Figure 3B and Figure 4B As mentioned above. Further, Figure 16As shown, an anisotropic etching process can be performed to form a first vertical edge portion 1602a of a blanket layer of silicon (p-type semiconductor 602). In this regard, the first vertical edge portion 1602a can connect a subsequently formed thin layer (i.e., second folded segment 306a2) of a first terminal 302a to be formed later to a previously formed thin layer (i.e., first folded segment 306a1).

[0197] Figure 17 FIG. 1 is a vertical cross-sectional view of a further intermediate structure 1700 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 16 A patterned photoresist 604 is formed above the intermediate structure 1600 to Figure 16 The intermediate structure 1600 is formed into an intermediate structure 1700. The patterned photoresist 604 can be used as an etch mask during an etching process that can be performed to etch a portion of the second folded section 306a2 of the first terminal 302a to be formed later.

[0198] Figure 18 FIG. 1 is a vertical cross-sectional view of a further intermediate structure 1800 that can be used to form a photonic device (e.g., photonic device 300, 400) according to various embodiments. The width of the second folded section 306a2 of the first terminal 302a can be reduced by performing an anisotropic etching process to reduce the width of the second folded section 306a2 of the first terminal 302a. Figure 17 The intermediate structure 1700 forms the intermediate structure 1800. Figure 18 As shown, the intermediate structure 1800 includes the aforementioned reference Figure 3A The completed first terminal 302a is shown. In this regard, the first terminal 302a is a connecting structure formed of p-type doped silicon, having a first U-shaped portion 306a. The first U-shaped portion 306a includes a first folded segment 306a1, a second folded segment 306a2, and a first vertical edge portion 1602a connecting the first folded segment 306a1 and the second folded segment 306a2. As described above, the intermediate structure 1800 also includes a first folded segment 306b1, which will later be formed into the second terminal 302b.

[0199] Figure 19 FIG. 1 is a vertical cross-sectional view of a further intermediate structure 1900 that can be used to form a photonic device (e.g., photonic device 300, 400) according to various embodiments. An additional cladding dielectric layer 212 can be formed above the intermediate structure 1800 to Figure 18The intermediate structure 1800 is formed into the intermediate structure 1900. In this regard, a blanket layer of dielectric material (not shown) can be deposited over the intermediate structure 1800 by performing a compliant deposition process such as CVD or a self-planarizing deposition process (e.g., spin coating). Other compliant deposition processes can include PECVD, ALD, PVD, HDPCVD, MOCVD, sputtering, laser ablation, etc. Excess material of the deposited capping dielectric layer 212 can be removed from above the top surface of the intermediate structure 1900 by a planarization process, such as CMP.

[0200] Figure 20 is a vertical cross-sectional view of a further intermediate structure 2000 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 19 A patterned photoresist 604 is formed above the intermediate structure 1900 to Figure 19 The intermediate structure 1900 is formed into the intermediate structure 2000. The patterned photoresist 604 can then be used as an etch mask during a subsequent etching process that can be performed to etch the capping dielectric layer 212.

[0201] Figure 21 FIG2 is a vertical cross-sectional view of a further intermediate structure 2100 that can be used to form a photonic device (e.g., photonic device 300, 400) according to various embodiments. An anisotropic etching process can be performed to remove portions of the capping dielectric layer 212 that are not masked by the patterned photoresist 604 to remove the photoresist 604. Figure 20 The intermediate structure 2000 forms the intermediate structure 2100. Figure 21 As shown, the etching process may produce a stair-step structure in which the capping dielectric layer 212 is divided into a lower portion having a first surface 1302 a and an upper portion having a second surface 1302 b .

[0202] Figure 22 is a vertical cross-sectional view of a further intermediate structure 2200 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 21 A blanket layer of polysilicon (eg, n-type semiconductor 902) is deposited over the intermediate structure 2100 to Figure 21 In this regard, the blanket layer of polysilicon (eg, n-type semiconductor 902) may be deposited using an LPCVD process, in which an in-situ doping process may be used to introduce n-type dopants, as previously described with reference to FIG. Figure 9As described in more detail in the figure, a blanket layer of polysilicon (e.g., n-type semiconductor 902) can be deposited on both the first surface 1302a and the second surface 1302b. In this way, the blanket layer of polysilicon (e.g., n-type semiconductor 902) can contact the first folded segment 306b1 of the second terminal 302b to be formed later and can form an integral structure with the first folded segment 306b1. Furthermore, the portions of the encapsulating dielectric layer 212 formed above and below the second folded segment 306a2 of the first terminal 302a can serve as corresponding portions of the capacitor dielectric layer 304.

[0203] Figure 23 is a vertical cross-sectional view of a further intermediate structure 2300 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 22 A patterned photoresist 604 is formed above the intermediate structure 2200 to Figure 22 The intermediate structure 2200 is formed into the intermediate structure 2300. The patterned photoresist 604 can then be used as an etch mask during a subsequent etching process that can be performed to etch a blanket layer of polysilicon (eg, n-type semiconductor 902).

[0204] Figure 24 2 is a vertical cross-sectional view of a further intermediate structure 2400 that can be used to form a photonic device (e.g., photonic devices 300 and 400) according to various embodiments. Figure 23 The portion masked by the patterned photoresist 604 is Figure 23 The intermediate structure 2300 is formed into the intermediate structure 2400. Then, the patterned photoresist 604 can be removed by ashing or dissolving with a solvent. As shown in the figure, the remaining portion of the blanket layer of polysilicon (e.g., n-type semiconductor 902) formed above the second surface 1302b can form the second folded section 306b2 of the second terminal 302b to be formed later, as described above with reference to Figure 3B and Figure 4B As mentioned above. Further, Figure 24 As shown, an anisotropic etching process can be performed to leave behind a second vertical edge portion 1602b of the blanket layer of polysilicon (e.g., n-type semiconductor 902). In this regard, the second vertical edge portion 1602b can connect a subsequently formed thin layer (i.e., second folded segment 306b2) of the second terminal 302b to a previously formed thin layer (i.e., first folded segment 306b1).

[0205] like Figure 24 As shown, the intermediate structure 2400 includes the aforementioned reference Figure 3AThe completed second terminal 302b is a connection structure formed of n-type polysilicon, and the connection structure has a second U-shaped portion 306b. The second U-shaped portion 306b includes a first folded segment 306b1, a second folded segment 306b2, and a second vertical edge portion 1602b connecting the first folded segment 306b1 and the second folded segment 306b2.

[0206] Figure 25 FIG. 2 is a vertical cross-sectional view of a further intermediate structure 2500 that can be used to form a photonic device (e.g., photonic device 300, 400) according to various embodiments. An additional cladding dielectric layer 212 can be formed above the intermediate structure 2400 to Figure 24 The intermediate structure 2400 is formed into the intermediate structure 2500. In this regard, a blanket layer of dielectric material (not shown) can be deposited over the intermediate structure 2400 by performing a compliant deposition process such as CVD or a self-planarizing deposition process (e.g., spin coating). Other compliant deposition processes can include PECVD, ALD, PVD, HDPCVD, MOCVD, sputtering, laser ablation, etc. Excess material of the deposited capping dielectric layer 212 can be removed from above the top surface of the intermediate structure 2500 by a planarization process, such as CMP.

[0207] Figure 26 is a vertical cross-sectional view of a further intermediate structure 2600 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 25 A patterned photoresist 604 is formed above the intermediate structure 2500 to Figure 25 The intermediate structure 2500 is formed into the intermediate structure 2600. The patterned photoresist 604 can then be used as an etch mask during a subsequent etching process that can be performed to etch the capping dielectric layer 212.

[0208] Figure 27 FIG. 2 is a vertical cross-sectional view of a further intermediate structure 2700 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 26 The intermediate structure 2600 is formed into the intermediate structure 2700. In this regard, the anisotropic etching process can etch the capping dielectric layer 212 to form a via hole 2702. The via hole 2702 can then be filled with p-type silicon to form a contact area for the first terminal, as described below with reference to Figure 28 Described in more detail.

[0209] Figure 28 FIG. 2 is a vertical cross-sectional view of a further intermediate structure 2800 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 27 A blanket layer of silicon (not shown) is deposited over the intermediate structure 2700 to Figure 27 In this regard, the blanket layer of silicon may be deposited using a CVD process, in which an in-situ doping process may be used to introduce p-type dopants, as previously described with reference to Figure 6 A blanket layer of silicon may be deposited to a thickness sufficient to fill the Figure 27 The through-hole 2702 is formed. Then, the excess material of the silicon blanket layer can be removed by performing a planarization process such as CMP. In this way, a p-type doped silicon contact region 2802 can be formed to serve as a connection structure with the first terminal 302a.

[0210] Figure 29 is a vertical cross-sectional view of a further intermediate structure 2900 that can be used to form a photonic element (eg, photonic element 300, 400) according to various embodiments. Figure 3A and Figure 4A The first heavily doped semiconductor region 314a and the second heavily doped semiconductor region 314b are formed to Figure 28 The intermediate structure 2800 is formed into an intermediate structure 2900. As described above, the dopants in the first heavily doped semiconductor region 314a and the second heavily doped semiconductor region 314b can increase the p-type and n-type carrier concentrations, which can allow ohmic contacts with the subsequently formed first electrode 312a and the second electrode 312b.

[0211] Figures 30 to 32 3000, 3100, 3200 are vertical cross-sectional views of further intermediate structures (intermediate structures 3000, 3100, 3200) that can be used to form photonic devices (e.g., photonic devices 300, 400) according to various embodiments. The additional capping dielectric layer 212 can be deposited and then a patterned photoresist 604 can be formed over the resulting structure according to the methods described in detail above. Figure 29 The intermediate structure 2900 is formed into an intermediate structure 3000. As shown, the patterned photoresist 604 may include an opening 3002, which may allow the capping dielectric layer 212 to be etched to form the intermediate structure 3000. Figure 31 The through hole 3102 is shown. The through hole 3102 can then be filled with a conductive material 3202 (e.g., see Figure 32 ), thereby forming a first electrode 312a and a second electrode 312b.

[0212] Conductive material 3202 may include a metal liner material and a metal filler material. The metal liner material may include a conductive metal nitride or a conductive metal carbide, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable conductive materials within the contemplation of the present disclosure may also be used.

[0213] Before introducing the conductive material 3202, a self-aligned silicide (i.e., salicide) 3204 may be formed over the first terminal 302a and the second terminal 302b. The salicide 3204 may be formed by introducing metal ions (e.g., Ni, Ti, Co, Hf, Mn, Pd, Pt, Ta, W, Zr) into the via hole 3102. The metal ions may be introduced using evaporation, sputtering, or a CVD process, allowing the metal ions to interact with the silicon of the first terminal 302a and the polysilicon of the second terminal 302b. After the metal ions are introduced, a rapid thermal anneal (RTA) process may be performed on the intermediate structure 3100 to form the salicide 3204. The self-aligned silicide 3204 may include various silicon / metal compounds, such as CoSi2, HfSi2, MoSi2, NiSi2, Pd2Si, PtSi, TaSi2, TiSi2, WSi2, ZrSi2, etc.

[0214] like Figure 32 As shown, the conductive material 3202 may be deposited so as to form direct contact between the conductive material 3202 and the self-aligned silicide 3204. In this way, a good electrical connection (i.e., ohmic contact) may be formed between the conductive material 3202 and the first terminal 302a and the second terminal 302b. Subsequently, the excess conductive material 3202 above the top surface of the capping dielectric layer 212 may be removed to form a Figure 3A and Figure 3B The photonic element 300 can be obtained by performing the same Figures 5 to 32 Similar processes to those described above are used to form Figure 4A and Figure 4B The photonic element 400. As hereinafter referred to Figure 33 Summarized.

[0215] Figure 33306a1, 306b1 and second folded segments 306a2, 306b2) of a first conductivity type semiconductor (e.g., p-type semiconductor 602) and a second conductivity type semiconductor (e.g., n-type semiconductor 902) over a substrate 301, and a capacitor dielectric layer 304 separating adjacent alternating layers (e.g., first folded segments 306a1, 306b1 and second folded segments 306a2, 306b2). In operation 3304, method 3300 may include, after completing the deposition process of each alternating layer (e.g., the first folding segment 306a1, 306b1 and the second folding segment 306a2, 306b2), continuing to perform an etching operation to reduce the width of each alternating layer (e.g., the first folding segment 306a1, 306b1 and the second folding segment 306a2, 306b2). In operation 3306, method 3300 may include, for each subsequent layer (e.g., second folded segment 306a2, 306b2) of semiconductor material of a given conductivity form (e.g., p-type semiconductor 602, n-type semiconductor 902), forming a vertical edge portion (e.g., first vertical edge portion 1602a, second vertical edge portion 1602b) of semiconductor material of a given conductivity form (e.g., p-type semiconductor 602, n-type semiconductor 902), the vertical edge portion connecting the subsequent layer (e.g., second folded segment 306a2, 306b2) of semiconductor material of a given conductivity form (e.g., p-type semiconductor 602, n-type semiconductor 902) to the previously deposited thin layer (e.g., first folded segment 306a1, 306b1).

[0216] In this regard, a plurality of connected first conductivity type semiconductor (e.g., p-type semiconductor 602) layers (e.g., first folded segment 306a1, second folded segment 306a2) form a first terminal 302a, the first terminal 302a having a first overlapping portion (e.g., first U-shaped portion 306a) in a first cross-sectional plane (e.g., xz plane) perpendicular to the first direction (e.g., y-axis), and a plurality of connected second conductivity type semiconductor (e.g., n-type semiconductor 902) layers (e.g., first folded segment 306b1, second folded segment 306b2) form a second terminal 302b, the second terminal 302b having a second overlapping portion (e.g., second U-shaped portion 306b) in the first cross-sectional plane (e.g., xz plane). Further, method 3300 may also include forming the first overlapping portion (e.g., first U-shaped portion 306a) and the second overlapping portion (e.g., second U-shaped portion 306b) to be arranged in an interlocking configuration (e.g., see Figure 3A and Figure 4A), the interlocking configuration includes an overlapping region 308, such that in the overlapping region 308, the first terminal 302a and the second terminal 302b further overlap in a second cross-sectional plane (ie, yz plane) perpendicular to the first cross-sectional plane (ie, xz plane).

[0217] During the deposition of alternating layers (e.g., first folded segments 306a1, 306b1 and second folded segments 306a2, 306b2) of the first conductivity type semiconductor (e.g., p-type semiconductor 602) and the second conductivity type semiconductor (e.g., n-type semiconductor 902) according to operations 3302 and 3304 and the subsequent etching operations, method 3300 may further include forming a first terminal 302a and a second terminal 302b such that the first overlapping portion (e.g., the first U-shaped portion 306a) and the second overlapping portion Each of the first U-shaped segments (e.g., the second U-shaped segment 306b) is folded an integer number (m) of times, so that the overlapping region 308 may include an alternating stack of m+1 first folded segments (e.g., the first folded segment 306a1, the second folded segment 306a2, and the third folded segment 306a3) of the first terminal 302a and m+1 second folded segments (e.g., the first folded segment 306b1, the second folded segment 306b2, and the third folded segment 306b3) of the second terminal 302b, where m is greater than or equal to 1 (e.g., for an embodiment where m=1, see Figure 3A and Figure 3B , for m = 2, see Figure 4A and Figure 4B The method 3300 may further include configuring the overlapping region 308 as an optical transmission line 309 , wherein the first direction (ie, the y-axis) is a light propagation direction in the optical transmission line 309 .

[0218] In the deposition of alternating layers (e.g., first folded segments 306a1, 306b1 and second folded segments 306a2, 306b2) of a first conductivity type semiconductor (e.g., p-type semiconductor 602) and a second conductivity type semiconductor (e.g., n-type semiconductor 902) according to operation 3302, method 3300 may further include performing the deposition process of each alternating layer (e.g., first folded segments 306a1, 306b1 and second folded segments 306a2, 306b2) as an in-situ doping process, so that the deposition of the first conductivity type semiconductor (e.g., p-type semiconductor 602) may further include deposition of a first conductivity type dopant, and the deposition of the second conductivity type semiconductor (e.g., n-type semiconductor 902) may further include deposition of a second conductivity type dopant. Furthermore, in the deposition of alternating layers (e.g., first folded segments 306a1, 306b1 and second folded segments 306a2, 306b2) of a first conductivity type semiconductor (e.g., p-type semiconductor 602) and a second conductivity type semiconductor (e.g., n-type semiconductor 902) according to operation 3302, method 3300 may further include depositing the first conductivity type semiconductor (e.g., p-type semiconductor 602) as p-type silicon, and depositing the second conductivity type semiconductor (e.g., n-type semiconductor 902) as n-type polysilicon.

[0219] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a photonic element (e.g., photonic element 300, 400) is provided herein. The photonic element (e.g., photonic element 300, 400) may include a first terminal (e.g., first terminal 302a) comprising silicon and a second terminal (e.g., second terminal 302b) comprising polysilicon. The first terminal (e.g., first terminal 302a) may be configured as a first three-dimensional structure, extending along a first direction (i.e., the y-axis) and having a first U-shaped portion (e.g., first U-shaped portion 306a) in a first cross-sectional plane (i.e., the xz plane) perpendicular to the first direction (i.e., the y-axis). Similarly, the second terminal (e.g., second terminal 302b) may be configured as a second three-dimensional structure, extending along the first direction (i.e., the y-axis) and having a second U-shaped portion (e.g., second U-shaped portion 306b) in a first cross-sectional plane (i.e., the xz plane). The photonic element (e.g., photonic element 300, 400) may further include a capacitor dielectric layer (e.g., capacitor dielectric layer 304) disposed between a first terminal (e.g., first terminal 302a) and a second terminal (e.g., second terminal 302b), and a cladding dielectric layer (e.g., cladding dielectric layer 212) surrounding the first terminal (e.g., first terminal 302a) and the second terminal (e.g., second terminal 302b).

[0220] The first U-shaped portion (eg, first U-shaped portion 306a) and the second U-shaped portion (eg, second U-shaped portion 306b) are arranged in an interlocking configuration (eg, see Figure 3A and Figure 4A ), the interlocking configuration includes an overlapping region (e.g., overlapping region 308), such that in the overlapping region (e.g., overlapping region 308), the first terminal (e.g., first terminal 302a) and the second terminal (e.g., second terminal 302b) further overlap in a second cross-sectional plane (i.e., yz plane) perpendicular to the first cross-sectional plane (i.e., xz plane). Furthermore, the overlapping region (e.g., overlapping region 308) is configured as an optical transmission line (e.g., optical transmission line 309), in which the first direction (i.e., y-axis) is the direction of light propagation.

[0221] According to various embodiments, the optical transmission line (e.g., optical transmission line 309) may include a first effective refractive index (n1) in response to a first potential difference applied between a first terminal (e.g., first terminal 302a) and a second terminal (e.g., second terminal 302b), and may include a second effective refractive index (n2) in response to a second potential difference applied between the first terminal (e.g., first terminal 302a) and the second terminal (e.g., second terminal 302b).

[0222] In various embodiments, the silicon of the first terminal (eg, first terminal 302 a ) may further include p-type doping, and the polysilicon of the second terminal (eg, second terminal 302 b ) may further include n-type doping.

[0223] According to some embodiments, each of the first terminal (e.g., first terminal 302a), the second terminal (e.g., second terminal 302b), and the capacitor dielectric layer (e.g., capacitor dielectric layer 304) may have a length (e.g., length 316) along the direction of light propagation, and the length (e.g., length 316) is in the range of about 150 microns to about 300 microns.

[0224] In some embodiments, the optical transmission line (e.g., optical transmission line 309) may have a width (e.g., width 318) located in a first cross-sectional plane (i.e., the xz plane), the width (e.g., width 318) being between approximately 400 nanometers and 500 nanometers, and the optical transmission line (e.g., optical transmission line 309) may have a thickness (e.g., thickness 320) located in the first cross-sectional plane (i.e., the xz plane), the thickness (e.g., thickness 320) being between approximately 150 nanometers and 250 nanometers.

[0225] In various embodiments, each of the first terminal (e.g., the first terminal 302a) and the second terminal (e.g., the second terminal 302b) may include multiple connecting layers (e.g., the first folding segment 306a1, the second folding segment 306a2, the third folding segment 306a3, the first folding segment 306b1, the second folding segment 306b2, the third folding segment 306b3), and the connecting layers have a thickness between 50 nanometers and 80 nanometers (e.g., 322a, 322b).

[0226] In some embodiments, an optical transmission line (e.g., optical transmission line 309) can be configured to support an optical mode having an electric field distribution (e.g., electric field distribution 310) in a first cross-sectional plane (e.g., xz plane) that spatially overlaps with a first terminal (e.g., first terminal 302a) and a second terminal (e.g., second terminal 302b).

[0227] In some embodiments, a photonic element (e.g., photonic elements 300, 400) may have a voltage times length product Vπ·Lπ, where the voltage times length product Vπ·Lπ describes a characteristic of a 180° phase shift of an optical mode propagating in an optical transmission line (e.g., optical transmission line 309), wherein the voltage times length product Vπ·Lπ is less than 0.1 V-cm.

[0228] In various embodiments, an optical transmission line (eg, optical transmission line 309 ) may have an optical insertion loss less than 0.5 dB relative to a silicon waveguide structure (eg, silicon waveguide 200 c ).

[0229] In some embodiments, the capacitor dielectric layer (eg, capacitor dielectric layer 304 ) comprises a thickness (eg, thickness 324 ) in a range of approximately 2 nm to 7 nm.

[0230] Further, in some embodiments, the first terminal (e.g., first terminal 302a), the second terminal (e.g., second terminal 302b), and the capacitor dielectric layer (e.g., capacitor dielectric layer 304) may be configured as a semiconductor-insulator-semiconductor capacitor, wherein in response to a potential difference between 0 volts and 6 volts applied between the first terminal (e.g., first terminal 302a) and the second terminal (e.g., second terminal 302b), the semiconductor-insulator-semiconductor capacitor comprises a capacitance per unit length in the direction of light propagation (i.e., the y-axis), the capacitance per unit length being in a range from about 1 femtofarad / micrometer to about 20 femtofarads / micrometer.

[0231] In further embodiments, a photonic element (e.g., photonic elements 300 and 400) may include a first terminal (e.g., first terminal 302a) comprising a p-type semiconductor and a second terminal (e.g., second terminal 302b) comprising an n-type semiconductor. The first terminal (e.g., first terminal 302a) may be configured as a first three-dimensional structure, extending along a first direction (i.e., the y-axis) and having a first overlapping portion in a first cross-sectional plane (i.e., the xz plane) perpendicular to the first direction (i.e., the y-axis). Similarly, the second terminal (e.g., second terminal 302b) may be configured as a second three-dimensional structure, extending along the first direction (i.e., the y-axis) and having a second overlapping portion in a first cross-sectional plane (i.e., the xz plane) perpendicular to the first direction (i.e., the y-axis). The photonic device (e.g., photonic device 300, 400) may further include a capacitor dielectric layer (e.g., capacitor dielectric layer 304) disposed between a first terminal (e.g., first terminal 302a) and a second terminal (e.g., second terminal 302b), and a cladding dielectric layer (e.g., cladding dielectric layer 212) surrounding the first terminal (e.g., first terminal 302a) and the second terminal (e.g., second terminal 302b). The first overlapping portion (e.g., first U-shaped portion 306a) and the second overlapping portion (e.g., second U-shaped portion 306b) are arranged in an interlocking configuration (e.g., see FIG. 1 ). Figure 3A and Figure 4A ), the interlocking configuration includes an overlapping area (e.g., overlapping area 308), so that in the overlapping area (e.g., overlapping area 308), the first terminal (e.g., first terminal 302a) and the second terminal (e.g., second terminal 302b) further overlap in a second cross-sectional plane (i.e., yz plane) perpendicular to the first cross-sectional plane (i.e., xz plane).

[0232] According to various embodiments, each of the first overlapping portion (e.g., the first U-shaped portion 306a) and the second overlapping portion (e.g., the second U-shaped portion 306b) may be folded an integer number (m) of times, such that the overlapping region (e.g., the overlapping region 308) may include an alternating stack of m+1 first folded segments (e.g., the first folded segment 306a1, the second folded segment 306a2, and the third folded segment 306a3) of the first terminal (e.g., the first terminal 302a) and m+1 second folded segments (e.g., the first folded segment 306b1, the second folded segment 306b2, and the third folded segment 306b3) of the second terminal (e.g., the second terminal 302b), where m is greater than or equal to 1 (e.g., in Figure 3A and Figure 3B In m=1, and Figure 4A and Figure 4BThe overlapping region (eg, overlapping region 308 ) can be further configured as an optical transmission line (eg, optical transmission line 309 ), in which the first direction (ie, the y-axis) is the light propagation direction.

[0233] In various embodiments, an optical transmission line (e.g., optical transmission line 309) may support an optical mode having an electric field distribution (e.g., electric field distribution 310) in a first cross-sectional plane (i.e., xz plane) that spatially overlaps with each of the m+1 first folded segments (e.g., first folded segment 306a1, second folded segment 306a2, third folded segment 306a3) of a first terminal (e.g., first terminal 302a) and each of the m+1 second folded segments (e.g., first folded segment 306b1, second folded segment 306b2, third folded segment 306b3) of a second terminal (e.g., second terminal 302b).

[0234] In some embodiments, the integer m is greater than or equal to 2.

[0235] In some embodiments, the first terminal (eg, first terminal 302 a ) may further include p-type silicon, and the second terminal (eg, second terminal 302 b ) may further include n-type polysilicon.

[0236] Further, in some embodiments, the photonic element (e.g., photonic element 300, 400) may have a voltage times length product Vπ·Lπ (characterized by a 180° phase shift of an optical mode propagating in an optical transmission line (e.g., optical transmission line 309)), wherein the voltage times length product Vπ·Lπ is less than 0.1 V-cm; and have an optical insertion loss less than 0.5 dB relative to a silicon waveguide structure.

[0237] In a further embodiment, a method for forming a photonic element is provided herein. The method includes depositing a plurality of alternating layers of a first conductivity type semiconductor and a second conductivity type semiconductor over a substrate, and a plurality of capacitor dielectric layers separating adjacent alternating layers; after completing the deposition process for each of the plurality of alternating layers, sequentially performing an etching operation to reduce the width of each of the plurality of alternating layers; and, for each subsequent layer of a given conductivity type semiconductor, forming a vertical edge portion of the given conductivity type semiconductor, the vertical edge portion connecting the subsequent layer to the previously deposited layer of the given conductivity type semiconductor. The plurality of connected first conductivity type semiconductor layers form a first terminal, the first terminal having a first overlapping portion in a first cross-sectional plane perpendicular to a first direction. The plurality of connected second conductivity type semiconductor layers form a second terminal, the second terminal having a second overlapping portion in the first cross-sectional plane. The first overlapping portion and the second overlapping portion are arranged in an interlocking configuration, the interlocking configuration including an overlapping region such that, in the overlapping region, the first terminal and the second terminal further overlap in a second cross-sectional plane perpendicular to the first cross-sectional plane.

[0238] In some embodiments, the deposition of the above-mentioned alternating layers of the first conductivity form semiconductor and the above-mentioned second conductivity form semiconductor and the continued execution of the above-mentioned etching operation also include: forming a first terminal and a second terminal, so that each of the first overlapping part and the second overlapping part is folded an integer (m) times, so that the overlapping area includes an alternating stack of m+1 first folded segments of the first terminal and m+1 second folded segments of the second terminal, where m is greater than or equal to 1, and configuring the overlapping area as an optical transmission line, in which the first direction is the direction of light propagation.

[0239] In some embodiments, the deposition of multiple alternating layers of first conductivity form semiconductor and second conductivity form semiconductor also includes: performing the deposition process for each of the multiple alternating layers as an in-situ doping process, so that the deposition of the first conductivity form semiconductor also includes the deposition of multiple first conductivity form dopants, and the deposition of the second conductivity form semiconductor also includes the deposition of multiple second conductivity form dopants.

[0240] In some embodiments, depositing the plurality of alternating layers of the first conductivity type semiconductor and the second conductivity type semiconductor further comprises depositing the first conductivity type semiconductor as p-type silicon and depositing the second conductivity type semiconductor as n-type polysilicon.

[0241] The embodiments disclosed herein offer advantages over existing modulators by generating a larger optical phase shift for a given applied voltage and by having reduced optical insertion loss relative to existing modulators. In this regard, the optical modulator of the embodiments includes a first terminal 302a and a second terminal 302b having an interlocking structure. The interlocking structure comprises a stacked structure comprising alternating connected layers of the first terminal 302a and the second terminal 302b (e.g., first folded segments 306a1, 306b1 and second folded segments 306a2, 306b2). The stacked structure effectively improves modulation efficiency due to increased overlap of the electric field distribution 310 of the optical mode with the charge carriers of the first terminal 302a and the second terminal 302b, resulting in sub-1 volt phase modulation and less than 0.5 dB insertion loss relative to a silicon waveguide structure.

[0242] The foregoing text summarizes the features of various embodiments so that those skilled in the art can better understand how the present disclosure may be implemented. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the present disclosure to accomplish the same objectives and / or achieve the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A photonic element, characterized in that: include: a first terminal comprising silicon, wherein the first terminal is a first three-dimensional structure extending along a first direction and having a first U-shaped portion in a first cross-sectional plane perpendicular to the first direction; a second terminal comprising polysilicon, wherein the second terminal is a second three-dimensional structure extending along the first direction and having a second U-shaped portion in the first cross-sectional plane; a capacitor dielectric layer disposed between the first terminal and the second terminal; and a dielectric layer surrounding the first terminal and the second terminal; wherein the first U-shaped portion and the second U-shaped portion are arranged in an interlocking configuration, the interlocking configuration including an overlapping region, such that in the overlapping region, the first terminal and the second terminal further overlap in a second cross-sectional plane perpendicular to the first cross-sectional plane, and The overlapping region is configured as an optical transmission line, and in the optical transmission line, the first direction is a light propagation direction.

2. The photonic element according to claim 1, wherein: The silicon of the first terminal further includes a p-type dopant; and The polysilicon of the second terminal further includes an n-type doping.

3. The photonic element according to claim 1, wherein Each of the first terminal, the second terminal, and the capacitor dielectric layer includes a length along the light propagation direction, and the length is in a range of 150 micrometers to 300 micrometers.

4. The photonic element according to claim 1, wherein: The optical transmission line includes a width in the first cross-sectional plane, the width being between 400 nanometers and 500 nanometers; and The optical transmission line includes a thickness located in the first cross-sectional plane, and the thickness is between 150 nanometers and 250 nanometers.

5. The photonic element according to claim 1, wherein Each of the first terminal and the second terminal includes a plurality of connection layers, and each of the connection layers includes a thickness between 50 nanometers and 80 nanometers.

6. The photonic element according to claim 1, wherein The capacitor dielectric layer includes a thickness in a range of 2 nm to 7 nm.

7. The photonic element according to claim 1, wherein The first terminal, the second terminal, and the capacitor dielectric layer are configured as a semiconductor-insulator-semiconductor capacitor, and in response to a potential difference between 0 volts and 6 volts applied between the first terminal and the second terminal, the capacitance per unit length of the semiconductor-insulator-semiconductor capacitor in the direction of light propagation is in the range of 1 femtofarad / micrometer to 20 femtofarads / micrometer.

8. A photonic element, characterized in that: include: a first terminal comprising a p-type semiconductor, wherein the first terminal is a first three-dimensional structure extending along a first direction and having a first overlapping portion in a first cross-sectional plane perpendicular to the first direction; a second terminal comprising an n-type semiconductor, wherein the second terminal is a second three-dimensional structure extending along the first direction and having a second overlapping portion in the first cross-sectional plane perpendicular to the first direction; a capacitor dielectric layer disposed between the first terminal and the second terminal; as well as a dielectric layer surrounding the first terminal and the second terminal; wherein the first overlapping portion and the second overlapping portion are arranged in an interlocking configuration, the interlocking configuration including an overlapping region such that in the overlapping region, the first terminal and the second terminal further overlap in a second cross-sectional plane perpendicular to the first cross-sectional plane; wherein each of the first overlapping portion and the second overlapping portion is folded an integer number m times so that the overlapping region comprises an alternating stack of m+1 first folded segments of the first terminal and m+1 second folded segments of the second terminal, where m is greater than or equal to 1, and The overlapping region is configured as an optical transmission line, and in the optical transmission line, the first direction is a light propagation direction.

9. The photonic element according to claim 8, wherein m is greater than or equal to 2.

10. The photonic element according to claim 8, wherein: The first terminal further comprises p-type silicon; and The second terminal further comprises n-type polysilicon.

Images