Device structure and assembly

Abstract

A device structure includes an interposer including a metal wiring structure embedded in an interlayer dielectric layer and an optical waveguide, where the interposer includes a stepped outer sidewall, and the interposer includes a metal wiring structure embedded in the interlayer dielectric layer and an optical waveguide embedded in the metal wiring structure. The stepped outer side wall comprises an outermost vertical surface section, a transverse concave side wall section which is transversely concave relative to the outermost vertical surface section, and a connecting horizontal surface section which is connected with the outermost vertical surface section and the transverse concave side wall section; and a fiber access unit having a first end optically coupled to a subset of the optical waveguides through at least one optical cement portion disposed between the fiber access unit and the laterally recessed sidewall section of the stepped outer sidewall.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to device structures and components. Background Art

[0002] Optical devices can be integrated with silicon packages in silicon photonics technology. The performance of integrated optical devices can be enhanced by providing low optical loss and high optical bandwidth. Utility Model Content

[0003] The purpose of the present invention is to provide a device structure and assembly to solve at least one of the above problems.

[0004] In some embodiments, a device structure is provided, which includes an interposer, a metal wiring structure and an optical waveguide buried in an interlayer dielectric layer, wherein the interposer further includes a stepped outer sidewall, the stepped outer sidewall including an outermost vertical surface segment, a laterally recessed sidewall segment that is laterally recessed relative to the outermost vertical surface segment, and a connecting horizontal surface segment connecting the outermost vertical surface segment and the laterally recessed sidewall segment; and an optical fiber access unit having a first end, the first end being optically coupled to a subset of the optical waveguides via at least one optical adhesive portion disposed between the optical fiber access unit and the laterally recessed sidewall segment of the stepped outer sidewall.

[0005] According to one embodiment of the present invention, the invention further includes at least one semiconductor die attached to the metal wiring structure of the interposer.

[0006] According to one embodiment of the present invention, the device further includes a molding compound die frame laterally surrounding the at least one semiconductor die, wherein the outermost vertical surface segment is located in the same vertical plane as a sidewall of the molding compound die frame.

[0007] According to one embodiment of the present invention, the at least one optical adhesive portion contacts a horizontal bottom surface section of the molding compound die frame and a bottom portion of the sidewall of the molding compound die frame.

[0008] According to one embodiment of the present invention, one of the at least one semiconductor die includes an additional optical waveguide coupled to a subset of the optical waveguides in the interposer via evanescent coupling.

[0009] According to one embodiment of the present invention, the lateral recess sidewall section vertically extends from the topmost surface of the interlayer dielectric layer to at least the bottommost surface of the interlayer dielectric layer.

[0010] According to one embodiment of the present invention, the at least one optical adhesive portion includes: a first optical adhesive portion, contacting the laterally recessed side wall segment and having an outer side wall in a vertical plane of the outermost vertical surface segment including the stepped outer side wall; and a second optical adhesive portion, contacting the first end of the optical fiber access unit and having an inner side wall contacting the outer side wall of the first optical adhesive portion.

[0011] According to one embodiment of the present invention, the at least one optical adhesive portion includes a single optical adhesive portion having a homogeneous material composition and contacting the transverse recessed sidewall section and the first end of the optical fiber access unit.

[0012] In some embodiments, a component is provided, comprising a composite semiconductor package including an interposer and at least one semiconductor die attached to the interposer, wherein the interposer includes a metal wiring structure and an optical waveguide embedded in a dielectric layer, the interposer further including a stepped outer sidewall, the stepped outer sidewall including a first outermost vertical surface segment and a laterally recessed sidewall segment that is laterally recessed relative to the first outermost vertical surface segment; a molding compound; and a fiber access unit having a first end, the first end being optically coupled to a subset of the optical waveguides via at least one optical adhesive portion disposed between the fiber access unit and the laterally recessed sidewall segment of the stepped outer sidewall, wherein a sidewall of the at least one optical adhesive portion is aligned with a sidewall of the molding compound.

[0013] According to one embodiment of the present invention, the stepped outer side wall includes: a first connecting horizontal surface section, connecting the edge of the first outermost vertical surface section to the edge of the transverse recessed side wall section; and a second outermost vertical surface section, connected to the transverse recessed side wall section via a second connecting horizontal surface section. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following detailed description, taken in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It should be noted that, in accordance with standard industry practice, the various features shown in the figures are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration.

[0015] Figure 1 FIG1 is a vertical cross-sectional view of an intermediate structure including a silicon substrate and a through-substrate hole structure in the silicon substrate according to an embodiment of the present invention.

[0016] Figure 2 FIG. 1 is a vertical cross-sectional view of an intermediate structure after forming an interlayer dielectric layer and a metal wiring structure according to an embodiment of the present invention.

[0017] Figure 3FIG. 1 is a schematic vertical cross-sectional view of an intermediate structure after forming an optical converter, a waveguide, an additional metal wiring structure, an interposer-side bonding pad, and an additional interlayer dielectric layer according to an embodiment of the present invention.

[0018] Figure 4 FIG1 is a vertical cross-sectional view of an intermediate structure after forming channel grooves according to an embodiment of the present invention.

[0019] Figure 5 FIG. 1 is a schematic vertical cross-sectional view of an intermediate structure after a semiconductor die is attached to an interconnect interposer according to an embodiment of the present invention.

[0020] Figure 6 FIG1 is a vertical cross-sectional view of an intermediate structure after forming an optical adhesive trench filling structure according to an embodiment of the present invention.

[0021] Figure 7 FIG. 1 is a schematic vertical cross-sectional view of an intermediate structure after forming a molding compound matrix according to an embodiment of the present invention.

[0022] Figure 8 FIG1 is a vertical cross-sectional view of an intermediate structure after the back side of the silicon substrate is thinned according to an embodiment of the present invention.

[0023] Figure 9 FIG. 1 is a vertical cross-sectional view of the intermediate structure after forming an array of interposer-side bonding pads and solder material portions according to the first embodiment of the present invention.

[0024] Figure 10 FIG1 is a vertical cross-sectional view of an intermediate structure after a reconstructed wafer is cut into composite semiconductor packages according to an embodiment of the present invention.

[0025] Figure 11 The diagram is a vertical cross-sectional view of an intermediate structure after a composite semiconductor package is attached to a package substrate and after the package substrate is attached to a printed circuit board according to an embodiment of the present invention.

[0026] Figure 12 FIG1 is a vertical cross-sectional view of an intermediate structure after the optical fiber access unit is attached to the composite semiconductor package according to an embodiment of the present invention.

[0027] Figure 13 FIG1 is a vertical cross-sectional view of a first alternative embodiment of an exemplary structure after a fiber access unit is attached to a composite semiconductor package according to an embodiment of the present invention.

[0028] Figure 14FIG. 1 is a vertical cross-sectional view of a second alternative embodiment of an exemplary structure after a fiber access unit is attached to a composite semiconductor package according to an embodiment of the present invention.

[0029] Figure 15 FIG1 is a vertical cross-sectional view of a third alternative embodiment of an exemplary structure after a fiber access unit is attached to a composite semiconductor package according to an embodiment of the present invention.

[0030] Figure 16 A flow chart showing steps for forming a device structure according to one embodiment of the present invention is shown.

[0031] The reference numerals are as follows:

[0032] 60: Stepped outer wall

[0033] 61: First outermost vertical surface segment

[0034] 62: Second outermost vertical surface segment

[0035] 63: Laterally recessed sidewall section

[0036] 64: First connecting horizontal surface section

[0037] 65: Second connecting horizontal surface section

[0038] 100: Printed Circuit Board

[0039] 110: Printed circuit board substrate

[0040] 180: Printed circuit board bonding pad

[0041] 190: Welding joint

[0042] 200: packaging substrate

[0043] 210: Core base

[0044] 214: Through the core guide hole structure

[0045] 240: Board side surface layer circuit

[0046] 242: Board side insulation layer

[0047] 244: Board side wiring interconnection

[0048] 248: Board side bonding pad

[0049] 260: Chip side surface layer circuit

[0050] 262: Chip side insulation layer

[0051] 264: Chip side wiring interconnection

[0052] 268: substrate bonding pad

[0053] 292: Board-substrate bottom filling material part

[0054] 400:Silicon interposer

[0055] 409:Silicon substrate

[0056] 412: Dielectric spacer

[0057] 420:Through silicon structure

[0058] 430: Backside dielectric layer

[0059] 488:Interposer side bonding pad

[0060] 490: Welding materials

[0061] 492: Intermediary layer-package bottom filling material part

[0062] 500: Interconnection structure

[0063] 500': Interconnection structure in process

[0064] 560: interlayer dielectric layer

[0065] 570: Optical converter

[0066] 571: channel groove

[0067] 572,772: Optical waveguide

[0068] 580:Metal wiring structure

[0069] 588:Metal bonding structure

[0070] 700:Semiconductor grains

[0071] 701:Logic chip

[0072] 702: Optical device chip

[0073] 730:Molding compound die frame

[0074] 730M: Molding compound matrix

[0075] 788: Wafer bonding structure

[0076] 800:Compound semiconductor package

[0077] 901: Optical adhesive groove filling structure

[0078] 902: first optical adhesive portion

[0079] 904: Second optical adhesive part

[0080] 910: Fiber access unit

[0081] 920: Optical cable

[0082] 930: Module transceiver

[0083] 931: Adhesive layer

[0084] 1610,1620: Steps

[0085] VP: Vertical Plane

[0086] UA:Unit area DETAILED DESCRIPTION

[0087] It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the provided subject matter. Specific examples of the various components and their arrangement are described below in order to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the size of an element is not limited to the range or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the element. In addition, in the subsequent description, forming a first component above or on a second component includes embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components can be formed between the first and second components so that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity and are not intended to limit the relationship between the various embodiments and / or the described appearance structures.

[0088] Furthermore, to facilitate description of the relationship of one element or component to another (plural) element or (plural) component in the drawings, spatially relative terms such as "under...", "below," "lower," "above...", "upper," and similar terms may be used. In addition to the orientations shown in the drawings, spatially relative terms also encompass different orientations of the device during use or operation. The device may also be positioned otherwise (e.g., rotated 90 degrees or in other orientations), and the description of the spatially relative terms used should be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference symbol is assumed to have the same material composition and a thickness within the same thickness range.

[0089] Various embodiments described herein relate to a device structure comprising an optical waveguide in an interposer and a fiber access unit having a first end optically coupled to the optical waveguide via at least one optical adhesive portion. A sidewall of the interposer proximate the end of the optical waveguide can be formed into a smooth surface by performing an anisotropic etching process. During singulation of the interposer from a reconstructed wafer containing an array of interposers, an optical adhesive or sacrificial material can be applied to the surface formed by the anisotropic etching process. The remaining portion of the optical adhesive can serve as part of the optical path between the fiber access unit and the optical waveguide, or can be replaced by another optical adhesive portion.

[0090] Please refer to Figure 1 , Figure 1 A region of an intermediate structure according to one embodiment of the present invention is shown, comprising a silicon substrate 409 and a through-substrate via (TSV) structure formed in the silicon substrate 409. The silicon substrate 409 may comprise a commercially available silicon wafer. An array of TSVs may be formed in the upper portion of the silicon substrate 409 (e.g., by a photolithographic etching process) and may be filled with a dielectric liner layer and at least one conductive filler material (e.g., at least one metal material). The remaining portion of the dielectric liner layer comprises dielectric spacers 412. The remaining portion of the at least one conductive filler material comprises TSV structures 420. In one embodiment, a two-dimensional periodic array of unit areas UA may be provided in the silicon substrate 409. Each unit area UA may comprise an array of TSV structures 420. The height of the TSV structures 420 may range from 2 μm to 30 μm, for example, from 6 μm to 15 μm, although smaller and larger heights may also be used.

[0091] Please refer to Figure 2In the process, an interconnect structure 500' may be formed in each unit area UA. A two-dimensional periodic array of interconnect structures 500' may be formed on a silicon substrate 409. Each interconnect structure 500' may include an interlayer dielectric (ILD) layer 560 and a metal wiring structure 580. The interlayer dielectric layer 560 may include a corresponding dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, organic silicate glass, and / or a dielectric metal oxide. The interlayer dielectric layer 560 may include an inorganic dielectric material, may be mainly composed of an inorganic dielectric material, and / or may be essentially composed of an inorganic dielectric material. Each interlayer dielectric layer 560 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, etc. The thickness of each interlayer dielectric layer 560 may be from 100 nm to 1000 nm, for example, from 200 nm to 600 nm, although smaller and larger thicknesses may also be used. Each interlayer dielectric layer 560 may be patterned, for example, by applying and patterning a corresponding photoresist layer thereon and transferring the pattern in the photoresist layer to the interlayer dielectric layer 560 using an etching process (e.g., an anisotropic etching process). Thereafter, the photoresist layer may be removed, for example, by ashing.

[0092] The metal wiring structure 580 can be formed by depositing a metal layer and patterning the metal layer by a combination of photolithography and etching. Additionally or alternatively, the metal wiring structure 580 can be formed using a damascene process, wherein recesses (e.g., line cavities, via cavities, and / or integrated line and via cavities) are formed in the interlayer dielectric layer 560, which is then filled with at least one metal material, and then the at least one metal material is planarized, for example, by a chemical mechanical polishing process. The total number of wiring layers in the interconnect structure 500' (i.e., the number of layers of the metal wiring structure 580) in each process can be in the range of 1 to 10. In some embodiments, the interconnect structure 500' can be formed in a back-end-of-the-line (BEOL) process.

[0093] Please refer to Figure 3 , the additional interlayer dielectric layer 560, the optical waveguide 572, the optical converter 570, the additional metal wiring structure 580, and the metal bonding structure 588 can be formed on each in-process interconnect structure 500' and can be incorporated into the corresponding in-process interconnect structure 500'. The optical waveguide 572 can include any optical waveguide material known to those skilled in the art, such as silicon, silicon nitride, etc. The width and height of the optical waveguide 572 can be selected based on the wavelength of the photons used to be transmitted through the optical waveguide 572 to ensure total internal reflection at the interface between the optical waveguide 572 and the additional interlayer dielectric layer 560.

[0094] A subset of optical waveguides 572 may be formed near the topmost surface of the in-process interconnect structure 500' and may be configured to evanescently couple with an optical waveguide to be provided in a semiconductor die that is subsequently attached to the in-process interconnect structure 500'. The subset of optical waveguides 572 may have a depth from a horizontal plane including the topmost surface of the in-process interconnect structure 500' of 30 nm to 200 nm, although lesser and greater depths may also be used. An optical converter 570, if present, may be embedded in the additional interlayer dielectric layer 560 and may be connected to a corresponding one of the optical waveguides 572. The optical converter 570 may be configured to provide conversion between an optical signal in the optical waveguide 572 and an electrical signal transmitted to the subset of metal wiring structures 580. For example, the optical converter 570 may include a photodetector, a light emitting diode, and / or a photonic memory device.

[0095] The metal bonding structure 588 includes a metal bonding pad or a metal bonding column. For example, the metal bonding structure 588 may include a controlled collapse chip connection (C4) bonding pad or a chip connection (C2) columnar structure (also referred to as a microbump structure). Alternatively, the metal bonding structure 588 may be configured as a metal-to-metal bond. The metal bonding structure 588 may have a thickness (i.e., height) from 10 μm to 60 μm, but smaller and larger thicknesses may also be used. In one embodiment, the metal bonding structure 588 may be formed as an array of microbumps (e.g., copper pillars) having a lateral dimension from 10 μm to 25 μm and a pitch from 20 μm to 50 μm.

[0096] Please refer to Figure 4 A photoresist layer (not shown) may be applied over the array of interconnect structures 500' in the process and may be photolithographically patterned to form two sets of intersecting, laterally extending openings. The width of the laterally extending openings may be greater than the width of a saw blade subsequently used to cut the array of interconnect structures 500' in the process. For example, the width of the laterally intersecting openings in the photoresist layer may be from 50 μm to 300 μm, although smaller and larger widths may also be used.

[0097] An anisotropic etching process may be performed to transfer the pattern of laterally extending openings in the photoresist layer through the array of in-process interconnect structures 500' to the upper portion of the silicon substrate 409. Two sets of intersecting trenches may be formed in the void, from which material of the in-process interconnect structures 500' (and specifically, material of the interlayer dielectric layer 560) and material of the silicon substrate 409 are removed. These two sets of intersecting trenches are referred to herein as channel trenches 571. In one embodiment, the channel trenches 571 may include a first channel trench extending laterally along a first horizontal direction and a second channel trench extending laterally along a second horizontal direction perpendicular to the first horizontal direction.

[0098] Each patterned portion of the in-process interconnect structure 500' located within the corresponding unit area UA constitutes an interconnect structure 500. In one embodiment, each interconnect structure 500 may include four straight sidewalls abutting each other at vertically extending edges. In one embodiment, a channel trench 571 may be laterally defined by the straight sidewalls of the interconnect structure 500 and may have a corresponding uniform width. Generally speaking, the channel trench 571 is formed through the interlayer dielectric layer 560 and into the upper portion of the silicon substrate 409 at the location of the cutting channel used to subsequently singulate the interconnect structure 500. Each interconnect structure 500 may include an interconnect interposer.

[0099] Please refer to Figure 5 At least one semiconductor die 700 may be bonded to a corresponding interconnect structure 500 within a corresponding unit area UA. In one embodiment, a plurality of semiconductor dies 700 may be bonded to a corresponding interconnect structure 500 within each unit area UA. In one embodiment, the plurality of semiconductor dies 700 may include a logic die 701 and an optical device die 702, wherein the optical device die 702 includes an optical device, such as an optical switch (not explicitly shown). In this case, the optical device die 702 may include a plurality of optical waveguides 772 arranged in the same configuration and located adjacent to the plurality of optical waveguides 572 of the underlying interconnect structure 500. The pattern of the plurality of optical waveguides 772 may be the same as that of the plurality of optical waveguides 572 in the underlying interconnect structure 500, and may overlap with the plurality of optical waveguides 572 in the underlying interconnect structure 500 in a vertical direction in a plan view. The vertical distance between the facing pair of optical waveguides 572 in the interconnect structure 500 and the optical waveguides 772 in the optical device die 702 (i.e., the optically coupled pair) is sufficiently short to enable evanescent coupling between the facing pair of optical waveguides 572 and 772. For example, the vertical distance can be from 600 nm to 400 nm, although smaller and larger vertical distances can also be used. In the presence of evanescent optical coupling, photons in the optical waveguide 572 in the interconnect structure 500 can be converted to the optically coupled optical waveguide 772 in the optical device die 702, and vice versa. The optical converter in the optical device die can capture photons from the optical waveguide 772 or emit photons to the optical waveguide 772.

[0100] In one embodiment, each semiconductor die 700 may include a corresponding array of on-wafer bonding structures 788 configured to bond to a corresponding subset of metal bonding structures 588 of a corresponding interconnect structure 500. The on-wafer bonding structures 788 may include metal bonding pads configured for direct metal-to-metal bonding. Specifically, the on-wafer bonding structures 788 may be configured for direct metal-to-metal bonding with the corresponding array of metal bonding structures 588. The semiconductor die 700 may be bonded to a corresponding one of the interconnect structures 500 via metal-to-metal bonding without using a portion of solder material to eliminate any gaps between the interconnect structure 500 and the semiconductor die 700.

[0101] Please refer to Figure 6 , the optical adhesive material can be conformally deposited in the channel groove 571. The optical adhesive material includes an optically transparent material and provides adhesion to various materials such as polymer materials, plastic surfaces, semiconductor surfaces and / or metal surfaces. Exemplary optical adhesive materials include epoxy resin-based adhesive materials, UV-curable adhesive materials, silicone-based adhesive materials, acrylic adhesive materials, polyurethane adhesive materials, etc. The portion of the optical adhesive material formed above the horizontal plane of the topmost surface of the two-dimensional array comprising the interconnect structure 500 can be removed by performing a recessed etching process, which may include an isotropic etching process or an anisotropic etching process. After the recessed etching process, a suitable cleaning process can be performed to remove the remaining portion of the optical adhesive material from the surface of the semiconductor die 700. The remaining portion of the optical adhesive filling the channel groove 571 includes an optical adhesive groove filling structure 901, which includes two sets of intersecting optical adhesive material tracks extending laterally along their respective horizontal directions. For example, a first track of optical adhesive material may extend laterally along a first horizontal direction, and a second track of optical adhesive material may extend laterally along a second horizontal direction perpendicular to the first horizontal direction. Each track of optical adhesive material may have a uniform width and may contact the straight sidewalls of a corresponding pair of rows of the interconnect structure 500.

[0102] Please refer to Figure 7, an encapsulant (such as a molding compound (MC) material) can be applied to the gaps between the semiconductor dies 700. The molding compound material may include a hardenable (i.e., solidified) epoxy resin compound to provide sufficient rigidity and mechanical strength to the dielectric material portion. The molding compound material may contain an epoxy resin, a hardener, silicon dioxide (as a filler material) and other additives. Depending on the viscosity and fluidity, the molding compound material can be provided in liquid form or solid form. Liquid molding compound materials generally provide better workability, good fluidity, fewer voids, better filling and fewer flow marks. Solid molding compound materials generally provide less curing shrinkage, better isolation and less die drift. A higher filling level in the molding compound material (e.g., 85% by weight) can shorten the molding time, reduce mold shrinkage, and reduce mold warpage. A consistent filler size distribution in the molding compound material can reduce flow marks and enhance fluidity.

[0103] The mold compound material may be cured at a curing temperature to form a mold compound (MC) matrix 730M, referred to herein as a die-level mold compound matrix. The mold compound matrix 730M laterally surrounds each semiconductor die 700.

[0104] The mold compound matrix 730M can be a continuous layer of material extending across the entire area of the reconstituted wafer. A planarization process (e.g., a chemical mechanical polishing process) can be performed to planarize the mold compound matrix 730M. The top surface of the mold compound matrix 730M can be formed in a horizontal plane that includes the top surfaces of the semiconductor dies 700. Each portion of the mold compound matrix 730M located in a corresponding unit area UA constitutes a mold compound (MC) die frame. Thus, the mold compound matrix 730M can include a two-dimensional array of adjacent mold compound interposer frames. Each mold compound interposer frame can be located in a corresponding unit area UA and laterally surround a corresponding group of at least one semiconductor die 700.

[0105] Figure 7 The intermediate structure after the processing steps includes a reconstructed wafer, which includes a silicon substrate 409, a two-dimensional array of interconnect structures 500 (a two-dimensional array of interconnect interposers, each interconnect interposer including an optical waveguide 572 and optionally including an optical converter 570), a two-dimensional array of at least one semiconductor die 700, and a molding compound matrix 730M (including a two-dimensional array of molding compound die frames).

[0106] Please refer to Figure 8The silicon substrate 409 may be thinned from the back side, for example, by performing a grinding process, a polishing process, an anisotropic etching process, and / or an isotropic etching process. The bottom of the dielectric spacer 412 and / or the through-silicon via structure 420 may serve as a stop structure for the final step of the thinning process, which may include a grinding step, an anisotropic etching step, or an isotropic etching step. The thickness of the silicon substrate 409 after the thinning process may be in the range of 2 μm to 30 μm, for example, from 6 μm to 15 μm, although smaller and larger thicknesses may also be used.

[0107] Please refer to Figure 9 A selective etching process can be performed to selectively etch the silicon in the silicon substrate 409 relative to the material of the dielectric spacers 412 and the TSV structures 420, thereby vertically recessing the physically exposed backside surface of the silicon substrate 409. For example, a wet etching process using a potassium hydroxide (KOH) solution or a tetramethylammonium hydroxide (TMAH) solution can be performed to vertically recess the backside surface of the silicon substrate 409. A dielectric material (e.g., undoped silicate glass or doped silicate glass) can be deposited on the vertically recessed backside surface of the silicon substrate 409, and a planarization process (e.g., a chemical mechanical polishing process) can be performed to provide a flat surface coplanar with the bottom surface of the TSV structures 420. The remaining horizontal extension of the deposited and planarized dielectric material forms a backside dielectric layer 430, which can have a thickness of from 50 nm to 500 nm, although lesser and greater thicknesses can also be used.

[0108] An underbump metallurgy (UBM) layer stack may subsequently be deposited on the physically exposed backside surfaces of the TSV structures 420 and on the backside surface of the backside dielectric layer 430. The UBM layer stack may be patterned into discrete material portions that contact the bottom surface of a corresponding one of the TSV structures 420 to form interposer-side bond pads 488, which may include controllable collapse chip connection bond pads. The combination of the silicon substrate 409, TSV structures 420, dielectric spacers 412, backside dielectric layer 430, and interposer-side bond pads 488 may comprise a two-dimensional array of silicon interposers 400. Each silicon interposer 400 may be located within a corresponding unit area UA. A solder material portion 490 may be formed on each interposer-side bond pad 488.

[0109] The reconstructed wafer includes a two-dimensional array of composite interposers (silicon interposers 400 and interconnect structures 500). Each composite interposer includes an interconnect interposer, which is an interconnect structure 500 located within a corresponding unit area UA. Each composite interposer also includes a silicon interposer 400, which includes a portion of a silicon substrate 409 located within a corresponding unit area UA, an array of through-silicon via structures 420, an array of dielectric spacers 412, an array of interposer-side bonding pads 488, and a portion of a backside dielectric layer 430. The reconstructed wafer also includes a two-dimensional array of semiconductor dies 700 and a molding compound matrix 730M.

[0110] Please refer to Figure 10 The reconstructed wafer can be cut along the cutting lanes by performing a dicing process. Specifically, the array of mold compound matrix 730M and composite interposer (silicon interposer 400, interconnect structure 500) can be cut into discrete composite semiconductor packages 800. The dicing lanes correspond to the boundaries between adjacent pairs of unit areas UA and are located in the middle of the optical adhesive material tracks in the optical adhesive trench filling structure 901. In one embodiment, the width of the dicing blade can be smaller than the width of each optical adhesive material track in the optical adhesive trench filling structure 901.

[0111] Each cut unit of the reconstructed wafer includes a composite semiconductor package 800. The continuous combination of the silicon interposer 400 and the interconnect structure 500 (which is an interconnect interposer) comprises a composite interposer. Each composite interposer (silicon interposer 400, interconnect structure 500) is a composite interposer. Figure 9 The two-dimensional array of composite interposers in the reconstructed wafer is provided after the processing steps. Each composite semiconductor package 800 includes a corresponding silicon interposer 400, which includes a cut portion of the silicon substrate 409, an array of through-silicon via structures 420, a backside dielectric layer 430, and an array of interposer-side bonding pads 488. Each composite semiconductor package 800 includes a corresponding interconnect structure 500, which is an interconnect interposer. Each cut portion of the mold compound matrix 730M forms a mold compound die frame (i.e., MC die frame) 730. Therefore, each composite semiconductor package 800 includes at least one semiconductor die 700 and a mold compound die frame 730.

[0112] According to one aspect of an embodiment of the present invention, the remaining portion of the optical adhesive trench-fill structure 901 can be provided on each composite semiconductor package 800. Each remaining portion of the optical adhesive trench-fill structure 901 is referred to herein as a first optical adhesive portion 902. After dicing and reconstructing the wafer, the first optical adhesive portion 902 is located on the corresponding composite interposer (silicon interposer 400, interconnect structure 500). Each composite interposer (silicon interposer 400, interconnect structure 500) includes a metal wiring structure 580 and an optical waveguide 572 embedded in an interlayer dielectric layer 560. Each first optical adhesive portion 902 can be provided on the stepped outer sidewall 60 of the corresponding composite semiconductor package 800. Furthermore, each first optical adhesive portion 902 can be provided on the stepped outer sidewall (second outermost vertical surface segment 62, laterally recessed sidewall segment 63, second connection horizontal surface segment 65) of the corresponding composite interposer (silicon interposer 400, interconnect structure 500).

[0113] In one embodiment, the stepped outer sidewall 60 of the composite semiconductor package 800 may include a first outermost vertical surface segment 61 located in a vertical plane VP (which may be a flat vertical surface located in a vertical Euclidean plane), a second outermost vertical surface segment 62 located in the vertical plane VP, a laterally recessed sidewall segment 63 that is recessed laterally inward relative to the vertical plane VP (i.e., toward the interconnect structure 500), a first connecting horizontal surface segment 64 connecting an edge of the first outermost vertical surface segment 61 to an edge of the laterally recessed sidewall segment 63, and a second connecting horizontal surface segment 65 connecting an edge of the second outermost vertical surface segment 62 to another edge of the laterally recessed sidewall segment 63.

[0114] In one embodiment, a composite semiconductor package 800 includes an interconnect interposer (including an interconnect structure 500) and a silicon interposer 400 (including a silicon substrate 409 and a plurality of through-silicon via structures 420 extending vertically through the silicon substrate 409). A laterally recessed sidewall segment 63 includes sidewall surface segments of the silicon interposer 400 and the interconnect interposer. A second connected horizontal surface segment 65 includes a horizontal surface segment of the silicon interposer 400. In one embodiment, the entirety of the laterally recessed sidewall segment 63 may be a straight, flat sidewall, so that the sidewall surface segments of the silicon interposer 400 and the interconnect interposer may lie in a different vertical plane. In one embodiment, the first connected horizontal surface segment 64 includes a horizontal surface segment of the mold compound die frame 730 and may lie in the same horizontal plane as the top surface of the interconnect structure 500 (i.e., the interconnect interposer).

[0115] In one embodiment, the composite interposer (silicon interposer 400, interconnect structure 500) includes a stepped outer sidewall, which includes an outermost vertical surface segment (e.g., second outermost vertical surface segment 62), a laterally recessed sidewall segment 63 that is laterally recessed relative to the outermost vertical surface segment, and a connecting horizontal surface segment (e.g., second connecting horizontal surface segment 65) connecting the outermost vertical surface segment and the laterally recessed vertical sidewall segment. In one embodiment, at least one semiconductor die 700 can be attached to the metal bonding structure 588 of the composite interposer (silicon interposer 400, interconnect structure 500).

[0116] In one embodiment, the mold compound die frame 730 laterally surrounds at least one semiconductor die 700. The outermost vertical surface segments (e.g., the second outermost vertical surface segment 62) lie in the same vertical plane VP as the sidewalls of the mold compound die frame 730, which includes the first outermost vertical surface segment 61 of the stepped outer sidewalls 60 of the composite semiconductor package 800. In one embodiment, the laterally recessed sidewall segments 63 extend vertically from the topmost surface of the interlayer dielectric layer 560 to at least the bottommost surface of the interlayer dielectric layer 560 and may extend to the recessed horizontal surface of the silicon interposer 400, which includes the second connecting horizontal surface segment 65 of the stepped outer sidewalls 60 of the composite semiconductor package 800.

[0117] In one embodiment, the composite interposer (silicon interposer 400, interconnect structure 500) includes a silicon interposer 400 including a silicon substrate 409 and a plurality of through-silicon via structures 420 extending vertically through the silicon substrate 409; and the laterally recessed sidewall segment 63 includes a sidewall surface segment of the silicon interposer 400. In one embodiment, the outermost vertical sidewall surface segment (e.g., the second outermost vertical surface segment 62 of the stepped outer sidewall 60 of the composite semiconductor package 800) includes a sidewall surface segment of the silicon interposer 400; and the connecting horizontal surface segment (e.g., the second connecting horizontal surface segment 65 of the stepped outer sidewall 60 of the composite semiconductor package 800) includes a horizontal surface segment of the silicon interposer 400.

[0118] In one embodiment, the first optical adhesive portion 902 may have a configuration of a rectangular frame of uniform height, a set of four inner vertical sidewalls, and a set of four outer vertical sidewalls. In one embodiment, the lateral distance between adjacent pairs of the inner vertical sidewalls and the outer vertical sidewalls of each first optical adhesive portion 902 may be in a range from 10 μm to 200 μm, for example, from 20 μm to 100 μm, although smaller and larger lateral distances may also be used. Alternatively, the cutting of the optical adhesive trench fill structure 901 may be performed off-center relative to the geometric center of the optical adhesive material track, and a first subset of the sidewalls of the composite semiconductor package 800 may include the first optical adhesive portion 902 and the stepped outer sidewalls 60, and a second subset of the sidewalls of the composite semiconductor package 800 may be free of any optical adhesive portions and may consist of corresponding straight sidewalls.

[0119] Please refer to Figure 11 The composite semiconductor package 800 can be bonded to a package substrate 200. The package substrate 200 can be a cored package substrate including a core substrate 210 or a coreless package substrate without a package core. Alternatively, the package substrate 200 can include a system-on-integrated packaging substrate (SoIS) that includes a redistribution layer, a dielectric interlayer, and / or at least one buried interposer (e.g., a silicon interposer). This system-on-integrated package substrate can include layer-to-layer interconnects using interposer-side solder material portions, microbumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. While embodiments of the present invention are described using a cored package substrate, it should be understood that the scope of the present invention is not limited to any particular type of substrate package. For example, a system-on-integrated package substrate can be used in place of a cored package substrate. In embodiments using a system-on-integrated package substrate, the core substrate 210 can include a glass epoxy plate that includes an array of through-plate holes. An array of through-core via structures 214 comprising a metallic material may be provided in the through-board hole. Each through-core via structure 214 may or may not include a cylindrical hollow core therein. Optionally, a dielectric liner (not shown) may be used to electrically isolate the through-core via structures 214 from the core substrate 210.

[0120] The package substrate 200 may include a board-side surface laminar circuit (SLC) 240 and a chip-side surface laminar circuit (SLC) 260. The board-side surface laminar circuit 240 may include a board-side insulating layer 242 having board-side wiring interconnects 244 formed therein. The chip-side surface laminar circuit 260 may include a chip-side insulating layer 262 having chip-side wiring interconnects 264 formed therein. The board-side insulating layer 242 and the chip-side insulating layer 262 may include a photosensitive epoxy material, which may be photolithographically patterned and then cured. The board-side wiring interconnects 244 and the chip-side wiring interconnects 264 may include copper, which may be deposited by electroplating within patterns in the board-side insulating layer 242 or the chip-side insulating layer 262.

[0121] In one embodiment, the chip-side surface build-up circuit 260 includes a chip-side wiring interconnect 264 connected to an array of substrate bonding pads 268. The array of substrate bonding pads 268 can be configured to allow bonding via controlled collapse chip connection solder balls. The board-side surface build-up circuit 240 includes a board-side wiring interconnect 244 connected to an array of board-side bonding pads 248. The array of board-side bonding pads 248 can be configured to allow bonding via solder joints having a larger size than the controlled collapse chip connection solder balls. Although the present invention describes an embodiment using a package substrate 200 including the chip-side surface build-up circuit 260 and the board-side surface build-up circuit 240, embodiments are expressly contemplated herein in which either the chip-side surface build-up circuit 260 or the board-side surface build-up circuit 240 is omitted or replaced with an array of bonding structures, such as microbumps. In the example shown, the chip-side surface build-up circuit 260 can be replaced with an array of microbumps or other bonding structures.

[0122] In one embodiment, package substrate 200 includes a first horizontal surface configured to face composite semiconductor package 800. The first horizontal surface is the surface facing the substrate horizontal surface that faces composite semiconductor package 800 during subsequent assembly processes. Package substrate 200 also includes a second horizontal surface located opposite the first horizontal surface. Substrate bonding pads 268 of package substrate 200 may be located on the first horizontal surface of package substrate 200 and may have a mirror image pattern of interposer-side bonding pads 488.

[0123] Specifically, each solder material portion 490 may be bonded to a corresponding one of the substrate bonding pads 268 and a corresponding one of the interposer-side bonding pads 488. A reflow process may be performed to reflow the solder material portions 490 so that each solder material portion 490 is bonded to a corresponding one of the substrate bonding pads 268 and a corresponding one of the interposer-side bonding pads 488.

[0124] An underfill material may be applied to the gap between the composite interposer (silicon interposer 400, interconnect structure 500) and the package substrate 200. The underfill material may include any underfill material known to those skilled in the art. An underfill material portion may be formed in the gap between the composite interposer (silicon interposer 400, interconnect structure 500) and the package substrate 200, surrounding the array of interposer-side bond pads 488, the array of substrate bond pads 268, and the array of solder material portions 490. The underfill material portion formed between the composite interposer (silicon interposer 400, interconnect structure 500) and the package substrate 200 is referred to herein as an interposer-package underfill material portion (IP underfill material portion) 492. A stiffener ring (not shown) may be attached to the physically exposed surface of the mold compound die frame 730, for example, using an adhesive layer (not shown).

[0125] A printed circuit board (PCB) 100 including a printed circuit board substrate 110 and printed circuit board bonding pads 180 may be provided. The printed circuit board 100 includes a printed circuit (not shown) on at least one side of the printed circuit board 100. Solder joints 190 may be formed to bond the array of board-side bonding pads 248 to the array of printed circuit board bonding pads 180. The solder joints 190 may be formed by placing an array of solder balls between the array of board-side bonding pads 248 and the array of printed circuit board bonding pads 180 and by reflowing the array of solder balls. An additional underfill material portion (referred to herein as a board-substrate underfill material portion (BS underfill material portion) 292) may be formed around the solder joints 190 by applying and shaping the underfill material. The package substrate 200 is attached to the printed circuit board 100 via the array of solder joints 190.

[0126] Please refer to Figure 12, the fiber access unit 910 can be attached to the composite semiconductor package 800 by using the second optical adhesive portion 904. As used herein, the fiber access unit (FAU) 910 refers to any external device that can optically couple the optical waveguide 572. In some embodiments, the fiber access unit 910 can be referred to as a fiber array unit. The fiber access unit 910 can be used as an interface device between an external optical system and the optical waveguide 572 in a semiconductor device (e.g., the interconnect structure 500 in the composite semiconductor package 800). The external optical system may include a module transceiver 930, which is optically coupled to the fiber access unit 910 via an optical cable 920. The module transceiver 930 can perform the functions of transmitting and receiving optical signals. In other words, the module transceiver 930 converts electrical signals into optical signals for transmission via the optical cable 920, and vice versa.

[0127] According to one aspect of an embodiment of the present invention, a fiber access unit 910 can be optically coupled to a subset of optical waveguides 572 via a combination of a first optical adhesive portion 902 and a second optical adhesive portion 904. In one embodiment, the first optical adhesive portion 902 is formed on the composite interposer (silicon interposer 400, interconnect structure 500) during cleaving of the composite interposer (silicon interposer 400, interconnect structure 500). The second optical adhesive portion 904 can comprise any material suitable for the first optical adhesive portion 902 and can be applied in a sufficient amount to provide a reliable and strong bond between the first optical adhesive portion 902 and the fiber access unit 910. In one embodiment, the first optical adhesive portion 902 contacts the laterally recessed sidewall segment 63 and has an outer sidewall in a vertical plane VP including the first outermost vertical surface segment 61; and the second optical adhesive portion 904 contacts the first end of the fiber access unit 910 and has an inner sidewall that contacts the outer sidewall of the first optical adhesive portion 902. The thickness of the second optical adhesive portion 904 may be in the range from 20 μm to 400 μm, although lesser and greater thicknesses may also be used.

[0128] Generally, at least one optical adhesive portion (the first optical adhesive portion 902, the second optical adhesive portion 904) is disposed between the fiber access unit 910 and the laterally recessed sidewall section 63 of the stepped outer sidewall 60. In one embodiment, at least one optical adhesive portion (the first optical adhesive portion 902, the second optical adhesive portion 904) contacts the horizontal bottom surface section of the mold compound die frame 730 (which is the first connecting horizontal surface section 64 of the stepped outer sidewall 60) and the bottom of the sidewall of the mold compound die frame 730 (which is the first outermost vertical surface section 61 of the stepped outer sidewall 60).

[0129] Please refer to Figure 13 , available from Figure 12A first alternative embodiment of the exemplary structure is derived from the exemplary structure of FIG. , in which the first optical adhesive portion 902 is partially or completely removed so that the laterally recessed sidewall section 63 of the stepped outer sidewall 60 is physically exposed before forming the second optical adhesive portion 904. In this embodiment, a suitable selective cleaning process can be performed to selectively remove the first optical adhesive portion 902 relative to the interlayer dielectric layer 560 before forming the second optical adhesive portion 904. The second optical adhesive portion 904 can be formed directly on the laterally recessed sidewall section 63 of the stepped outer sidewall 60.

[0130] Alternatively, a sacrificial filling material (e.g., amorphous carbon, diamond-like carbon, or a polymer material) may be used in place of the optical adhesive material used for the optical adhesive trench filling structure 901. In this embodiment, the sacrificial filling material may be removed at any processing step after cutting the redistribution wafer and before forming the second optical adhesive portion 904. In other words, the optical adhesive material used for the optical adhesive trench filling structure 901 may be replaced by any sacrificial filling material, and the sacrificial filling material may be removed after the cutting process of forming the composite semiconductor package 800.

[0131] In a first alternative configuration of the exemplary structure, the fiber access unit 910 can be attached to the composite semiconductor package 800 using a single second optical adhesive portion 904, which can have a homogenous material composition and can contact the laterally recessed sidewall section 63 and the first end of the fiber access unit 910. The thickness of the second optical adhesive portion 904 can range from 20 μm to 400 μm, although lesser and greater thicknesses can also be used.

[0132] Please refer to Figure 14 A second alternative configuration of the exemplary structure can be derived from any of the above configurations for the exemplary structure by forming a first optical adhesive portion 902 or sacrificial material portion on fewer than four sidewalls of the composite interposer (silicon interposer 400, interconnect structure 500). In this embodiment, the first optical adhesive portion 902 or sacrificial material portion can be formed on one, two, or three sidewalls of the composite interposer (silicon interposer 400, interconnect structure 500). The composite semiconductor package 800 can include one, two, or three stepped outer sidewalls, and include at least one straight sidewall entirely contained within a flat vertical plane.

[0133] Please refer to Figure 15A third alternative configuration of the exemplary structure can be derived from any of the aforementioned configurations for the exemplary structures by disposing the module transceiver 930 on a surface of the package substrate 200, such as the top surface or sidewall of the package substrate 200. In this embodiment, an adhesive layer 931 can be used to secure the module transceiver 930 to the top surface or sidewall of the package substrate 200. This arrangement can increase the structural stability of the module transceiver 930 and mitigate structural damage to the module transceiver 930 during operation of the device of the present invention. Furthermore, during operation of the module transceiver 930, the package substrate 200 can serve as a heat sink for the module transceiver 930.

[0134] Please refer to Figure 16 , showing a flow chart of steps for forming a device structure according to an embodiment of the present invention.

[0135] Please refer to step 1610 and Figures 1 to 11 , providing an interposer (silicon interposer 400, interconnect structure 500), the interposer includes a metal wiring structure 580 and an optical waveguide 572 buried in an interlayer dielectric layer 560, and also includes a stepped outer sidewall 60, the stepped outer sidewall 60 includes a laterally recessed sidewall section 63, the laterally recessed sidewall section 63 includes a vertically extending surface of the interlayer dielectric layer 560 and a lateral recess relative to the first outermost vertical surface section 61.

[0136] Please refer to step 1620 and Figures 12 to 14 The first end of the fiber access unit 910 is optically coupled to a subset of the optical waveguides 572 via at least one optical adhesive portion (optionally a first optical adhesive portion 902, a second optical adhesive portion 904). The at least one optical adhesive portion (optionally a first optical adhesive portion 902, a second optical adhesive portion 904) is disposed between the fiber access unit 910 and the laterally recessed sidewall section 63 of the stepped outer sidewall 60.

[0137] With reference to all the drawings and according to various embodiments of the present invention, a device structure is provided, comprising: an interposer (silicon interposer 400, interconnect structure 500), comprising a metal wiring structure 580 and an optical waveguide 572 buried in an interlayer dielectric layer 560, wherein the interposer (silicon interposer 400, interconnect structure 500) comprises a stepped outer sidewall (a second outermost vertical surface segment 62, a laterally recessed sidewall segment 63, and a second connecting horizontal surface segment 65), the stepped outer sidewall comprising an outermost vertical surface segment (e.g., the second outermost vertical surface segment 62), a laterally recessed sidewall segment 63 relative to the outermost vertical surface segment (e.g., the second outermost vertical surface segment 62), and a second connecting horizontal surface segment 65. a recessed transverse recessed side wall section 63 and a connecting horizontal surface section (e.g., a second connecting horizontal surface section 65) connecting the outermost vertical surface section (e.g., the second outermost vertical surface section 62) and the transverse recessed side wall section 63; and an optical fiber access unit 910 having a first end, the first end being optically coupled to a subset of the optical waveguides 572 by at least one optical glue portion (optionally a first optical glue portion 902, a second optical glue portion 904) disposed between the optical fiber access unit 910 and the transverse recessed side wall section 63 of the stepped outer side wall (the second outermost vertical surface section 62, the transverse recessed side wall section 63, the second connecting horizontal surface section 65).

[0138] In one embodiment, the device structure further includes at least one semiconductor die 700 attached to the metal wiring structure of the interposer (silicon interposer 400, interconnect structure 500). In one embodiment, the device structure further includes a mold compound die frame 730 laterally surrounding the at least one semiconductor die 700, wherein the outermost vertical surface segment (e.g., the second outermost vertical surface segment 62) lies in the same vertical plane VP as the sidewalls of the mold compound die frame 730. In one embodiment, at least one optical glue portion (optionally, the first optical glue portion 902, the second optical glue portion 904) contacts the horizontal bottom surface segment of the mold compound die frame 730 and the bottom of the sidewalls of the mold compound die frame 730.

[0139] In one embodiment, the laterally recessed sidewall segment 63 extends vertically from the topmost surface of the interlayer dielectric layer 560 to at least the bottommost surface of the interlayer dielectric layer 560. In one embodiment, the interposer (silicon interposer 400, interconnect structure 500) includes a silicon interposer 400, which includes a silicon substrate 409 and a plurality of through-silicon via structures 420 extending vertically through the silicon substrate 409; and the laterally recessed sidewall segment 63 includes a sidewall surface segment of the silicon interposer 400. In one embodiment, the outermost vertical surface segment (e.g., the second outermost vertical surface segment 62) includes a sidewall surface segment of the silicon interposer 400; and the connecting horizontal surface segment (e.g., the second connecting horizontal surface segment 65) includes a horizontal surface segment of the silicon interposer 400.

[0140] In one embodiment, at least one optical adhesive portion (a first optical adhesive portion 902, a second optical adhesive portion 904) includes: a first optical adhesive portion 902, contacting the laterally recessed side wall segment 63, and having an outer side wall in a vertical plane VP of an outermost vertical surface segment (for example, the second outermost vertical surface segment 62) including a stepped outer side wall (a second outermost vertical surface segment 62, a laterally recessed side wall segment 63, a second connecting horizontal surface segment 65); and a second optical adhesive portion 904, contacting the first end of the optical fiber access unit 910, and having an inner side wall contacting the outer side wall of the first optical adhesive portion 902.

[0141] In one embodiment, at least one optical adhesive portion (second optical adhesive portion 904) includes a single optical adhesive portion and / or is composed of a single optical adhesive portion, the second optical adhesive portion 904 has a homogeneous material composition and contacts the transverse recessed sidewall section 63 and the first end of the optical fiber access unit 910.

[0142] In one embodiment, the interposer (silicon interposer 400, interconnect structure 500) includes an optical converter connected to one of the optical waveguides 572 and buried in the interlayer dielectric layer 560, and the optical converter is configured to provide conversion between an optical signal in one of the optical waveguides 572 and an electrical signal transmitted to a corresponding one of the metal wiring structures 580.

[0143] In one embodiment, at least one semiconductor die 700 includes additional optical waveguides 772 coupled to a subset of the optical waveguides 572 in the interposer (silicon interposer 400, interconnect structure 500) via evanescent coupling, enabling optical signals to be transmitted across the interface between one of the at least one semiconductor die 700 and the interposer (silicon interposer 400, interconnect structure 500).

[0144] According to another aspect of an embodiment of the present invention, a component is provided, comprising a composite semiconductor package 800, comprising an interposer (silicon interposer 400, interconnect structure 500) and at least one semiconductor die 700 attached to the interposer (silicon interposer 400, interconnect structure 500), wherein the interposer (silicon interposer 400, interconnect structure 500) comprises a metal wiring structure 580 and an optical waveguide 572 embedded in an interlayer dielectric layer 560, and the interposer further comprises a stepped outer sidewall 60, the stepped outer sidewall comprising an outermost vertical surface segment and a vertical surface segment relative to the outermost surface segment. a laterally recessed sidewall section in which the vertical surface section is laterally recessed; a molding compound (molding compound die frame 730); and a fiber access unit 910 having a first end, the first end being optically coupled to a subset of the optical waveguides 572 by at least one optical glue portion (optionally a first optical glue portion 902, a second optical glue portion 904) disposed between the fiber access unit 910 and the laterally recessed sidewall section 63 of the stepped outer side wall 60, wherein the sidewall of the first optical glue portion 902 is aligned with the sidewall of the molding compound (molding compound die frame 730).

[0145] In one embodiment, the stepped outer sidewall 60 includes a first connecting horizontal surface segment 64 connecting an edge of the first outermost vertical surface segment 61 to an edge of the laterally recessed sidewall segment 63; and a second outermost vertical surface segment 62 connected to the laterally recessed sidewall segment 63 via a second connecting horizontal surface segment 65. In one embodiment, the composite semiconductor package 800 includes a silicon interposer 400 comprising a silicon substrate 409 and a plurality of through-silicon via structures 420 extending vertically through the silicon substrate 409; the laterally recessed sidewall segment 63 comprises a sidewall surface segment of the silicon interposer 400; and the second connecting horizontal surface segment 65 comprises a horizontal surface segment of the silicon interposer 400. In one embodiment, at least one optical adhesive portion (optionally a first optical adhesive portion 902 or a second optical adhesive portion 904) contacts the laterally recessed sidewall segment 63 of the stepped outer sidewall 60 and the horizontal surface segment of the silicon interposer 400.

[0146] In one embodiment, at least one optical glue part (a first optical glue part 902, a second optical glue part 904) includes: a first optical glue part 902, contacting the laterally recessed side wall section 63 and having an outer side wall in a vertical plane VP including the first outermost vertical surface section 61; and a second optical glue part 904, contacting the first end of the optical fiber access unit 910 and having an inner side wall contacting the outer side wall of the first optical glue part 902.

[0147] Various embodiments of the present invention can be used to provide a smooth optical interface between the interlayer dielectric layer 560 and at least one optical adhesive portion (first optical adhesive portion 902, second optical adhesive portion 904) to provide optical coupling between the interposer (silicon interposer 400, interconnect structure 500) and the optical fiber access unit 910.

[0148] According to another aspect of an embodiment of the present invention, a method for forming a device structure is provided, which includes providing an intermediary layer, the intermediary layer including a metal wiring structure and an optical waveguide buried in an interlayer dielectric layer, and the intermediary layer also including a stepped outer wall, the stepped outer wall including a laterally recessed sidewall section, the laterally recessed sidewall section including a vertically extending surface of the interlayer dielectric layer and being laterally recessed relative to the first outermost vertical surface section; and optically coupling the first end of the optical fiber access unit to a subset of the optical waveguides through at least one optical adhesive portion, wherein the at least one optical adhesive portion is arranged between the optical fiber access unit and the laterally recessed sidewall section of the stepped outer wall.

[0149] In one embodiment, the method further comprises forming a reconstructed wafer comprising an array of a plurality of interposers; and dicing the reconstructed wafer, wherein the interposers are diced portions of the array of a plurality of interposers.

[0150] In one embodiment, the method further comprises filling trenches between the plurality of interposers of the array of the plurality of interposers with an optical adhesive material, wherein after sawing the reconstituted wafer, at least one optical adhesive portion comprises a remaining portion of the optical adhesive material.

[0151] In one embodiment, the reconstructed wafer includes a silicon substrate including a plurality of through-silicon via (TSV) structures; a metal wiring structure and an optical waveguide are formed above the silicon substrate; and a trench is formed through an interlayer dielectric layer and into an upper portion of the silicon substrate.

[0152] In one embodiment, the method further includes attaching a semiconductor die to an array of a plurality of interposers; forming a molding compound matrix around the semiconductor die; and cutting the molding compound matrix and the array of the plurality of interposers, wherein at least one optical adhesive portion includes a first optical adhesive portion positioned on the interposer when the array of the plurality of interposers is cut.

[0153] The foregoing text summarizes the features of many embodiments so that those skilled in the art can better understand the present invention embodiments from all aspects. Each embodiment described using the term "comprising" also inherently discloses additional embodiments, wherein unless otherwise clearly disclosed herein, the term "comprising" is replaced with "substantially consisting of..." or the term "consisting of...". Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, the Markush group (Markush group) of the list comprising two or more elements is also implicitly disclosed. Whenever the auxiliary verb "may" is used in the present disclosure to describe the formation of an element or the performance of a processing step, it is also explicitly envisioned that such an element is not formed or such a processing step is not performed, as long as the resulting equipment or device can provide equivalent results. Therefore, whenever the formation of such an element or such a processing step is omitted and the same or equivalent results are provided, the auxiliary verb "may" applied to the formation of an element or the performance of a processing step should also be interpreted as "may" or "may or may not", and equivalent results include slightly better results and slightly worse results. Those skilled in the art will readily appreciate that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A device structure, characterized in that: include: An interposer comprising a metal wiring structure and an optical waveguide embedded in an interlayer dielectric layer, wherein the interposer further comprises a stepped outer sidewall, the stepped outer sidewall comprising an outermost vertical surface segment, a laterally recessed sidewall segment laterally recessed relative to the outermost vertical surface segment, and a connecting horizontal surface segment connecting the outermost vertical surface segment and the laterally recessed sidewall segment; as well as A fiber access unit has a first end optically coupled to a subset of the optical waveguides via at least one optical adhesive portion disposed between the fiber access unit and the laterally recessed sidewall section of the stepped outer sidewall.

2. The device structure according to claim 1, characterized in that Also included is at least one semiconductor die attached to the metal wiring structure of the interposer.

3. The device structure according to claim 2, characterized in that: Also included is a mold compound die frame laterally surrounding the at least one semiconductor die, wherein the outermost vertical surface segment lies in a same vertical plane as a sidewall of the mold compound die frame.

4. The device structure according to claim 3, characterized in that: The at least one optical adhesive portion contacts a horizontal bottom surface section of the molding compound die frame and a bottom portion of the sidewall of the molding compound die frame.

5. The device structure according to any one of claims 2 to 4, characterized in that: One of the at least one semiconductor die includes an additional optical waveguide coupled to a subset of the optical waveguides in the interposer by evanescent coupling.

6. The device structure according to any one of claims 1 to 4, characterized in that: The lateral recess sidewall segment vertically extends from a topmost surface of the interlayer dielectric layer to at least a bottommost surface of the interlayer dielectric layer.

7. The device structure according to any one of claims 1 to 4, characterized in that: The at least one optical adhesive portion comprises: a first optical adhesive portion contacting the lateral recessed sidewall segment and having an outer sidewall in a vertical plane including the outermost vertical surface segment of the stepped outer sidewall; and A second optical adhesive portion contacts the first end of the optical fiber access unit and has an inner sidewall contacting the outer sidewall of the first optical adhesive portion.

8. The device structure according to any one of claims 1 to 4, characterized in that: The at least one optical adhesive portion includes a single optical adhesive portion having a homogeneous material composition and contacting the transverse recessed sidewall section and the first end of the optical fiber access unit.

9. A component, characterized in that include: A composite semiconductor package comprising an interposer and at least one semiconductor die attached to the interposer, wherein the interposer includes a metal wiring structure and an optical waveguide embedded in a dielectric layer, and the interposer further includes a stepped outer sidewall, the stepped outer sidewall including a first outermost vertical surface segment and a laterally recessed sidewall segment laterally recessed relative to the first outermost vertical surface segment; a molding compound; and A fiber access unit has a first end optically coupled to a subset of the optical waveguides via at least one optical adhesive portion disposed between the fiber access unit and the laterally recessed sidewall section of the stepped outer sidewall, wherein the sidewall of the at least one optical adhesive portion is aligned with the sidewall of the molding compound.

10. The assembly according to claim 9, wherein The stepped outer side wall comprises: a first connecting horizontal surface segment connecting an edge of the first outermost vertical surface segment to an edge of the transverse recessed sidewall segment; as well as A second outermost vertical surface section is connected to the transverse recessed sidewall section via a second connecting horizontal surface section.

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