Low-cost Hall chip surge electrostatic protection device
By designing a low-cost Hall chip surge electrostatic protection device and using current limiting resistors and feedback loops to protect Hall sensors, the problems of easy damage and high cost of Hall sensors are solved, and effective protection of static electricity and surge current is achieved, reducing the rework rate and production cost of motor products.
Patent Information
- Application Number
- CN202422454112.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-10-11
AI Technical Summary
Existing Hall sensors are prone to damage in the motor, especially the MOS switch tube part at the output, and the existing protection solutions are costly.
Design a low-cost Hall chip surge electrostatic protection device, including a circuit composed of Hall sensor, operational amplifier, NMOS and PMOS transistors, current limiting resistors and current sense resistors, to protect Hall chips through current limiting and feedback loops.
Effectively protect Hall chips from electrostatic shocks and transient surge currents, reduce product rework rate, improve product quality and reduce costs.
Smart Images
Figure CN223218836U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of circuit protection, in particular to a low-cost Hall chip surge electrostatic protection device. Background Art
[0002] Hall effect sensors are widely used in electric motors, primarily responsible for controlling the commutation process of the coil current and are a key component in motor control circuits. However, Hall effect sensors are also one of the most vulnerable components in motors, especially the MOS switches at the output. Currently, most electric vehicle motor Hall effect circuits use TVS diodes for energy suppression. However, this protection solution often results in higher overall circuit costs. Therefore, we are now designing a low-cost electrostatic surge protection device for Hall effect chips. Utility Model Content
[0003] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a low-cost Hall chip surge electrostatic protection device to enhance the circuit protection capability of the Hall chip circuit against electrostatic shock and transient surge current.
[0004] In order to achieve the above-mentioned purpose, a low-cost Hall chip surge electrostatic protection device is designed, comprising: a Hall sensor HALL; an operational amplifier U1; an NMOS transistor Q1; a PMOS transistor Q2; a current limiting resistor R1; a current detection resistor R2; and a MOS switch tube gate current limiting resistor R3; wherein, the output end of the Hall sensor HALL is connected to the positive input end of the operational amplifier U1; the output end of the operational amplifier U1 is connected to the gate of the NMOS transistor Q1; the source of the NMOS transistor Q1 is connected to the ground through the current detection resistor R2; the drain of the NMOS transistor Q1 is connected to the source of the PMOS transistor Q2 through the current limiting resistor R1; the drain of the PMOS transistor Q2 is connected to the positive pole of the power supply; and the gate of the PMOS transistor Q2 is connected to the connection point of the source of the NMOS transistor Q1 and the current detection resistor R2 through the MOS switch tube gate current limiting resistor R3.
[0005] Preferably, the low-cost Hall chip surge electrostatic protection device provided by the present invention also includes other technical features, including a diode D1; a voltage regulator REG; wherein the anode of the diode D1 is connected to the voltage regulator REG, and the cathode is connected to the positive pole of the power supply.
[0006] Preferably, the low-cost Hall chip surge electrostatic protection device provided by the present invention also includes other technical features, including a bias resistor R4; wherein the bias resistor R4 is connected between the positive pole of the power supply and other parts of the circuit.
[0007] Preferably, the low-cost Hall chip surge electrostatic protection device provided by the present invention also includes other technical features, wherein a feedback loop is formed between the negative input terminal and the output terminal of the operational amplifier U1.
[0008] Preferably, the low-cost Hall chip surge electrostatic protection device provided by the present invention also includes other technical features, wherein the connection point between the source of the PMOS transistor Q2 and the current limiting resistor R1 serves as the output end of the circuit.
[0009] Compared with the prior art, the utility model has the following advantages:
[0010] This utility model adopts a simple circuit design and has extremely low manufacturing costs, and can effectively protect the switching tube of the Hall chip. While providing protection, it will not affect the normal operating efficiency of the equipment. The addition of this circuit device can significantly enhance the protection against surge voltage. In surge voltage testing, according to this circuit design, the Hall chip can remain intact under test voltages up to 120 volts and can withstand electrostatic discharges exceeding 10,000 volts, greatly reducing the risk of motor scrapping due to damage to the Hall chip. This not only improves the overall quality of the product, but also reduces the product return rate. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 , is the connection diagram of this device;
[0012] In the figure: 1. Hall sensor, 2. Operational amplifier U1, 3. NMOS transistor Q1, 4. PMOS transistor Q2, 5. Current limiting resistor R1, 6. Current detection resistor R2, 7. Current limiting resistor R3, 8. Diode D1, 9. Voltage regulator REG, 10. TVS tube, 11. Bias resistor R4. DETAILED DESCRIPTION
[0013] In order to make the purpose, principle and structure of the present invention more clear, it is further described below with reference to the accompanying drawings and specific embodiments.
[0014] The utility model provides a low-cost Hall chip surge electrostatic protection device, comprising:
[0015] The main purpose of this device is to improve the protection against transient static electricity and surge current. For applications inside a motor, which is subject to various noises, a transient static electricity and surge absorption circuit is required to provide protection for the Hall effect circuit. The premise of transient surge current protection is that the instantaneous high voltage or noise interference exceeds the normal withstand voltage range of the internal NMOS transistor Q1 3. Transient high voltage protection refers to the protection circuit operating when the maximum withstand voltage between the drain and source of the NMOS transistor Q1 3 is exceeded. Figure 1A current-limiting resistor R15 is connected in series between the output terminal and the NMOS transistor Q13, and a TVS diode 10 is connected in parallel. When a large static or surge current enters, the parallel TVS diode 10 first clamps some of the energy. This current then flows through the current-limiting resistor R15, then through the NMOS transistor Q13, and into the current-sensing resistor R26, forming a current loop. Simultaneously, a large voltage is generated across the current-sensing resistor R25, which then flows through the MOS switch gate current-limiting resistor R37 to the gate of the PMOS transistor Q24. At this point, the PMOS transistor Q24 is not turned on. When there is no static or surge current, the chip operates normally, the voltage across the current-sensing resistor R26 is low, and the PMOS transistor Q24 turns on, short-circuiting the current-limiting resistor R15 and saving energy.
[0016] The output of the Hall sensor HALL 1 is connected to the positive input of the operational amplifier U1 2; the output of the operational amplifier U1 2 is connected to the gate of the NMOS transistor Q1 3; the source of the NMOS transistor Q1 3 is connected to ground via the current sensing resistor R2 6; the drain of the NMOS transistor Q1 3 is connected to the source of the PMOS transistor Q2 4 via the current limiting resistor R1 5; the drain of the PMOS transistor Q2 4 is connected to the positive power supply; and the gate of the PMOS transistor Q2 4 is connected to the junction of the source of the NMOS transistor Q1 3 and the current sensing resistor R2 6 via the MOS switch gate current limiting resistor R3 7. The anode of the diode D1 8 is connected to the voltage regulator REG 9, and the cathode is connected to the positive power supply. A bias resistor R4 11 is connected between the positive power supply and the rest of the circuit. A feedback loop is formed between the negative input of the operational amplifier U1 and its output. The connection point between the source of the PMOS transistor Q2 4 and the current limiting resistor R1 5 serves as the output end of the circuit.
[0017] The above description is only a specific implementation method of this utility model, but the protection scope of this utility model is not limited thereto. Any technician familiar with this technical field, within the technical scope disclosed by this utility model, can make equivalent substitutions or changes based on the technical solutions and new concepts of this utility model, which should be covered by the protection scope of this utility model.
Claims
1. A low-cost Hall chip surge electrostatic protection device, characterized in that: include Hall sensor HALL; Operational amplifier U1; NMOS transistor Q1; PMOS transistor Q2; Current limiting resistor R1; Current detection resistor R2; MOS switch tube gate current limiting resistor R3; in, The output end of the Hall sensor HALL is connected to the positive input end of the operational amplifier U1; The output terminal of the operational amplifier U1 is connected to the gate of the NMOS transistor Q1; The source of the NMOS transistor Q1 is connected to the ground through the current detection resistor R2; The drain of the NMOS transistor Q1 is connected to the source of the PMOS transistor Q2 through the current limiting resistor R1; The drain of the PMOS transistor Q2 is connected to the positive electrode of the power supply; The gate of the PMOS transistor Q2 is connected to the connection point between the source of the NMOS transistor Q1 and the current detection resistor R2 through the MOS switch gate current limiting resistor R3.
2. A low-cost Hall chip surge electrostatic protection device as claimed in claim 1, characterized in that: Also includes Diode D1; Voltage regulator REG; The anode of the diode D1 is connected to the voltage regulator REG, and the cathode is connected to the positive electrode of the power supply.
3. A low-cost Hall chip surge electrostatic protection device as claimed in claim 1, characterized in that: Also includes Bias resistor R4; The bias resistor R4 is connected between the positive electrode of the power supply and other parts of the circuit.
4. A low-cost Hall chip surge electrostatic protection device as claimed in claim 1, characterized in that: A feedback loop is formed between the negative input terminal of the operational amplifier U1 and its output terminal.
5. A low-cost Hall chip surge electrostatic protection device as claimed in claim 1, characterized in that: The connection point between the source of the PMOS transistor Q2 and the current limiting resistor R1 serves as the output end of the circuit.