Motor driving circuit and chip system

Abstract

The embodiment of the utility model provides a motor driving circuit and a chip system, and relates to the technical field of motor driving. In the motor driving circuit, to-be-merged pins of a motor driving chip are connected to branch ends of a signal merging unit, the merging ends of the signal merging unit are used for being connected with a microprocessor chip or a motor, the number of the merging ends of the merging unit is smaller than the number of the branch ends of the signal merging unit, the number of output signals of the motor driving chip is reduced, and the reliability of the motor driving chip is improved. And IO resources of a microprocessor chip or a motor are saved.

Description

Technical Field

[0001] The present application relates to the field of motor drive technology, and in particular to motor drive circuits and chip systems. Background Art

[0002] With the development of electronic information technology, electronic devices are developing rapidly in the direction of miniaturization, diversification of functions and complexity of systems; however, this is accompanied by complex systems that make the demand for IO interfaces between modules larger and larger.

[0003] Typically, each communication pin occupies one IO port. For example, a stepper motor driver chip has four motor monitoring signal pins and four synchronization signal input pins. If each communication pin occupies one IO port, eight IO ports are required. However, the number of IO ports in a system-on-chip (SoC) is fixed, which greatly consumes valuable IO resources.

[0004] How to design a motor drive circuit to save SoC IO resources is a technical problem to be solved in this application. Utility Model Content

[0005] The purpose of this application is to provide a motor drive circuit and chip system to solve the technical problem of how to design a motor drive circuit to save IO resources of SoC in the prior art.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides a motor drive circuit, comprising a motor drive chip and a signal merging unit, wherein at least two pins to be merged of the motor drive chip are connected to a branch end of the signal merging unit, and the merging end of the signal merging unit is used to connect a microprocessor chip or a motor, and the number of merging ends of the merging unit is less than the number of branch ends of the signal merging unit.

[0008] Optionally, the motor drive circuit further includes a plurality of first resistors;

[0009] Each of the pins to be merged is connected to a branch end of the signal merging unit via a different first resistor. The first resistor can play a role of current limiting and protection.

[0010] Optionally, the signal merging unit includes an OR gate chip, and each of the pins to be merged is connected to a different input end of the OR gate chip.

[0011] Optionally, the OR gate chip includes a plurality of dual-channel input OR gate chips;

[0012] The input end of each dual-channel input OR gate chip is connected to different pins to be merged.

[0013] Optionally, the signal combining unit includes a plurality of diodes and a second resistor;

[0014] Each of the pins to be merged is connected to the anode of a different diode;

[0015] The cathodes of all the diodes are connected to the first end of the second resistor and are used to connect to the microprocessor chip;

[0016] A second end of the second resistor is grounded.

[0017] Optionally, the pins to be merged include multiple groups, and the number of the signal merging units is multiple; the multiple signal merging units correspond one-to-one to the multiple groups of pins to be merged;

[0018] Each group of pins to be merged is connected to a different signal merging unit.

[0019] Optionally, the pins to be merged include a motor monitoring output pin group and a motor synchronization signal input pin group;

[0020] The signal merging unit includes a first signal merging unit and a second signal merging unit;

[0021] The motor monitoring output pin group is connected to the branch end of the first signal merging unit, and the merging end of the first signal merging unit is connected to the microprocessor chip;

[0022] The motor synchronization signal input pin group is connected to the branch end of the second signal merging unit, and the merging end of the second signal merging unit is connected to the motor.

[0023] Optionally, the motor driver chip is an MS41959 four-channel stepper motor driver chip.

[0024] Optionally, the pins to be merged of the MS41959 four-channel stepper motor driver chip include a motor monitoring output pin group and a motor synchronization signal input pin group;

[0025] The signal merging unit includes a first signal merging unit and a second signal merging unit;

[0026] The motor monitoring output pin group is connected to the branch end of the first signal merging unit, and the merging end of the first signal merging unit is connected to the microprocessor chip;

[0027] The motor synchronization signal input pin group is connected to the branch end of the second signal merging unit, and the merging end of the second signal merging unit is connected to the motor.

[0028] In a second aspect, an embodiment of the present application provides a chip system, which includes a microprocessor chip and the motor drive circuit of the first aspect, and the microprocessor chip is connected to at least one merging end of the signal merging unit.

[0029] Compared with the prior art, this application has the following beneficial effects:

[0030] In the motor drive circuit, the pin to be merged of the motor drive chip is connected to the branch end of the signal merging unit, and the merging end of the signal merging unit is used to connect to the microprocessor chip or the motor. The signal merging unit reduces the number of output signals of the motor drive chip and saves the IO resources of the microprocessor chip or the motor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram of a motor drive circuit provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram of a motor drive circuit including a first resistor provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a motor drive circuit in which a signal merging unit is implemented by multiple diodes according to an embodiment of the present application;

[0035] Figure 4 A schematic diagram of a motor drive circuit in which a signal merging unit is implemented by a second resistor and two diodes, provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of a motor drive circuit in which a signal merging unit is implemented by a second resistor and three diodes according to an embodiment of the present application;

[0037] Figure 6 A schematic diagram of a motor drive circuit in which a signal merging unit is implemented by an OR gate chip according to an embodiment of the present application;

[0038] Figure 7 A schematic diagram of a motor drive circuit using two dual-channel input OR gate chips provided in an embodiment of the present application;

[0039] Figure 8A schematic diagram of a motor drive circuit using three dual-channel input OR gate chips provided in an embodiment of the present application;

[0040] Figure 9 A schematic diagram of a motor drive circuit with a four-channel input OR gate chip provided in an embodiment of the present application;

[0041] Figure 10 A schematic diagram of a signal merging unit formed by a merged signal line and multiple branch signal lines provided in an embodiment of the present application;

[0042] Figure 11 A schematic diagram of a first resistor connected in series with a combined signal line provided in an embodiment of the present application;

[0043] Figure 12 A schematic diagram of a motor drive circuit with three groups of pins to be merged provided in an embodiment of the present application;

[0044] Figure 13 A schematic diagram of a motor drive circuit using the MS41959 chip as the motor drive chip is provided in an embodiment of the present application.

[0045] Description of reference numerals:

[0046] 1 Motor driver chip

[0047] 2 Signal merging unit

[0048] 3. First resistor

[0049] 4 diodes

[0050] 5. Second resistor

[0051] 6 OR gate chips

[0052] 7 dual-channel input OR gate chip

[0053] 8 four-channel input OR gate chip

[0054] 9 branch signal lines

[0055] 10 Merge signal lines DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. The described embodiments are part of the embodiments of the present application, but not all of the embodiments. Generally, the components of the embodiments of the present application described in the drawings herein can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is claimed, but rather merely represents selected embodiments of the present application. All other embodiments derived by persons of ordinary skill in the art based on the embodiments in this application without creative effort are intended to fall within the scope of protection of this application. The following embodiments and features therein may be combined with each other unless there is a conflict.

[0058] In the description of this application, it is necessary to explain:

[0059] Relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another entity or operation and do not necessarily require or imply any actual relationship or order between these entities or operations;

[0060] “Connection” should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0061] An existing stepper motor driver chip has multiple motor monitoring signal pins and multiple synchronization signal input pins. However, the number of IO ports in the system-on-chip (SoC) is fixed. If each communication pin occupies an IO port, a large number of IO ports will be occupied, consuming valuable IO resources.

[0062] To overcome the above problems, please refer to Figure 1 An embodiment of the present application provides a motor drive circuit, which includes a motor drive chip 1 and a signal merging unit 2, wherein at least two pins to be merged of the motor drive chip 1 are connected to a branch end of the signal merging unit 2.

[0063] The merging end of the signal merging unit 2 can be used to connect to a system-level chip or a microprocessor chip. The signal merging unit 2 plays the role of signal transmission between the motor driver chip 1 and the system-level chip, or between the motor driver chip 1 and the microprocessor chip.

[0064] The merging end of the signal merging unit 2 can also be used to connect to the motor, and the signal merging unit 2 can also play a role in signal transmission between the motor driving chip 1 and the motor.

[0065] The number of merging terminals of the merging unit is less than the number of branch terminals of the signal merging unit 2. Therefore, it is not necessary for each pin to be merged to occupy an IO port, and the number of required IO ports is less than the number of pins to be merged, saving IO resources.

[0066] like Figure 2The motor driving circuit may include a plurality of first resistors 3. The number of the first resistors 3 may be the same as the number of the pins to be combined of the motor driving chip 1.

[0067] The first resistor 3 is connected between the pin to be combined of the motor driver chip 1 and the branch end of the signal combining unit 2. Each pin to be combined is connected to the branch end of the signal combining unit 2 through a different first resistor 3. The first resistor 3 can play the role of current limiting and protection.

[0068] like Figure 3 The signal merging unit may include multiple diodes 4, and the number of diodes 4 may be the same as the pins to be merged of the motor driver chip 1.

[0069] Each of the pins to be merged is connected to the anode of a different diode 4; the cathodes of the plurality of diodes 4 are connected together, and the cathodes of the diodes 4 can be connected to a microprocessor chip.

[0070] The diode 4 can enable high-level signals to be transmitted in one direction, thereby forming a simple signal combining unit 2 .

[0071] like Figure 4 The signal merging unit may include a second resistor 5 and a plurality of diodes 4. The number of diodes 4 may be the same as the number of pins to be merged of the motor driver chip 1, and the number of second resistors 5 may be the same as the number of merging terminals of the signal merging unit 2.

[0072] Each pin to be combined is connected to the anode of a different diode 4. The cathodes of the plurality of diodes 4 are connected to the first end of the second resistor, and the connection point can be connected to the microprocessor chip. The second end of the second resistor is grounded.

[0073] The second resistor can release the charge to the ground in time when the pins to be combined all output a low level, thereby quickly reaching a low level state.

[0074] Figure 4 What is shown is an implementation method in which there are two pins to be merged, and two diodes 4 are provided accordingly. Figure 5 An implementation method is shown in which there are three pins to be merged, and three diodes 4 are correspondingly provided.

[0075] like Figure 6 , an OR gate chip 6 can be used as a component of the signal merging unit. Different input terminals of the OR gate chip 6 are connected to the pins to be merged.

[0076] The OR gate chip 6 can be a dual-channel input OR gate chip. When there are 4 pins to be merged that need to be merged into 2 IO ports, such as Figure 7, you can use two dual-channel input OR gate chips. Each dual-channel input OR gate chip combines two signals into one, and two dual-channel input OR gate chips combine four signals into two.

[0077] If a dual-channel input or gate chip is used and there are 4 pins to be merged into one IO port, Figure 8 , you can use three dual-channel input or gate chips, first use two dual-channel input or gate chips to merge 4 signals into 2, and then use one dual-channel input or gate chip to merge 2 signals into 1. At this time, you can replace the three dual-channel input or gate chips with one four-channel input or gate chip, such as Figure 9 , a four-channel input OR gate chip combines four signals into one.

[0078] When the signals do not interfere with each other, there is no need for an OR gate chip, such as Figure 10 The signal merging unit 2 may include a merged signal line and multiple branch signal lines, each pin to be merged is connected to a different branch signal line, and all branch signal lines are connected to the merged signal line. Figure 11 , the merged signal line can be connected in series with the first resistor 3.

[0079] The pins to be merged can include multiple groups, such as Figure 12 , Figure 12 The example shows a situation where there are three groups of pins to be merged. The number of signal merging units 2 is three. Multiple signal merging units 2 correspond one-to-one to multiple groups of pins to be merged. Each signal merging unit 2 merges the signals of one group of pins to be merged.

[0080] like Figure 13 Taking the MS41959 chip as the motor driver chip 1 as an example, the MS41959 chip is a four-channel stepper motor driver chip, which merges the four PLS signal ports of the MS4195 chip and merges the four VF signal ports of the MS4195 chip.

[0081] The PLS signal port is connected to the microprocessor chip, which transmits the motor monitoring signal to the microprocessor chip. Based on this signal and the preset timing, the microprocessor chip can obtain the operating status of each motor, such as whether each motor is running and how much it has rotated.

[0082] The VF signal port is connected to the synchronous signal port of the motor to receive the synchronous signal fed back by the motor. The MS4195 chip obtains the operating status of each motor based on the synchronous signal, such as whether each motor is running and how much it has rotated.

[0083] Since the four PLS signals can be set to be output at different times in the control, the PLS signal output ports can be merged into one; and the four VF signals can be input at the same time, the four VF signal ports can be directly merged into one port input.

[0084] The PLS signal port can be brought out on the circuit board and the PLS signal of the circuit board can be brought out to a four-channel input or gate chip, so that the four PLS signal ports become one output port. For the four VF signals, the four VF signal lines can be combined into one signal line for input.

[0085] visible, Figure 13 The motor drive circuit shown here reduces I / O usage by reducing the original eight I / O ports to two. This also simplifies layout and routing.

[0086] Based on the above embodiments, an embodiment of the present application further provides a chip system, which includes a microprocessor chip and the motor drive circuit of the first aspect, and the microprocessor chip is connected to at least one merging end of the signal merging unit.

[0087] In general, this application proposes a motor drive circuit and chip system. In the motor drive circuit, the pins to be merged of the motor drive chip are connected to the branch terminals of a signal merging unit. The merging terminals of the signal merging unit are used to connect to a microprocessor chip or a motor. The number of merging terminals of the merging unit is less than the number of branch terminals of the signal merging unit, thereby reducing the number of output signals of the motor drive chip and saving I / O resources of the microprocessor chip or the motor.

[0088] The above-described device and system embodiments are merely illustrative, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art may understand and implement the present invention without inventive effort.

[0089] The above are merely preferred embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A motor drive circuit, characterized in that: It includes a motor driving chip and a signal merging unit, at least two pins to be merged of the motor driving chip are connected to the branch end of the signal merging unit, the merging end of the signal merging unit is used to connect to a microprocessor chip or a motor, and the number of merging ends of the merging unit is less than the number of branch ends of the signal merging unit.

2. The motor drive circuit according to claim 1, wherein: The motor drive circuit further includes a plurality of first resistors; each of the pins to be merged is connected to a branch end of the signal merging unit via a different first resistor.

3. The motor drive circuit according to claim 1, wherein: The signal merging unit includes an OR gate chip, and each of the pins to be merged is connected to a different input end of the OR gate chip.

4. The motor drive circuit according to claim 3, wherein: The OR gate chip includes a plurality of dual-channel input OR gate chips; The input end of each dual-channel input OR gate chip is connected to different pins to be merged.

5. The motor drive circuit according to claim 1, wherein: The signal combining unit includes a second resistor and a plurality of diodes; Each of the pins to be merged is connected to the anode of a different diode; The cathodes of all the diodes are connected to the first end of the second resistor and are used to connect to the microprocessor chip; A second end of the second resistor is grounded.

6. The motor drive circuit according to claim 1, wherein: The pins to be merged include multiple groups, and the number of the signal merging units is multiple; the multiple signal merging units correspond one-to-one to the multiple groups of pins to be merged; Each group of pins to be merged is connected to a different signal merging unit.

7. The motor drive circuit according to claim 6, wherein: The pins to be merged include a motor monitoring output pin group and a motor synchronization signal input pin group; The signal merging unit includes a first signal merging unit and a second signal merging unit; The motor monitoring output pin group is connected to the branch end of the first signal merging unit, and the merging end of the first signal merging unit is connected to the microprocessor chip; The motor synchronization signal input pin group is connected to the branch end of the second signal merging unit, and the merging end of the second signal merging unit is connected to the motor.

8. The motor drive circuit according to claim 1, wherein: The motor driver chip is the MS41959 four-channel stepper motor driver chip.

9. The motor driving circuit according to claim 8, wherein: The pins to be merged include a motor monitoring output pin group and a motor synchronization signal input pin group; The signal merging unit includes a first signal merging unit and a second signal merging unit; The motor monitoring output pin group is connected to the branch end of the first signal merging unit, and the merging end of the first signal merging unit is connected to the microprocessor chip; The motor synchronization signal input pin group is connected to the branch end of the second signal merging unit, and the merging end of the second signal merging unit is connected to the motor.

10. A chip system, characterized in that: The chip system includes a microprocessor chip and the motor drive circuit according to any one of claims 1 to 9, and the microprocessor chip is connected to at least one merging end of the signal merging unit.

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