Miniaturized device for pulse power amplifier detection control

Abstract

The utility model relates to a miniaturized device for pulse power amplifier detection control, which belongs to the technical field of pulse power amplifier detection control device design and adopts a structure that three layers of plates are sequentially stacked, a first circuit board is a radio frequency and analog circuit board, a second circuit board is a processor circuit board, and a third circuit board is a power conversion circuit board. The first inner pin and the second inner pin form a connection structure of each circuit board, compared with a tiled circuit design in the prior art, the device structure is simplified, the device size is reduced, the overall firmness is ensured, interference is further shielded by packaging the device into a whole through the metal shell, the miniaturization design of the pulse power amplifier detection control device is realized, and the reliability of the device is improved. The problems that in the prior art, devices and circuits are complex in structural design and prone to interference, and miniaturization cannot be achieved are solved.

Description

Technical Field

[0001] The utility model relates to the technical field of pulse power amplifier detection and control device design, in particular to a miniaturized device used for pulse power amplifier detection and control. Background Art

[0002] Pulse power amplifiers are widely used in defense radar, weather radar, ranging radar, communications and other fields. In the existing technology, a control circuit with a flat layout is generally integrated into the pulse power amplifier to realize fault detection and control of the pulse power amplifier.

[0003] Due to the use of a tiled device layout, the existing pulse power amplifier control circuit has problems such as complex wiring, cumbersome cross-linking, and large space requirements. Moreover, the existing pulse power amplifier control circuit does not integrate a detection radio frequency circuit, which further increases the complexity of the circuit design and makes it susceptible to interference. Furthermore, due to the large size of the existing pulse power amplifier control circuit, the use of a metal shell shielding occupies a large space, further increasing the complexity and difficulty of the overall device layout of the pulse power amplifier. Utility Model Content

[0004] In view of the above analysis, the present invention aims to provide a miniaturized device for pulse power amplifier detection and control, so as to solve the problems of the existing design being complex, susceptible to interference and unable to be miniaturized.

[0005] The purpose of this utility model is mainly achieved through the following technical solutions:

[0006] A miniaturized device for detecting and controlling a pulsed power amplifier, the device comprising a first circuit board, a second circuit board, and a third circuit board stacked in sequence, wherein the first circuit board is a radio frequency and analog circuit board, the second circuit board is a processor circuit board, and the third circuit board is a power conversion circuit board; the first, second, and third circuit boards are of the same shape and size;

[0007] The first circuit board is provided with first pin holes at the left and right edges, and the second circuit board is provided with second pin holes at corresponding positions; one end of the lead pin is inserted into the first pin hole, and the other end is inserted into the second pin hole and fixed by welding to form a first inner pin;

[0008] The second circuit board is also provided with third pin holes on the four edges, and the third circuit board is provided with fourth pin holes at corresponding positions; one end of the lead pin is inserted into the third pin hole, and the other end passes through the fourth pin hole and is welded and fixed to form a second inner pin, and the lead pin is led out from the bottom of the third circuit board to form an outer pin.

[0009] The beneficial effects of the above scheme are as follows: a structure in which three layers of boards are stacked in sequence is adopted, the first circuit board is the RF and analog circuit board, the second circuit board is the processor circuit board, and the third circuit board is the power conversion circuit board, and the connection structure of each circuit board is formed by the first inner pin and the second inner pin. Compared with the flat circuit design of the prior art, the device structure is simplified, the device size is reduced, the overall strength is ensured, and it is easy to set a small-size metal shell to shield interference.

[0010] Based on a further improvement of the above solution, the top of the first circuit board is provided with a first RF signal interface, a first detection circuit, a first conditioning circuit, and a first peak holding circuit and a first high-speed comparison circuit connected to the first conditioning circuit in sequence; and is also provided with a second RF signal interface, a second detection circuit, a second conditioning circuit, and a second peak holding circuit and a second high-speed comparison circuit connected to the second conditioning circuit in sequence.

[0011] The beneficial effect of the above-mentioned further improvement scheme is that, compared with the existing technology, the radio frequency signal interface, detection circuit, conditioning circuit, peak hold circuit, and high-speed comparison circuit are all integrated on a single board, which simplifies the device structure and reduces possible interference.

[0012] Based on the further improvement of the above solution, a first reference voltage circuit and a second reference voltage circuit are also provided on the top of the first circuit board; the output end of the first reference voltage circuit is connected to the input end of the first high-speed comparison circuit; the output end of the second reference voltage circuit is connected to the input end of the second high-speed comparison circuit.

[0013] The beneficial effect of the above-mentioned further improvement scheme is: providing reference voltages for the first high-speed comparison circuit and the second high-speed comparison circuit respectively, which helps to form a more complete device structure and provides device structure support for achieving more reliable pulse power amplifier detection.

[0014] Based on a further improvement of the above solution, a processor chip is provided on the top of the second circuit board, and the processor chip is connected to the output end of the first peak holding circuit, the output end of the second peak holding circuit, the output end of the first high-speed comparison circuit, and the output end of the second high-speed comparison circuit through a first internal pin.

[0015] The beneficial effects of the above-mentioned further improvement scheme are: the use of the processor chip further simplifies the device structure and size of the second circuit board; the processor chip of the second circuit board, as well as the first and second peak holding circuit output ends, and the first and second high-speed comparison circuit output ends of the first circuit board are connected through the first inner pin, forming a simple inter-board device connection structure.

[0016] Based on a further improvement of the above solution, a power conversion circuit is provided on the top of the third circuit board, and the power conversion circuit is electrically connected to the second circuit board through the second inner pin, and is also electrically connected to the first circuit board through the second inner pin and the first inner pin.

[0017] The beneficial effect of the above-mentioned further improved scheme is: the third circuit board is provided with a power conversion circuit, and is electrically connected to the second circuit board through the second inner pin, and is electrically connected to the first circuit board through the second inner pin and the first inner pin to supply power to the second circuit board and the third circuit board.

[0018] Based on a further improvement of the above solution, the device also includes a metal shell and an upper cover, wherein the first circuit board and the second circuit board are arranged inside the metal shell; the upper cover fixedly covers the top opening of the metal shell; and the third circuit board fixedly covers the bottom opening of the metal shell.

[0019] The beneficial effects of the above-mentioned further improvement scheme are: ensuring the robustness of the overall structure of the device, and achieving electromagnetic shielding and anti-interference through the metal shell.

[0020] Based on the further improvement of the above solution, the length×width×height of the device after packaging is not greater than 52mm×52mm×16mm.

[0021] The beneficial effect of the above further improvement scheme is that the device is miniaturized.

[0022] Based on a further improvement of the above solution, a through hole corresponding to the position of the first radio frequency signal interface and the second radio frequency signal interface is provided on the left side of the housing.

[0023] The beneficial effects of the above-mentioned further improvement scheme are: facilitating the connection of radio frequency signal lines and reducing interference.

[0024] Based on the further improvement of the above solution, the second inner pins have 64 and are divided into 4 groups, among which:

[0025] The first group consists of 16 pieces, located on the left edge of the second circuit board;

[0026] The second group consists of 16 pieces, located at the lower edge of the second circuit board;

[0027] The third group consists of 16 pieces, located on the right edge of the second circuit board;

[0028] The fourth group of 16 pieces is located at the upper edge of the second circuit board.

[0029] The beneficial effects of the above-mentioned further improvement scheme are: the pin layout is reasonable, so that the overall structure of the device is stable, the area occupied on the board is small, and it is conducive to miniaturization of the device structure.

[0030] Based on the further improvement of the above solution, there are 9 first inner pins in total, which are divided into 4 groups, among which:

[0031] The first group includes two pins, located on the upper right side of the second inner pin on the left edge of the second circuit board;

[0032] The second group of 2 is located at the lower right side of the second inner pin on the left edge of the second circuit board;

[0033] The third group of three is located to the left of the second inner pin in the lower middle of the right edge of the second circuit board;

[0034] The second group includes two pieces, which are located at the left side of the second inner pin in the lower middle of the right edge of the second circuit board.

[0035] The beneficial effects of the above-mentioned further improvement scheme are: a small number of pins are used, the layout is reasonable, it helps to miniaturize the device structure, and the overall structure is stable.

[0036] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following content, and some advantages will become apparent from the description or be understood through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the text and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the accompanying drawings, the same reference symbols denote the same components.

[0038] Figure 1 This is a schematic diagram of the overall structure of the device in the embodiment of the utility model

[0039] Figure 2 This is a schematic diagram of the first circuit board component structure of the utility model embodiment

[0040] Figure 3 Schematic diagram of the conditioning circuit structure of the utility model embodiment

[0041] Figure 4 This is a schematic diagram of the peak holding circuit structure of the utility model embodiment

[0042] Figure 5 This is a schematic diagram of the high-speed comparison circuit structure with a reference voltage circuit according to an embodiment of the utility model.

[0043] Figure 6 This is a schematic diagram of the first inner pin layout of the first circuit board of the embodiment of the utility model

[0044] Figure 7 This is a schematic diagram of the second circuit board device structure of the utility model embodiment

[0045] Figure 8 This is a schematic diagram of the layout of the first and second inner pins of the second circuit board according to the embodiment of the utility model.

[0046] Figure 9 This is a schematic diagram of the second inner pin layout of the third circuit board according to the embodiment of the utility model. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0048] A specific embodiment of the present utility model discloses a miniaturized device for pulse power amplifier detection and control, such as Figure 1 The device comprises a first circuit board, a second circuit board, and a third circuit board stacked in sequence, wherein the first circuit board is a radio frequency and analog circuit board, the second circuit board is a processor circuit board, and the third circuit board is a power conversion circuit board; the first circuit board, the second circuit board, and the third circuit board have the same shape; and the first circuit board and the second circuit board have the same size;

[0049] The first circuit board is provided with first pin holes at the left and right edges, and the second circuit board is provided with second pin holes at corresponding positions; one end of the lead pin is inserted into the first pin hole, and the other end is inserted into the second pin hole and fixed by welding to form a first inner pin;

[0050] The second circuit board is also provided with third pin holes on the four edges, and the third circuit board is provided with fourth pin holes at corresponding positions; one end of the lead pin is inserted into the third pin hole, and the other end passes through the fourth pin hole and is welded and fixed to form a second inner pin, and the lead pin is led out from the bottom of the third circuit board to form an outer pin.

[0051] Compared with the prior art, this embodiment re-miniaturizes and modularizes the pulse power amplifier detection control circuit, adopts three-layer circuit boards stacked one on top of the other, and connects the boards through internal pins to form an overall structure.

[0052] Preferably, Figure 1The pin structures adopted by the first inner pin and the second inner pin are both gold-plated round-head pin headers with a plastic fixed structure wrapped in the middle part, wherein the gold-plated round-head pin header is a thin cylinder with a plastic cylinder wrapped in the middle part. The length of the plastic cylinder of the first inner pin is set to be equal to the spacing between the first and second circuit boards, and the length of the plastic cylinder of the second inner pin is set to be equal to the spacing between the second and third circuit boards. The plastic cylinder plays a supporting role between the boards, further strengthening the stability of the overall structure of the device.

[0053] Specifically, such as Figure 2 As shown, the top of the first circuit board is provided with a first RF signal interface, a first detection circuit, a first conditioning circuit, and a first peak holding circuit and a first high-speed comparison circuit connected to the first conditioning circuit in sequence; and is also provided with a second RF signal interface, a second detection circuit, a second conditioning circuit, and a second peak holding circuit and a second high-speed comparison circuit connected to the second conditioning circuit in sequence.

[0054] Specifically, the first RF signal interface is provided at an upper position on the left edge of the top of the first circuit board and is connected to the input end of the first detection circuit; the first detection circuit preferably adopts an AD8318 logarithmic detection chip, and the output end of the first detection circuit is connected to the input end of the first conditioning circuit; Figure 3 As shown, the first conditioning circuit includes a high-speed operational amplifier chip, and the preferred model of the high-speed operational amplifier chip is MS8242; the input end of the first peak holding circuit is connected to the output end of the first conditioning circuit, Figure 4 As shown in the preferred example of the first peak hold circuit, the first peak hold circuit includes two MS8242 high-speed operational amplifiers, one 1N4148 diode, one 2N7002 N-channel field effect transistor, one BZT52C3V3 voltage regulator diode, four 1K resistors, and two 1000pF capacitors; the output end of the first conditioning circuit is also connected to the input end of the first high-speed comparison circuit. Figure 5 As shown in a preferred example of the first high-speed comparison circuit, the first high-speed comparison circuit includes a high-speed comparator of model SGM8745, wherein the first conditioning circuit is connected to the first input terminal of the high-speed comparator through a resistor R5 with a resistance of 2K, the output terminal of the high-speed comparator is connected to one end of a resistor R7 with a resistance of 2K, and the other end of the resistor R7 is connected to the other end of a grounded resistor R8 with a resistance of 3K.

[0055] Further, such as Figure 2As shown, a first reference voltage circuit and a second reference voltage circuit are also provided on the top of the first circuit board; the output end of the first reference voltage circuit is connected to the input end of the first high-speed comparison circuit; the output end of the second reference voltage circuit is connected to the input end of the second high-speed comparison circuit.

[0056] Figure 5 The figure also shows a preferred embodiment that can be used for both the first reference voltage circuit and the second reference voltage circuit, which specifically includes a voltage source, a resistor R6 and a potentiometer RP1; the voltage source is connected to one end of a resistor R6 with a resistance of 2K, the other end of the resistor R6 and one end of the potentiometer RP1 are both connected to the second input end of the high-speed comparator, and the other end of the potentiometer RP1 is grounded. It can be understood that Figure 5 This is not a limitation on the implementation methods of the first reference voltage circuit and the second reference voltage circuit. Those skilled in the art may apply the preferred implementation method to the first reference voltage circuit and the second reference voltage circuit as needed, or apply other implementation methods, or apply the preferred implementation method and other implementation methods to the first reference voltage circuit and the second reference voltage circuit respectively.

[0057] The device layout and circuit structure of the first circuit board include a first RF signal interface, a first detection circuit, a first conditioning circuit, and a first peak hold circuit and a first high-speed comparison circuit connected to the first conditioning circuit, all connected in sequence. It also includes a second RF signal interface, a second detection circuit, a second conditioning circuit, and a second peak hold circuit and a second high-speed comparison circuit connected to the second conditioning circuit, all connected in sequence. It also includes a first reference voltage circuit and a second reference voltage circuit. The output of the first reference voltage circuit is connected to the input of the first high-speed comparison circuit, and the output of the second reference voltage circuit is connected to the input of the second high-speed comparison circuit. Compared to existing technologies, this circuit board not only integrates the detection circuit but also provides two identically structured devices and circuit connection structures for accessing RF signals, resulting in a simple structure, high integration, and effective avoidance of interference issues.

[0058] Further, such as Figure 6 Combine Figure 7 As shown, a processor chip is provided on the top of the second circuit board, and the processor chip is connected to the first peak holding circuit output end, the second peak holding circuit output end, the first high-speed comparison circuit output end, and the second high-speed comparison circuit output end through a first inner pin.

[0059] Preferably, the processor chip is preferably AGM32VF407VGT6, so that the second circuit board occupies less board space, the device layout is simpler, and miniaturization design is easy.

[0060] Furthermore, a power conversion circuit is provided on the top of the third circuit board. The power conversion circuit is electrically connected to the second circuit board through the second inner pin, and is also electrically connected to the first circuit board through the second inner pin and the first inner pin.

[0061] Specifically,

[0062] In this embodiment, first pin holes are provided on the left and right edges of the first circuit board, and second pin holes are provided at corresponding positions of the second circuit board; one end of the lead pin is inserted into the first pin hole, and the other end is inserted into the second pin hole and welded to form a first inner pin, and the first circuit board and the second circuit board are fixedly connected through the first inner pin.

[0063] Specifically, such as Figure 6 Combine Figure 8 As shown, there are 9 first inner pins in total, divided into 4 groups, among which,

[0064] The first group of 2 is located on the upper right side of the second inner pin on the left edge of the second circuit board, corresponding to Figure 8 Middle pins B1 and B2;

[0065] The second group of 2 is located at the lower right side of the second inner pin on the left edge of the second circuit board, corresponding to Figure 8 Middle pins B3 and B4;

[0066] The third group of 3 is located at the left side of the second inner pin in the lower middle of the right edge of the second circuit board, corresponding to Figure 8 Middle pins B8 and B9;

[0067] The second group of 2 is located at the left side of the second inner pin in the lower middle of the right edge of the second circuit board, corresponding to Figure 8 Middle pins B5, B6, B7.

[0068] The second circuit board is also provided with third pin holes at the edges thereof, and the third circuit board is provided with fourth pin holes at corresponding positions thereof. A lead pin is inserted into the third pin hole at one end and passed through the fourth pin hole at the other end, which is soldered and fixed to form a second inner pin. The lead pin is extended from the bottom of the third circuit board to form an outer pin. The second and third circuit boards are fixedly connected via the second inner pin.

[0069] Specifically, such as Figure 8 Combine Figure 9 As shown, the second inner pins have 64, divided into 4 groups, among which,

[0070] The first group of 16 is located on the left edge of the second circuit board, corresponding to Figure 8 Pins A1-A16, and Figure 9 center left edge pin;

[0071] The second group of 16 is located at the lower edge of the second circuit board, corresponding to Figure 8 Pins A17-A32, and Figure 9 Lower middle edge pin;

[0072] The third group of 16 is located on the right edge of the second circuit board, corresponding to Figure 8 Pins A33-A48, and Figure 9 middle right edge pin;

[0073] The fourth group of 16 is located on the upper edge of the second circuit board, corresponding to Figure 8 Pins A49-A64, and Figure 9 Upper middle edge pin.

[0074] The outer pin and the second inner pin correspond to each other in position on the third circuit board.

[0075] Preferably, the following table shows the first inner pin, second inner pin, outer pin number, logo and function definition. During specific implementation, those skilled in the art can directly apply the following table or freely define it according to application needs.

[0076]

[0077]

[0078] In this embodiment, the first circuit board, the second circuit board, and the third circuit board are stacked in sequence. The first circuit board and the second circuit board are fixedly connected by first inner pins, the second circuit board and the third circuit board are fixedly electrically connected by second inner pins, and the external pins are led outward from the bottom of the third circuit board. This overall structure not only reduces the number of pins but also ensures the stability of the overall structure.

[0079] Further, such as Figure 1 As shown, the device also includes a metal shell and an upper cover, wherein the first circuit board and the second circuit board are arranged inside the metal shell; the upper cover fixedly covers the top opening of the metal shell; and the third circuit board fixedly covers the bottom opening of the metal shell.

[0080] The metal shell not only plays a role in shielding electromagnetic interference, but also further stabilizes the overall structure of the device.

[0081] Figure 1 It also shows that the first reference voltage circuit and the second reference voltage circuit in this embodiment adopt Figure 5 In the preferred example implementation shown, the upper cover plate of the metal housing is further provided with a through hole, the position of the through hole corresponds to the potentiometer provided on the top of the first circuit board.

[0082] The left side of the housing is provided with through holes corresponding to the positions of the first RF signal interface and the second RF signal interface, which further reduces RF interference and simplifies the connection structure between the RF signal input and the device of this embodiment.

[0083] The device has a packaged length × width × height of no greater than 52 mm × 52 mm × 16 mm. This embodiment utilizes a structure in which the first, second, and third circuit boards are stacked, and the boards are connected via first and second inner pins, respectively. Furthermore, the structure includes a reasonable and concise device layout, high integration, and a metal housing package to achieve overall miniaturization of the device.

[0084] This solution adopts a structure in which three layers of boards are stacked in sequence. The first circuit board is the RF and analog circuit board, the second circuit board is the processor circuit board, and the third circuit board is the power conversion circuit board. The connection structure of each circuit board is formed by the first inner pin and the second inner pin. Compared with the flat circuit design of the existing technology, it simplifies the device structure, reduces the device size, ensures the overall strength, and further shields interference through metal shell packaging as a whole, realizing the miniaturization design of the pulse power amplifier detection and control device.

[0085] Those skilled in the art will appreciate that the programs / software involved in the above embodiments are common methods in the prior art, and the present invention does not involve any software improvements. The present invention merely requires connecting the various devices with corresponding functions through the connection relationships provided in the embodiments of the present invention, and does not involve any program or software improvements. As for the connection methods between the various hardware devices with corresponding functions, these can be implemented by those skilled in the art using existing technologies and will not be described in detail here.

[0086] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the protection scope of the present invention.

Claims

1. A miniaturized device for pulse power amplifier detection and control, characterized in that: The device includes a first circuit board, a second circuit board, and a third circuit board stacked in sequence, wherein the first circuit board is a radio frequency and analog circuit board, the second circuit board is a processor circuit board, and the third circuit board is a power conversion circuit board; the first circuit board, the second circuit board, and the third circuit board have the same shape; and the first circuit board and the second circuit board have the same size; The first circuit board is provided with first pin holes at the left and right edges, and the second circuit board is provided with second pin holes at corresponding positions; one end of the lead pin is inserted into the first pin hole, and the other end is inserted into the second pin hole and fixed by welding to form a first inner pin; The second circuit board is also provided with third pin holes on the four edges, and the third circuit board is provided with fourth pin holes at corresponding positions; one end of the lead pin is inserted into the third pin hole, and the other end passes through the fourth pin hole and is welded and fixed to form a second inner pin, and the lead pin is led out from the bottom of the third circuit board to form an outer pin.

2. A miniaturized device for pulse power amplifier detection and control according to claim 1, characterized in that: The top of the first circuit board is provided with a first radio frequency signal interface, a first detection circuit, a first conditioning circuit, and a first peak holding circuit and a first high-speed comparison circuit connected to the first conditioning circuit in sequence; the top of the first circuit board is also provided with a second radio frequency signal interface, a second detection circuit, a second conditioning circuit, and a second peak holding circuit and a second high-speed comparison circuit connected to the second conditioning circuit in sequence.

3. A miniaturized device for pulse power amplifier detection and control according to claim 2, characterized in that: A first reference voltage circuit and a second reference voltage circuit are also provided on the top of the first circuit board; the output end of the first reference voltage circuit is connected to the input end of the first high-speed comparison circuit; the output end of the second reference voltage circuit is connected to the input end of the second high-speed comparison circuit.

4. A miniaturized device for pulse power amplifier detection and control according to claim 2, characterized in that: A processor chip is provided on the top of the second circuit board, and the processor chip is connected to the first peak holding circuit output end, the second peak holding circuit output end, the first high-speed comparison circuit output end, and the second high-speed comparison circuit output end through a first inner pin.

5. The miniaturized device for pulse power amplifier detection and control according to claim 1, characterized in that: A power conversion circuit is provided on the top of the third circuit board. The power conversion circuit is electrically connected to the second circuit board through the second inner pin, and is also electrically connected to the first circuit board through the second inner pin and the first inner pin.

6. A miniaturized device for pulse power amplifier detection and control according to claim 2, characterized in that: The device also includes a metal shell and an upper cover, wherein the first circuit board and the second circuit board are arranged inside the metal shell; the upper cover fixedly covers the top opening of the metal shell; and the third circuit board fixedly covers the bottom opening of the metal shell.

7. A miniaturized device for pulse power amplifier detection and control according to claim 6, characterized in that: The length*width*height of the device after packaging is no greater than 52mm×52mm×16mm.

8. The miniaturized device for pulse power amplifier detection and control according to claim 6, characterized in that: A through hole corresponding to the position of the first radio frequency signal interface and the second radio frequency signal interface is provided on the left side of the shell.

9. The miniaturized device for pulse power amplifier detection and control according to claim 1, characterized in that: The second inner pins have 64, divided into 4 groups, among which, The first group consists of 16 pieces, located on the left edge of the second circuit board; The second group consists of 16 pieces, located at the lower edge of the second circuit board; The third group consists of 16 pieces, located on the right edge of the second circuit board; The fourth group of 16 pieces is located at the upper edge of the second circuit board.

10. A miniaturized device for pulse power amplifier detection and control according to claim 9, characterized in that: There are 9 first inner pins in total, divided into 4 groups, among which, The first group includes two pins, located on the upper right side of the second inner pin on the left edge of the second circuit board; The second group of 2 is located at the lower right side of the second inner pin on the left edge of the second circuit board; The third group of three is located to the left of the second inner pin in the lower middle of the right edge of the second circuit board; The second group includes two pieces, which are located at the left side of the second inner pin in the lower middle of the right edge of the second circuit board.

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