Semiconductor device

Abstract

The utility model provides a semiconductor device, comprising a semiconductor chilling plate which is provided with a cold end plate and a hot end plate which are oppositely arranged; the conductive metal layer comprises a first conductive region and a second conductive region which are arranged on the cold end plate at an interval; a first semiconductor chip disposed on the first conductive region and conductively connected to the first conductive region; the first power terminal is arranged on the first conductive region and is conductively connected with the first conductive region; the second power terminal is arranged on the second conductive region and is conductively connected with the second conductive region; and a first conductive connector connected between the second conductive region and the upper surface of the first semiconductor chip to conduct the first semiconductor chip and the second power terminal. According to the technical scheme of the invention, the problem that the heat dissipation performance is affected by the large thermal resistance between the chip and the radiator in the semiconductor device in the related technology can be effectively solved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device. Background Art

[0002] Power semiconductor modules are in increasing demand due to their ability to improve power conversion and transmission efficiency. They are primarily used for power conversion, such as changing voltage and frequency, converting AC to DC, and vice versa. They efficiently transmit renewable energy sources like solar and wind power to power stations or core converter stations for high-voltage DC transmission. Furthermore, power semiconductor modules are widely used in new energy vehicles, industrial control, locomotive traction, and other fields, playing an indispensable and significant role.

[0003] Heat generation in traditional soldered power semiconductor modules primarily stems from conduction losses when the chip is on and switching losses during the chip switching process. Furthermore, applications such as power grids may experience current overshoots when experiencing peak load fluctuations. Electric vehicles also experience varying degrees of current overshoot when traveling uphill. These short-duration current overshoots can rapidly heat the chip and module package, increasing chip junction temperature fluctuations and potentially even reaching or exceeding the maximum allowable junction temperature. These factors can lead to bond wire failure, copper layer separation on the copper-clad ceramic substrate, debonding, and solder layer failure, ultimately degrading the power module's heat dissipation, current flow, insulation, and chip performance. In severe cases, they can cause thermal breakdown within the module or even explosion. Currently, most commercial modules use air- or water-cooled heat sinks, whose heat dissipation output cannot scale with chip junction temperature. Furthermore, to provide mechanical support, current flow, and insulation, the chip and heat sink are separated by a multi-layer structure consisting of a copper-clad ceramic substrate, solder layer, and baseplate, resulting in significant thermal resistance between the chip and heat sink.

[0004] In recent years, semiconductor coolers have been increasingly used in various fields. In the power semiconductor field, some have attempted to leverage their advantages, such as adjustable heat dissipation power and compact size, to dissipate heat from power modules. However, these attempts have mostly used semiconductor coolers as heat sinks, without changing the thermal resistance between the chip and the cooler. This fails to fully utilize the advantages of semiconductor coolers, such as fast response time, wide temperature adjustment range, and the ability to adjust heat dissipation power according to changes in the chip's junction temperature. Utility Model Content

[0005] The main purpose of the present invention is to provide a semiconductor device to solve the problem in the related art that the thermal resistance between the chip and the heat sink in the semiconductor device affects the heat dissipation performance.

[0006] In order to achieve the above-mentioned purpose, the present invention provides a semiconductor device, including: a semiconductor refrigeration plate, having a cold end plate and a hot end plate arranged opposite to each other; a conductive metal layer, including a first conductive area and a second conductive area spaced apart on the cold end plate; a first semiconductor chip, arranged on the first conductive area and conductively connected to the first conductive area; a first power terminal, arranged on the first conductive area and conductively connected to the first conductive area; a second power terminal, arranged on the second conductive area and conductively connected to the second conductive area; a first conductive connector, connected between the second conductive area and the upper surface of the first semiconductor chip to conduct electricity between the first semiconductor chip and the second power terminal.

[0007] Furthermore, the semiconductor refrigeration plate also includes a refrigeration unit arranged between the cold end plate and the hot end plate, and the refrigeration unit includes a plurality of semiconductor cells arranged in series and a current input end and a current output end arranged at both ends of the plurality of semiconductor cells.

[0008] Furthermore, the semiconductor device also includes a second semiconductor chip, a third power terminal and a second conductive connector, the conductive metal layer also includes a third conductive area, the second semiconductor chip is arranged on the second conductive area and conductively connected to the second conductive area, the third power terminal is arranged on the third conductive area and conductively connected to the third conductive area, the second conductive connector is connected between the third conductive area and the upper surface of the second semiconductor chip to conduct the second semiconductor chip and the third power terminal, wherein the first power terminal and the third power terminal are DC terminals, and the second power terminal is an AC terminal.

[0009] Furthermore, the refrigeration unit includes a first subunit provided corresponding to the first semiconductor chip and a second subunit provided corresponding to the second semiconductor chip.

[0010] Furthermore, the semiconductor device includes a plurality of first semiconductor chips, and the cooling unit includes a plurality of third sub-units corresponding one-to-one to the plurality of first semiconductor chips.

[0011] Furthermore, the conductive metal layer also includes a fourth conductive area arranged on the cold end plate, and the semiconductor device also includes a control terminal and a third conductive connector, the control terminal is arranged on the fourth conductive area and conductively connected to the fourth conductive area, and the third conductive connector is connected between the fourth conductive area and the upper surface of the first semiconductor chip to conduct electricity between the first semiconductor chip and the control terminal.

[0012] Furthermore, the semiconductor device also includes a shell, which is arranged above the cold end plate. The conductive metal layer, the first semiconductor chip and the first conductive connector are all located in the shell, and the first power terminal and the second power terminal pass upwardly out of the shell.

[0013] Furthermore, the first power terminal includes a vertical plate section extending upward from the housing and a horizontal plate section arranged above the vertical plate section. A connecting hole is provided on the horizontal plate section, and a nut groove is provided on the upper surface of the housing, and the nut groove is located below the connecting hole.

[0014] Furthermore, the semiconductor device further includes an insulating colloid disposed in the housing, and an upper surface of the insulating colloid is higher than an upper surface of the first conductive connecting member.

[0015] Furthermore, the semiconductor device further includes a heat sink arranged below the hot end plate.

[0016] By applying the technical solution of the present invention, a conductive metal layer is directly provided on the cold end plate of the semiconductor refrigeration plate, and a first semiconductor chip, a first power terminal, and a second power terminal that generate a large amount of heat during operation are provided on the conductive metal layer. The multi-layer structure such as the copper-clad ceramic substrate and the bottom plate in the related art is omitted, so that there are no other heat-conducting components in the middle. This can effectively reduce the thermal resistance between the first semiconductor chip and the semiconductor refrigeration plate, the thermal resistance between the first power terminal and the semiconductor refrigeration plate, and the thermal resistance between the second power terminal and the semiconductor refrigeration plate. This can improve the heat dissipation effect of the first semiconductor chip, the first power terminal, and the second power terminal, and can avoid the occurrence of connection failure or thermal breakdown between the various components of the semiconductor device. Therefore, the technical solution of the present application can effectively solve the problem in the related art that the thermal resistance between the chip and the heat sink in the semiconductor device is large and affects the heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting part of this application are provided to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are provided to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0018] Figure 1 FIG1 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a first embodiment of the present invention;

[0019] Figure 2 Shown Figure 1 Schematic diagram of the exploded structure of a semiconductor device;

[0020] Figure 3 Shown Figure 1 A schematic three-dimensional structural diagram of a partial structure of a semiconductor device;

[0021] Figure 4 Shown Figure 3 A schematic side view of a semiconductor device with a hot end plate removed;

[0022] Figure 5 Shown Figure 4A bottom-view schematic diagram of a semiconductor device;

[0023] Figure 6 A schematic three-dimensional structure diagram showing a partial structure of a semiconductor device according to a second embodiment of the present invention;

[0024] Figure 7 Shown Figure 6 A bottom-view schematic diagram of a semiconductor device;

[0025] Figure 8 A schematic three-dimensional structure diagram showing a partial structure of a semiconductor device according to a third embodiment of the present invention;

[0026] Figure 9 Shown Figure 8 A bottom-up schematic diagram of a semiconductor device.

[0027] The above drawings include the following reference numerals:

[0028] 10. Semiconductor refrigeration chip; 11. Cold end plate; 12. Hot end plate; 13. Refrigeration unit; 131. Semiconductor cell; 132. Current input terminal; 133. Current output terminal; 134. First subunit; 135. Second subunit; 136. Third subunit;

[0029] 20. Conductive metal layer; 21. First conductive region; 22. Second conductive region; 23. Third conductive region; 24. Fourth conductive region;

[0030] 30. a first semiconductor chip;

[0031] 41. First power terminal; 411. Vertical plate section; 412. Horizontal plate section; 413. Connection hole; 42. Second power terminal; 43. Third power terminal; 44. Control terminal;

[0032] 51. First conductive connector; 52. Second conductive connector; 53. Third conductive connector;

[0033] 60. A second semiconductor chip;

[0034] 70. Housing; 71. Nut slot;

[0035] 80. Insulating colloid;

[0036] 90. Radiator;

[0037] 100. Thermal grease. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0040] Unless otherwise specifically stated, the relative arrangement of the parts and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to actual proportional relationships. The technology, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be considered as part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0041] like Figures 1 to 5As shown, the present application provides a semiconductor device. A first embodiment of the semiconductor device of the present application includes: a semiconductor refrigeration plate 10, a conductive metal layer 20, a first semiconductor chip 30, a first power terminal 41, a second power terminal 42, and a first conductive connector 51. The semiconductor refrigeration plate 10 includes a cold end plate 11 and a hot end plate 12 disposed opposite to each other; the conductive metal layer 20 includes a first conductive region 21 and a second conductive region 22 spaced apart on the cold end plate 11; the first semiconductor chip 30 is disposed on the first conductive region 21 and conductively connected to the first conductive region 21; the first power terminal 41 is disposed on the first conductive region 21 and conductively connected to the first conductive region 21; the second power terminal 42 is disposed on the second conductive region 22 and conductively connected to the second conductive region 22; and the first conductive connector 51 is connected between the second conductive region 22 and the upper surface of the first semiconductor chip 30 to conduct electricity between the first semiconductor chip 30 and the second power terminal 42.

[0042] The technical solution of this embodiment directly disposes a conductive metal layer 20 on the cold end plate 11 of the semiconductor refrigeration plate 10, and disposes the first semiconductor chip 30, which generates a large amount of heat during operation, and the first power terminal 41 and the second power terminal 42 on the conductive metal layer 20. This eliminates the multi-layer structure of the copper-clad ceramic substrate and the base plate in the related art, eliminating other heat-conducting components in the middle. This effectively reduces the thermal resistance between the first semiconductor chip 30 and the semiconductor refrigeration plate 10, the thermal resistance between the first power terminal 41 and the semiconductor refrigeration plate 10, and the thermal resistance between the second power terminal 42 and the semiconductor refrigeration plate 10. This improves the heat dissipation effect of the first semiconductor chip 30, the first power terminal 41, and the second power terminal 42, and avoids connection failure or thermal breakdown between the various components of the semiconductor device. Therefore, the technical solution of this embodiment effectively solves the problem of large thermal resistance between the chip and the heat sink in semiconductor devices in the related art, which affects the heat dissipation performance.

[0043] like Figures 3 to 5As shown, the semiconductor refrigeration plate 10 also includes a refrigeration unit 13 disposed between the cold end plate 11 and the hot end plate 12. The refrigeration unit 13 includes multiple semiconductor cells 131 arranged in series, and a current input terminal 132 and a current output terminal 133 disposed at both ends of the multiple semiconductor cells 131. Specifically, in this embodiment, both the cold end plate 11 and the hot end plate 12 are thermally conductive ceramic plates with excellent thermal conductivity, insulation, and high-temperature resistance, effectively cooling the first semiconductor chip 30, the first power terminal 41, and the second power terminal 42. The semiconductor cell 131 is the basic unit of the semiconductor refrigeration plate 10. It is a thermocouple pair composed of an N-type semiconductor, a P-type semiconductor, and a metal connecting plate. Multiple semiconductor cells 131 are connected in series through the metal connecting plate to form the refrigeration unit 13, which can improve cooling efficiency. The current input terminal 132 and the current output terminal 133 are provided at both ends of the structure formed by the multiple semiconductor cells 131 in series, respectively, to energize the refrigeration unit 13.

[0044] The cold end plate 11 made of a heat-conducting ceramic plate has the following functions:

[0045] 1. Provide electrical insulation to isolate the high-voltage part inside the semiconductor device from the low-voltage part outside such as the heat sink 90;

[0046] 2. Forming the main heat dissipation path for the first semiconductor chip 30. The semiconductor device of this embodiment has a single-sided heat dissipation structure. The heat generated by the first semiconductor chip 30 is conducted through the single-sided copper-clad cold end plate 11. The cold end plate 11 is made of a ceramic material with high thermal conductivity. Compared with the traditional soldered device structure, the design without a base plate and a copper-clad ceramic substrate reduces the thermal resistance of the heat dissipation path by 96%, reducing the process difficulty while improving reliability.

[0047] 3. Provide mechanical support by directly fixing the housing 70 by means of adhesive or the like. The mechanical support of the entire semiconductor device is provided by the single-sided copper-clad cold end plate 11 and the housing 70;

[0048] 4. Use the Peltier effect and Thomson effect to achieve intelligent control of heat dissipation power.

[0049] like Figure 3 As shown, the conductive metal layer 20 further includes a fourth conductive region 24 disposed on the cold end plate 11. The semiconductor device further includes a control terminal 44 and a third conductive connector 53. The control terminal 44 is disposed on and conductively connected to the fourth conductive region 24. The third conductive connector 53 is connected between the fourth conductive region 24 and the upper surface of the first semiconductor chip 30 to provide electrical connection between the first semiconductor chip 30 and the control terminal 44. The control terminal 44 is directly disposed on the fourth conductive region 24, which can effectively dissipate heat from the control terminal 44.

[0050] Specifically, the present application does not limit the type of the first semiconductor chip 30 . For example, the first semiconductor chip 30 may be an IGBT chip, a MOSFET chip, or a diode chip.

[0051] Taking the first semiconductor chip 30 as a MOSFET chip as an example, Figure 3 As shown, a drain is provided on the lower surface of the first semiconductor chip 30, and a source and a gate are provided on the upper surface. The first power terminal 41 is electrically connected to the drain of the first semiconductor chip 30 through the first conductive region 21, the second power terminal 42 is electrically connected to the source of the first semiconductor chip 30 through the first conductive connection 51, and the control terminal 44 is electrically connected to the gate of the first semiconductor chip 30 through the third conductive connection 53.

[0052] The conductive metal layer 20 is a copper layer structure provided on the outer surface of the cold end plate 11. The first conductive connector 51, the second conductive connector 52 and the third conductive connector 53 can be bonding wires or copper bridges, as long as they can achieve electrical connection between the corresponding structures.

[0053] Specifically, a copper layer can be formed on the cold end plate 11 through a direct copper cladding process or an active metal brazing (AMB) process, and then the copper layer is etched to form a corresponding required circuit layout to form the conductive metal layer 20. The first semiconductor chip 30, the first power terminal 41, the second power terminal 42, and the control terminal 44 are connected to the conductive metal layer 20 through welding, sintering, or terminal bonding. The source and gate of the first semiconductor chip 30 are electrically connected to the second conductive region 22 and the fourth conductive region 24, respectively, through bonding wires.

[0054] like Figure 1 and Figure 2 As shown, the semiconductor device further includes a housing 70, which is disposed above the cold end plate 11. The conductive metal layer 20, the first semiconductor chip 30, and the first conductive connector 51 are all located within the housing 70. The first power terminal 41 and the second power terminal 42 extend upwardly out of the housing 70. The housing 70 forms a protective shell that effectively protects the conductive metal layer 20, the first semiconductor chip 30, and the first conductive connector 51. The first power terminal 41 and the second power terminal 42 extend upwardly out of the housing 70 to achieve connection with external structures.

[0055] Specifically, the housing 70 is sealed and connected to the semiconductor cooling plate 10 through a frame gluing process.

[0056] like Figure 1 and Figure 3As shown, the first power terminal 41 includes a vertical plate section 411 extending upwardly from the housing 70 and a horizontal plate section 412 disposed above the vertical plate section 411. The horizontal plate section 412 is provided with a connection hole 413. A nut slot 71 is provided on the upper surface of the housing 70, and the nut slot 71 is located below the connection hole 413. The nut slot 71 can be used to accommodate a connection nut. When connecting the first power terminal 41 to an external structure, a screw extending through the connection hole 413, the connection nut, and the external structure can achieve a stable connection between the first power terminal 41 and the external structure. The structure of the second power terminal 42 is similar to that of the first power terminal 41 and will not be further described here.

[0057] The housing 70 includes a panel and an upper cover disposed at the upper end of the panel. A nut slot 71 is disposed on the upper cover, and the upper cover also includes a perforated structure for the first power terminal 41, the second power terminal 42, and the control terminal 44 to pass upward.

[0058] like Figure 2 As shown, the semiconductor device further includes an insulating gel 80 disposed in the housing 70 , and the upper surface of the insulating gel 80 is higher than the upper surface of the first conductive connection 51 .

[0059] like Figure 1 and Figure 2 As shown, the semiconductor device further includes a heat sink 90 disposed below the hot end plate 12. The heat sink 90 is connected to the hot end plate 12 and can conduct and dissipate the heat at the hot end plate 12 to ensure the heat dissipation power at the cold end plate 11. Figure 2 As shown, the semiconductor device further includes a thermal grease 100 disposed between the hot end plate 12 and the heat sink 90 .

[0060] Specifically, in this embodiment, the radiator 90 is a metal heat sink having a plurality of fins to increase the contact area with the air or other heat medium. Of course, in embodiments not shown in the figures, the radiator can also be a fan, a phase change heat sink, or other structures.

[0061] In this embodiment, a semiconductor refrigeration plate 10 with a copper-clad upper surface is used to replace the base plate, copper-clad ceramic plate and intermediate solder layer in the traditional semiconductor device package, so that there is only one solder layer and one conductive metal layer 20 between the first semiconductor chip 30 and the semiconductor refrigeration plate 10, thereby reducing the thermal resistance between the first semiconductor chip 30 and the semiconductor refrigeration plate 10, improving the heat dissipation power regulation response speed and heat dissipation efficiency, reducing the heat dissipation cost, and thereby improving the working performance and reliability of the semiconductor device.

[0062] The semiconductor device of this embodiment has the feature of fewer process steps, which can improve the packaging yield of the first semiconductor chip 30 while increasing the reliability and life of the semiconductor device and reducing the packaging cost and use cost of the semiconductor device.

[0063] Figure 6 and Figure 7 A structural diagram of part of the structure of the second embodiment of the semiconductor device according to the present application is shown. The following mainly describes the parts of the second embodiment that are different from the first embodiment, and the same parts of the two embodiments are not repeated.

[0064] In the first embodiment, the semiconductor device includes one first semiconductor chip 30 ; in the second embodiment, the semiconductor device includes two or more first semiconductor chips 30 .

[0065] Specifically, if Figure 6 and Figure 7 As shown, the semiconductor device includes a plurality of first semiconductor chips 30, and the cooling unit 13 includes a plurality of third sub-units 136 corresponding one to one with the plurality of first semiconductor chips 30. Providing a third sub-unit 136 for each first semiconductor chip 30 enables targeted heat dissipation control for each first semiconductor chip 30, resulting in a better heat dissipation effect.

[0066] Each third sub-unit 136 includes a plurality of semiconductor cells 131 , a current input terminal 132 and a current output terminal 133 .

[0067] In order to better dissipate heat for the first semiconductor chip 30 , a temperature sensor may be provided at each first semiconductor chip 30 , and the start and stop or current level of each third subunit 136 may be controlled according to detection data of the temperature sensor.

[0068] Of course, the above configuration will complicate the control of the semiconductor refrigeration plate 10. To simplify the control, the refrigeration unit may also include only one sub-unit that covers the entire lower surface of the cold end plate.

[0069] Figure 8 and Figure 9 A structural diagram of part of the structure of the third embodiment of the semiconductor device according to the present application is shown. The following mainly describes the parts of the third embodiment that are different from the first embodiment, and the same parts of the two embodiments are not repeated.

[0070] like Figure 8 and Figure 9As shown, the semiconductor device further includes a second semiconductor chip 60, a third power terminal 43, and a second conductive connector 52. The conductive metal layer 20 further includes a third conductive region 23. The second semiconductor chip 60 is disposed on and conductively connected to the second conductive region 22. The third power terminal 43 is disposed on and conductively connected to the third conductive region 23. The second conductive connector 52 is connected between the third conductive region 23 and the upper surface of the second semiconductor chip 60 to provide electrical connection between the second semiconductor chip 60 and the third power terminal 43. The first power terminal 41 and the third power terminal 43 are DC terminals, and the second power terminal 42 is an AC terminal. The above configuration enables a half-bridge topology connection.

[0071] Specifically, if Figure 8 As shown, in this embodiment, the conductive metal layer 20 includes two first conductive regions 21, two second conductive regions 22, and two third conductive regions 23. The two first conductive regions 21 are spaced apart along the length of the semiconductor device and connected by a copper bridge. The two second conductive regions 22 are spaced apart along the length of the semiconductor device and connected by a copper bridge. The two third conductive regions 23 are spaced apart along the length of the semiconductor device and connected by a copper bridge. Multiple first semiconductor chips 30 are arranged side by side on each of the two first conductive regions 21, and multiple second semiconductor chips 60 are arranged side by side on each of the two second conductive regions 22. There are two second power terminals 42.

[0072] like Figure 9 As shown, the cooling unit 13 includes a first subunit 134 corresponding to the first semiconductor chip 30 and a second subunit 135 corresponding to the second semiconductor chip 60. When the half-bridge topology circuit is operating, the first semiconductor chip 30 and the second semiconductor chip 60 are intermittently conductive. Therefore, the first subunit 134 and the second subunit 135 are provided for the first semiconductor chip 30 and the second semiconductor chip 60, respectively, to dissipate heat. This enables targeted heat dissipation control of the first semiconductor chip 30 and the second semiconductor chip 60, resulting in a better heat dissipation effect.

[0073] In the description of the present invention, it needs to be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0074] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0075] In addition, it should be noted that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this utility model.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor refrigeration plate (10) has a cold end plate (11) and a hot end plate (12) arranged opposite to each other; A conductive metal layer (20) comprising a first conductive area (21) and a second conductive area (22) spaced apart on the cold end plate (11); a first semiconductor chip (30) disposed on the first conductive region (21) and conductively connected to the first conductive region (21); a first power terminal (41), disposed on the first conductive area (21) and conductively connected to the first conductive area (21); a second power terminal (42), disposed on the second conductive area (22) and conductively connected to the second conductive area (22); A first conductive connection member (51) is connected between the second conductive area (22) and the upper surface of the first semiconductor chip (30) to conduct electricity between the first semiconductor chip (30) and the second power terminal (42).

2. The semiconductor device according to claim 1, wherein The semiconductor refrigeration plate (10) further includes a refrigeration unit (13) arranged between the cold end plate (11) and the hot end plate (12), wherein the refrigeration unit (13) includes a plurality of semiconductor cells (131) arranged in series and a current input end (132) and a current output end (133) arranged at both ends of the plurality of semiconductor cells (131).

3. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises a second semiconductor chip (60), a third power terminal (43) and a second conductive connector (52); the conductive metal layer (20) further comprises a third conductive region (23); the second semiconductor chip (60) is arranged on the second conductive region (22) and is conductively connected to the second conductive region (22); the third power terminal (43) is arranged on the third conductive region (23) and is conductively connected to the third conductive region (23); the second conductive connector (52) is connected between the third conductive region (23) and the upper surface of the second semiconductor chip (60) to conduct the second semiconductor chip (60) and the third power terminal (43); wherein the first power terminal (41) and the third power terminal (43) are DC terminals, and the second power terminal (42) is an AC terminal.

4. The semiconductor device according to claim 3, wherein The refrigeration unit (13) includes a first subunit (134) arranged corresponding to the first semiconductor chip (30) and a second subunit (135) arranged corresponding to the second semiconductor chip (60).

5. The semiconductor device according to claim 2, wherein The semiconductor device includes a plurality of the first semiconductor chips (30), and the refrigeration unit (13) includes a plurality of third sub-units (136) corresponding one-to-one to the plurality of the first semiconductor chips (30).

6. The semiconductor device according to any one of claims 1 to 5, wherein: The conductive metal layer (20) further includes a fourth conductive area (24) arranged on the cold end plate (11), and the semiconductor device further includes a control terminal (44) and a third conductive connector (53), wherein the control terminal (44) is arranged on the fourth conductive area (24) and conductively connected to the fourth conductive area (24), and the third conductive connector (53) is connected between the fourth conductive area (24) and the upper surface of the first semiconductor chip (30) to conduct electricity between the first semiconductor chip (30) and the control terminal (44).

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The semiconductor device further comprises a housing (70), wherein the housing (70) is arranged above the cold end plate (11); the conductive metal layer (20), the first semiconductor chip (30) and the first conductive connector (51) are all located within the housing (70); and the first power terminal (41) and the second power terminal (42) extend upwardly out of the housing (70).

8. The semiconductor device according to claim 7, wherein: The first power terminal (41) comprises a vertical plate section (411) extending upwardly out of the housing (70) and a horizontal plate section (412) arranged above the vertical plate section (411); a connecting hole (413) is provided on the horizontal plate section (412); a nut groove (71) is provided on the upper surface of the housing (70); and the nut groove (71) is located below the connecting hole (413).

9. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises an insulating colloid (80) arranged in the housing (70), and the upper surface of the insulating colloid (80) is higher than the upper surface of the first conductive connecting member (51).

10. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor device further includes a heat sink (90) disposed below the hot end plate (12).

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