Adapter plate and packaging structure

Abstract

The utility model discloses an adapter plate and a packaging structure. The adapter plate comprises a first capacitor structure and a second capacitor structure which are arranged on a substrate; the first capacitor structure and the second capacitor structure respectively comprise a plurality of electrode layers and inter-electrode dielectric layers located between every two adjacent electrode layers, and every two adjacent electrode layers and the corresponding inter-electrode dielectric layers form a sub-capacitor; the first capacitor structure comprises a plurality of first sub-capacitors which are connected in parallel; the second capacitor structure comprises a plurality of second sub-capacitors which are connected in series, and every two adjacent electrode layers in the lower electrode layer, the upper electrode layer and the at least one middle electrode layer of the second capacitor structure and the corresponding inter-electrode dielectric layer form a second sub-capacitor; the multiple electrode layers and the multiple inter-electrode dielectric layers of the first capacitor structure and the multiple electrode layers and the multiple inter-electrode dielectric layers of the second capacitor structure are arranged on the same layer, the capacitance of the first capacitor structure is larger than that of the second capacitor structure, and the working voltage of the second capacitor structure is higher than that of the first capacitor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to an adapter board and a packaging structure. Background Art

[0002] In the semiconductor packaging field and other technical fields, interposers, as intermediate connecting components, are widely used in various semiconductor packages. Within these packages, capacitors can be incorporated into the interposer to address power supply noise. The capacitance of a capacitor is closely related to its ability to mitigate power supply noise. Furthermore, capacitors must operate at an appropriate operating voltage to avoid failure due to excessive voltage. Ensuring that the capacitors in the interposer meet both capacitance and operating voltage requirements is a key research topic in this field. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a transfer board is provided, comprising: a substrate; and a first capacitor structure and a second capacitor structure, which are arranged on the substrate and each include multiple electrode layers and an inter-electrode dielectric layer located between each adjacent two electrode layers, wherein each adjacent two electrode layers and the corresponding inter-electrode dielectric layer constitute a sub-capacitor; wherein the first capacitor structure includes multiple first sub-capacitors connected in parallel with each other; the second capacitor structure includes multiple second sub-capacitors connected in series with each other, and includes a lower electrode layer, an upper electrode layer and at least one intermediate electrode layer, the at least one intermediate electrode layer is located between the lower electrode layer and the upper electrode layer, and each adjacent two electrode layers in the lower electrode layer, the upper electrode layer and the at least one intermediate electrode layer and the corresponding inter-electrode dielectric layer constitute a second sub-capacitor; the multiple electrode layers and the multiple inter-electrode dielectric layers of the first capacitor structure are respectively arranged on the same layer as the multiple electrode layers and the multiple inter-electrode dielectric layers of the second capacitor structure, and the capacitance of the first capacitor structure is greater than the capacitance of the second capacitor structure, and the operating voltage of the second capacitor structure is higher than the operating voltage of the first capacitor structure.

[0004] In the adapter board provided according to at least one embodiment of the present disclosure, in the second capacitor structure, the lower electrode layer is configured to be connected to a first power supply voltage, the upper electrode layer is configured to be connected to a second power supply voltage, and the at least one intermediate electrode layer is each configured to be electrically floating or connected to an intermediate power supply voltage; and the first power supply voltage is different from the second power supply voltage, and the intermediate power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

[0005] In the adapter board provided according to at least one embodiment of the present disclosure, the at least one intermediate electrode layer includes multiple intermediate electrode layers, the multiple intermediate electrode layers are respectively connected to multiple intermediate power supply voltages, and the multiple intermediate power supply voltages increase or decrease in sequence between the first power supply voltage and the second power supply voltage.

[0006] In the adapter board provided according to at least one embodiment of the present disclosure, the second capacitor structure further includes one or more additional electrode layers, which are located on a side of the lower electrode layer away from the upper electrode layer and / or a side of the upper electrode layer away from the lower electrode layer.

[0007] In the adapter board provided according to at least one embodiment of the present disclosure, the one or more additional electrode layers and the lower electrode layer or every two adjacent electrode layers in the lower electrode layer form a third sub-capacitor, and the third sub-capacitor is connected in parallel with the multiple second sub-capacitors.

[0008] In the adapter board provided according to at least one embodiment of the present disclosure, the one or more additional electrode layers are electrically floating or connected to an additional power supply voltage, and the additional power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

[0009] In the adapter board provided according to at least one embodiment of the present disclosure, among the multiple electrode layers of the first capacitor structure, every two adjacent electrode layers are connected to different power supply voltages, and every two electrode layers separated by one electrode layer are connected to the same power supply voltage.

[0010] In the adapter board provided according to at least one embodiment of the present disclosure, in the first sub-capacitor and the second sub-capacitor arranged in the same layer in the first capacitor structure and the second capacitor structure, the inter-electrode dielectric layer of the first sub-capacitor and the inter-electrode dielectric layer of the second sub-capacitor have the same thickness, and the relative area between the two electrode layers in the first sub-capacitor is the same as the relative area between the two electrode layers in the second sub-capacitor.

[0011] In the adapter board provided according to at least one embodiment of the present disclosure, the second capacitor structure includes a first electrode layer, a second electrode layer and a third electrode layer arranged in sequence, and the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, and the at least one intermediate electrode layer is the second electrode layer.

[0012] In the adapter board provided according to at least one embodiment of the present disclosure, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer arranged in sequence, the first electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, and the at least one intermediate electrode layer includes the second electrode layer and the third electrode layer.

[0013] In the adapter board provided according to at least one embodiment of the present disclosure, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer arranged in sequence; wherein the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the second electrode layer, and the fourth electrode layer is an additional electrode layer; or the second electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the third electrode layer, and the first electrode layer is an additional electrode layer, wherein the additional electrode layer is electrically floating or connected to an additional power supply voltage, and the additional power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

[0014] In the adapter board provided according to at least one embodiment of the present disclosure, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer and a fifth electrode layer arranged in sequence, wherein the first electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, and the at least one intermediate electrode layer includes the second electrode layer, the third electrode layer and the fourth electrode layer.

[0015] According to at least one embodiment of the present disclosure, in the adapter board provided, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer and a fifth electrode layer arranged in sequence, wherein the first electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer includes the second electrode layer and the third electrode layer, and the fifth electrode layer serves as an additional electrode layer; or the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the second electrode layer, and the fourth electrode layer and the fifth electrode layer serve as additional electrode layers; or the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the second electrode layer, and the fourth electrode layer and the fifth electrode layer serve as additional electrode layers; The second electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, the at least one intermediate electrode layer includes the third electrode layer and the fourth electrode layer, and the first electrode layer is an additional electrode layer; or the second electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the third electrode layer, and the first electrode layer and the fifth electrode layer are additional electrode layers; or the third electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the fourth electrode layer, and the first electrode layer and the second electrode layer are additional electrode layers.

[0016] In the adapter board provided according to at least one embodiment of the present disclosure, the additional electrode layers are each electrically floating or connected to an additional power supply voltage, and the additional power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

[0017] In the adapter board provided according to at least one embodiment of the present disclosure, the electric field directions of every two adjacent first sub-capacitors in the multiple sub-capacitors of the first capacitor structure are opposite; and the electric field directions of at least two sub-capacitors in the multiple sub-capacitors of the second capacitor structure are the same.

[0018] In the adapter board provided according to at least one embodiment of the present disclosure, the substrate is a semiconductor substrate, the first capacitor structure and the second capacitor structure are deep trench capacitors, and each has a portion embedded in the substrate.

[0019] The adapter board provided according to at least one embodiment of the present disclosure further includes: an interconnection structure, which is arranged on one side of the semiconductor substrate and includes a conductive component electrically connected to the corresponding electrode layers of the first capacitor structure and the second capacitor structure; and a substrate through-hole, which is embedded in the semiconductor substrate and electrically connected to the interconnection structure.

[0020] According to at least one embodiment of the present disclosure, a packaging structure is provided, comprising an adapter board as described above; a chip module, which is arranged on one side of the adapter board, and a plurality of chips in the chip module are interconnected with each other through the adapter board; and a packaging substrate, which is arranged on a side of the adapter board away from the chip module and is electrically connected to the chip module through the adapter board. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0022] Figure 1 A schematic cross-sectional view of an adapter plate according to some embodiments of the present disclosure is shown.

[0023] Figure 2 A schematic plan view of an adapter plate according to some embodiments of the present disclosure is shown.

[0024] Figure 3A A schematic diagram illustrating connecting a first capacitor structure in a transfer board to a power supply voltage according to some embodiments of the present disclosure is shown.

[0025] Figure 3B A schematic diagram illustrating connecting a second capacitor structure in a transfer board to a power supply voltage according to some embodiments of the present disclosure is shown.

[0026] Figures 4A to 4C A schematic enlarged cross-sectional view of a second capacitor structure in an adapter board according to some embodiments of the present disclosure is shown.

[0027] Figures 5A to 5F Schematic enlarged cross-sectional views of the second capacitor structure in the adapter board according to some other embodiments of the present disclosure are shown.

[0028] Figure 6 A schematic cross-sectional view of a first capacitor structure in an adapter board according to some embodiments of the present disclosure is shown.

[0029] Figure 7 Schematic cross-sectional views of the first capacitor structure in the adapter board according to some other embodiments of the present disclosure are shown.

[0030] Figure 8 A schematic cross-sectional view illustrating a package structure according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0031] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0033] In interposers such as silicon interposers, power supply noise issues can be mitigated or resolved by installing capacitors (e.g., deep trench capacitors). Generally speaking, the larger the capacitance of a capacitor, the smaller its capacitive reactance, which helps reduce the impedance of the electrical path in which it is located, thereby reducing power supply noise. The capacitance of a capacitor is positively correlated with the relative area of the capacitor plates and negatively correlated with the inter-electrode distance between the capacitor plates. Therefore, in order to better reduce power supply noise, the inter-electrode distance between the electrode plates can be set smaller, thereby forming a higher-density capacitor, thereby increasing the capacitance of the capacitor.

[0034] On the other hand, the operating voltage of a capacitor is generally positively correlated with the inter-electrode distance between the electrode plates. For example, to achieve a higher operating voltage, the operating voltage can be increased by increasing the inter-electrode distance to form a lower-density capacitor. However, higher-density, high-capacity capacitors and lower-density, higher-operating-voltage capacitors require different manufacturing processes.

[0035] Under the same process platform, it may be difficult for the capacitors of the adapter board to simultaneously meet the requirements of high capacitance and high operating voltage.

[0036] Based on the above, the embodiments of the present disclosure provide a transfer board that can have capacitors that meet high capacitance requirements and capacitors that meet high operating voltage requirements under the same process platform.

[0037] For example, the adapter plate of the embodiment of the present disclosure has a first capacitor unit area and a second capacitor unit area, and includes: a substrate; and a first capacitor structure and a second capacitor structure, which are arranged on the substrate and are respectively located in the first capacitor unit area and the second capacitor unit area, and each includes multiple electrode layers and an inter-electrode dielectric layer located between each adjacent two electrode layers, wherein each adjacent two electrode layers and the corresponding inter-electrode dielectric layer constitute a sub-capacitor; wherein the first capacitor structure includes multiple first sub-capacitors connected in parallel with each other; the second capacitor structure includes multiple second sub-capacitors connected in series with each other, and includes a lower electrode layer, an upper electrode layer and at least one intermediate electrode layer, the at least one intermediate electrode layer is located between the lower electrode layer and the upper electrode layer, and each adjacent two electrode layers in the lower electrode layer, the upper electrode layer and the at least one intermediate electrode layer and the corresponding inter-electrode dielectric layer constitute a second sub-capacitor; the multiple electrode layers and the multiple inter-electrode dielectric layers of the first capacitor structure are respectively arranged in the same layer as the multiple electrode layers and the multiple inter-electrode dielectric layers of the second capacitor structure, and the capacitance of the first capacitor structure is greater than the capacitance of the second capacitor structure, and the operating voltage of the second capacitor structure is higher than the operating voltage of the first capacitor structure.

[0038] In the adapter board of the embodiment of the present disclosure, the multiple electrode layers and the multiple inter-electrode dielectric layers of the first capacitor structure are respectively arranged in the same layer as the multiple electrode layers and the multiple inter-electrode dielectric layers of the second capacitor structure, that is, they can be formed under the same process platform; moreover, the multiple first sub-capacitors in the first capacitor structure are connected in parallel with each other, and the multiple second sub-capacitors in the second capacitor structure are connected in series with each other, so that the capacitance of the first capacitor structure is greater than that of the capacitor of the second capacitor structure to meet the capacitance requirement of high capacitance, and the operating voltage of the second capacitor structure is higher than that of the first capacitor structure to meet the capacitance requirement of high operating voltage. In other words, the present disclosure can simultaneously meet the capacitance requirements of high capacitance and high operating voltage under the same process platform.

[0039] Figure 1 A schematic cross-sectional view of an adapter plate according to some embodiments of the present disclosure is shown.

[0040] refer to Figure 1In some embodiments, the adapter plate 200 has a first capacitor unit area R1 and a second capacitor unit area R2, and includes a substrate 100, a first capacitor structure CS1, and a second capacitor structure CS2. The first capacitor structure CS1 and the second capacitor structure CS2 are located on the substrate 100, and are respectively located in the first capacitor unit area R1 and the second capacitor unit area R2, and each includes a plurality of electrode layers and an inter-electrode dielectric layer located between each two adjacent electrode layers, wherein each two adjacent electrode layers and the inter-electrode dielectric layer located between the two adjacent electrode layers constitute a sub-capacitor. In this article, the capacitor structure being located on the substrate includes the capacitor structure being located on the main surface of the substrate and / or at least a portion of the capacitor structure being embedded in the substrate.

[0041] In some embodiments, multiple sub-capacitors of the first capacitor structure CS1 are connected in parallel to increase the overall capacitance of the first capacitor structure CS1; for example, the first capacitor structure CS1 may include multiple first sub-capacitors C1 connected in parallel. In some embodiments, at least two of the multiple sub-capacitors of the second capacitor structure CS2 are connected in series to increase the overall operating voltage of the second capacitor structure CS2. For example, the second capacitor structure CS2 includes multiple second sub-capacitors C2 connected in series. In some embodiments, the second capacitor structure CS2 includes a lower electrode layer Eb, an upper electrode layer Et, and at least one intermediate electrode layer Em located between the lower electrode layer Eb and the upper electrode layer Et. Each adjacent two electrode layers among the lower electrode layer Eb, the upper electrode layer Et, and the at least one intermediate electrode layer Em constitute a second sub-capacitor C2.

[0042] In some embodiments, the plurality of electrode layers of the first capacitor structure CS1 are respectively arranged in the same layer as the plurality of electrode layers of the second capacitor structure CS2, and the plurality of inter-electrode dielectric layers of the first capacitor structure CS1 are respectively arranged in the same layer as the plurality of inter-electrode dielectric layers of the second capacitor structure CS2. In this article, the plurality of component layers are arranged in the same layer means that these component layers are formed from the same material layer using the same process platform, such as using the same formation process (for example, the same deposition or plating and / or patterning process) or using the same mask. For example, the first capacitor structure CS1 and the second capacitor structure CS2 are formed simultaneously using the same semiconductor process under the same process platform. For example, each layer (electrode layer or inter-electrode dielectric layer) of the first capacitor structure is formed from the same material layer using the same mask as the corresponding layer (electrode layer or inter-electrode dielectric layer) of the second capacitor structure.

[0043] In some embodiments, the capacitance of the first capacitor structure CS1 is greater than the capacitance of the second capacitor structure CS2, and the operating voltage of the second capacitor structure CS2 is higher than the operating voltage of the first capacitor structure CS1, so that capacitors that meet high capacitance requirements and capacitors that meet high operating voltage requirements are available on the same process platform. For example, in some embodiments, the capacitance of the first capacitor structure CS1 is greater than or equal to 500nF / mm 2 , for example, up to 1000nf / mm 2 The capacitance of the second capacitor structure CS2 may be less than 500nf / mm 2 ; For example, the operating voltage of the first capacitor structure CS1 may be less than or equal to 1.5V or less than or equal to 1.6V, for example, it may be in the range of about 0.5V to 1.5V, or it may be in the range of about 0.5V to 1.6V; and the operating voltage of the second capacitor structure CS2 may be greater than or equal to 1.8V, or it may be greater than or equal to 1.7V. It should be understood that the capacitance of each capacitor structure refers to the capacitance of the overall capacitor formed by its multiple sub-capacitors connected in series and / or in parallel; the operating voltage of the capacitor structure refers to the operating voltage of the overall capacitor formed by the multiple capacitors in the capacitor structure connected in series and / or in parallel. In this document, A and / or B includes at least one of A and B, that is, includes A; B; or A and B.

[0044] For example, each of the first capacitor structure CS1 and the second capacitor structure CS2 includes a first electrode layer 101 , a second electrode layer 102 , and a third electrode layer 103 arranged in sequence, and an inter-electrode dielectric layer 90 located between every two adjacent electrode layers.

[0045] For example, in the first capacitor structure CS1, the first electrode layer 101, the second electrode layer 102, and the inter-electrode dielectric layer 90 therebetween collectively constitute a first sub-capacitor C1. The second electrode layer 102, the third electrode layer 103, and the inter-electrode dielectric layer 90 therebetween collectively constitute a first sub-capacitor C1. The multiple first sub-capacitors C1 of the first capacitor structure CS1 are connected in parallel, and two adjacent first sub-capacitors C1 may share an electrode plate (e.g., the second electrode layer 102).

[0046] For example, in the second capacitor structure CS2, the first electrode layer 101, the second electrode layer 102, and the third electrode layer 103 serve as the lower electrode layer Eb, the middle electrode layer Em, and the upper electrode layer Et, respectively. The first electrode layer 101, the second electrode layer 102, and the inter-electrode dielectric layer 90 therebetween collectively constitute a second sub-capacitor C2. The second electrode layer 102, the third electrode layer 103, and the inter-electrode dielectric layer 90 therebetween collectively constitute a second sub-capacitor C2. The multiple second sub-capacitors C2 of the second capacitor structure CS2 are connected in series, and two adjacent second sub-capacitors C2 may share a common electrode plate (e.g., the second electrode layer 102).

[0047] For example, the first electrode layer 101 of the first capacitor structure CS1 and the first electrode layer 101 of the second capacitor structure CS2 can be formed from the same electrode material layer through the same patterning process; each inter-electrode dielectric layer 90 in the first capacitor structure CS1 and the corresponding inter-electrode dielectric layer 90 in the second capacitor structure CS2 can be formed from the same dielectric material layer through the same deposition process and / or patterning process, and can have the same thickness; and so on, the other electrode layers of the two capacitor structures are also arranged in the same layer.

[0048] The corresponding electrode layers in the first capacitor structure and the second capacitor structure are electrically isolated from each other; the dielectric layers between the electrodes of the first capacitor structure and the second capacitor structure may be disconnected or not disconnected from each other.

[0049] In some embodiments, in the second capacitor structure, the lower electrode layer is configured to be connected to a first power supply voltage, the upper electrode layer is configured to be connected to a second power supply voltage, and the at least one intermediate electrode layer is each configured to be electrically floating or connected to an intermediate power supply voltage; and the first power supply voltage is different from the second power supply voltage, the intermediate power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

[0050] In some embodiments, among the multiple electrode layers of the first capacitor structure, every two adjacent electrode layers are connected to different power supply voltages, and every two electrode layers separated by one electrode layer are connected to the same power supply voltage.

[0051] Figure 3A A schematic diagram schematically showing the connection of multiple electrode layers of a first capacitor structure to a power supply voltage; Figure 3B A schematic diagram schematically shows the connection of multiple electrode layers of the second capacitor structure to the power supply voltage. Figure 3A and Figure 3B The arrows in the figure schematically show the direction of the electric field of each sub-capacitor.

[0052] For example, Figure 1 and Figure 3BAs shown, in the second capacitor structure CS2, the first electrode layer 101 serves as the lower electrode layer Eb, connected to the first power supply voltage PV1; the third electrode layer 103 serves as the upper electrode layer Et, connected to the second power supply voltage PV2; and the second electrode layer 102 serves as the middle electrode layer Em, and can be configured to be electrically floating or connected to the middle power supply voltage PV3. For example, the first power supply voltage is VSS and the second power supply voltage is VDD, or vice versa. Figure 3B The intermediate power supply voltage PV3 is shown in dashed lines to indicate that the intermediate power supply voltage may be set or may not be set (ie, the intermediate electrode layer is electrically floating).

[0053] When the middle electrode layer Em is electrically floating, since the middle electrode layer Em is close to the upper electrode layer Et and / or the lower electrode layer Eb, and the upper electrode layer Et and the lower electrode layer Eb are each connected to a corresponding power supply voltage, the charge in the middle electrode layer Em will be redistributed due to electrostatic induction, and an induced electric field will be generated between the middle electrode layer and the upper electrode layer, between the middle electrode layer and the lower electrode layer, and (in the case of multiple middle electrode layers) between adjacent middle electrode layers; in this case, every two adjacent electrode layers in these electrode layers can form a second sub-capacitor, and the electric field directions of the multiple second sub-capacitors are the same. For example, in Figure 1 and Figure 3B In the example shown, with the second power supply voltage PV2 being VDD and the first power supply voltage PV1 being VSS, a voltage difference exists between the lower electrode layer Eb and the upper electrode layer Et. The lower electrode layer Eb (e.g., the first electrode layer 101) is negatively charged, while the upper electrode layer Ea (e.g., the third electrode layer 103) is positively charged. Due to electrostatic induction, the side of the middle electrode layer Em (e.g., the second electrode layer 102) closest to the lower electrode layer Eb is positively charged, while the side of the middle electrode layer Em closest to the upper electrode layer Et is negatively charged. Consequently, two second sub-capacitors are connected in series, and the direction of the electric field in the second sub-capacitor formed by the middle electrode layer Em and the lower electrode layer Eb is the same as the direction of the electric field in the second sub-capacitor formed by the middle electrode layer Em and the upper electrode layer Et. In some embodiments, electrically floating the middle electrode layer can simplify the design and manufacture of conductive circuits.

[0054] When the middle electrode layer Em is connected to the intermediate power supply voltage PV3, the intermediate power supply voltage PV3 is greater than one of the first power supply voltage PV1 and the second power supply voltage PV2, and less than the other of the first power supply voltage PV1 and the second power supply voltage PV2. That is, the first power supply voltage, the intermediate power supply voltage, and the second power supply voltage increase or decrease in sequence. For example, when one of the first power supply voltage and the second power supply voltage is VSS, and the other of the first power supply voltage and the second power supply voltage is VDD, the intermediate power supply voltage is a power supply voltage greater than VSS and less than VDD. In this way, the direction of the electric field generated between the middle electrode layer and the upper electrode layer is the same as the direction of the electric field between the middle electrode layer and the lower electrode layer. In some embodiments, the voltage difference across each second sub-capacitor can be substantially the same; for example, in this example, the voltage difference between the first power supply voltage PV1 and the intermediate power supply voltage PV3 can be substantially the same as the voltage difference between the second power supply voltage PV2 and the intermediate power supply voltage PV3. In some embodiments, connecting the middle electrode layer to the intermediate power supply voltage can achieve more uniform voltage distribution across each sub-capacitor, for example, allowing each sub-capacitor to more evenly and stably share the operating voltage of the overall capacitor.

[0055] refer to Figure 1 and Figure 3B In the second capacitor structure CS2, multiple second sub-capacitors C2 are connected in series. The voltage across the lower electrode layer Eb and the upper electrode layer Et in the second capacitor structure CS2 (for example, the difference between the first power supply voltage and the second power supply voltage) is shared by the multiple second sub-capacitors C2, thereby increasing the operating voltage of the entire capacitor structure. For example, the overall operating voltage of the multiple second sub-capacitors connected in series is approximately equal to the sum of the divided voltages WV2 of each second sub-capacitor.

[0056] refer to Figure 1 and Figure 3A In some embodiments, every two adjacent electrode layers in the first capacitor structure CS1 are connected to different power supply voltages, and every two electrode layers separated by one electrode layer are connected to the same power supply voltage; every two electrode layers separated by one electrode layer means that there is another electrode layer between the two electrode layers. For example, the first capacitor structure CS1 includes m electrode layers stacked in sequence, and the odd-numbered electrode layers of the m electrode layers are all connected to a first power supply voltage, and the even-numbered electrode layers of the m electrode layers are all connected to a second power supply voltage, and the first power supply voltage and the second power supply voltage are different. For example, one of the first power supply voltage and the second power supply voltage is VSS, and the other of the first power supply voltage and the second power supply voltage is VDD.

[0057] For example, in the first capacitor structure CS1, the first electrode layer 101 and the third electrode layer 103 are connected to the same first additional power supply voltage PV01, and the second electrode layer 102 is connected to another second additional power supply voltage PV02; for example, the first electrode layer 101 and the third electrode layer 103 are connected to VSS, and the second electrode layer 102 is connected to VDD. In this way, the first sub-capacitor C1 formed by the first electrode layer 101 and the second electrode layer 102 and the first sub-capacitor C1 formed by the second electrode layer 102 and the third electrode layer 103 are connected in parallel. The overall capacitance of the first capacitor structure CS1 is approximately equal to the sum of the capacitances of the multiple first sub-capacitors C1 connected in parallel, thereby increasing the overall capacitance of the capacitor structure. The electric fields of adjacent first sub-capacitors C1 are directed in opposite directions. The operating voltage of the overall capacitance of the multiple first sub-capacitors C1 connected in parallel is approximately the same as the voltage WV1 across each first sub-capacitor C1.

[0058] Under the same process platform, multiple second sub-capacitors are connected in series in the second capacitor structure to increase the operating voltage of the overall capacitor structure; multiple first sub-capacitors are connected in parallel in the first capacitor structure to increase the capacitance of the overall capacitor structure.

[0059] In some embodiments, in the first sub-capacitor and the second sub-capacitor disposed in the same layer in the first capacitor structure and the second capacitor structure, the inter-electrode dielectric layer of the first sub-capacitor and the inter-electrode dielectric layer of the second sub-capacitor have the same thickness, and the relative area between the two electrode layers in the first sub-capacitor is the same as the relative area between the two electrode layers in the second sub-capacitor. Here, the first sub-capacitor and the second sub-capacitor being disposed in the same layer means that the two electrode layers of the first sub-capacitor are respectively disposed in the same layer as the two electrode layers of the second sub-capacitor, and the inter-electrode dielectric layer of the first sub-capacitor and the inter-electrode dielectric layer of the second sub-capacitor are disposed in the same layer.

[0060] For example, the relative area between the first electrode layer 101 and the second electrode layer 102 in the first capacitor structure CS1 is approximately equal to the relative area between the first electrode layer 101 and the second electrode layer 102 in the second capacitor structure CS2, and the thickness of the inter-electrode dielectric layer 90 in the first capacitor structure CS1 is approximately equal to the thickness of the inter-electrode dielectric layer 90 in the second capacitor structure CS2. Other sub-capacitors arranged in the same layer of the first capacitor structure CS1 and the second capacitor structure CS2 also have similar characteristics. In this way, the manufacturing process of the first capacitor structure and the second capacitor structure can be simplified, saving manufacturing costs; for example, the first capacitor structure and the second capacitor structure can be formed using the same patterning process or using the same mask.

[0061] In some embodiments, the first capacitor structure CS1 and the second capacitor structure CS2 can be connected to corresponding power supply voltages via conductive members in an interposer. For example, the interposer 200 can be a silicon-based interposer; the power supply voltage can be provided by a package substrate and / or a circuit board disposed on one side of the interposer.

[0062] Figure 2 A schematic top view of multiple electrode layers and conductive vias of the first capacitor structure and the second capacitor structure in the adapter plate is schematically shown, which shows the positional relationship of the orthographic projections of the multiple electrode layers and the corresponding conductive vias on the main surface of the substrate.

[0063] refer to Figure 1 and Figure 2 In some embodiments, the first electrode layer 101, the second electrode layer 102 and the third electrode layer 103 are arranged at intervals in a direction perpendicular to the main surface of the substrate and overlap with each other; each two adjacent electrode layers are opposite to each other, and the lower electrode layer has an end portion extending beyond the electrode layer above it in a direction parallel to the main surface of the substrate for electrical connection with the corresponding conductive through hole.

[0064] For example, in the first capacitor structure CS1, the end portion of the first electrode layer 101 extends beyond the edge of the second electrode layer 102 in a direction parallel to the main surface of the substrate and is electrically connected to one or more first conductive vias V1; the end portion of the second electrode layer 102 extends beyond the edge of the third electrode layer 103 in a direction parallel to the main surface of the substrate and is electrically connected to one or more first conductive vias V1; the third electrode layer 103 is electrically connected to one or more first conductive vias V1.

[0065] The first electrode layer 101 and the third electrode layer 103 are connected to the same first conductive line 111 through a plurality of first conductive vias V1, and thus can be electrically connected to each other through the first conductive line 111. The second electrode layer 102 is connected to the second conductive line 112 through the first conductive vias V1.

[0066] In some embodiments, an interconnect structure 150 is disposed above substrate 100. Interconnect structure 150 includes a dielectric structure 110 and a plurality of conductive members embedded in dielectric structure 110. The plurality of conductive members include conductive traces connected to the respective capacitor structures and may also include conductive traces (not shown) for inter-chip interconnection. In some embodiments, substrate 100 is further provided with a plurality of conductive vias 83. The plurality of conductive vias 83 extend through substrate 100 and are used to provide electrical connections between the conductive members in interconnect structure 150 and external components (e.g., a package substrate connected to an interposer).

[0067] For example, in the first capacitor structure CS1, the first electrode layer 101 and the third electrode layer 103 are electrically connected to the corresponding first conductive through-holes 83a through multiple first conductive through-holes V1 and the first conductive line 111, and can then be connected to the corresponding power supply voltage through the first conductive through-holes 83a; the second electrode layer 102 is electrically connected to the corresponding second conductive through-holes 83b through the first conductive through-holes V1 and the second conductive line 112, and can then be connected to the corresponding power supply voltage through the second conductive through-holes 83b.

[0068] For example, in the second capacitor structure CS2, the first electrode layer 101 is connected to the third conductive circuit 121 and the third conductive through-hole 83c through the second conductive through-hole V2, and can be connected to the first power supply voltage through these conductive components; the third electrode layer 103 is connected to the fourth conductive circuit 123 and the fourth conductive through-hole 83d through the second conductive through-hole V2, and can be connected to the second power supply voltage through these conductive components.

[0069] Figure 1 In the example shown, each capacitor structure includes three electrode layers, and the second capacitor structure includes one intermediate electrode layer, but the present disclosure is not limited thereto. In other embodiments, each capacitor structure includes more than three electrode layers, and the second capacitor structure may include one or more intermediate electrode layers.

[0070] In some embodiments, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer arranged in sequence, the first electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, and the at least one intermediate electrode layer includes the second electrode layer and the third electrode layer.

[0071] In some embodiments, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer arranged in sequence; wherein the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the second electrode layer, and the fourth electrode layer is an additional electrode layer; or the second electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the third electrode layer, and the first electrode layer is an additional electrode layer, wherein the additional electrode layer is electrically floating or connected to an additional power supply voltage, and the additional power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

[0072] In some embodiments, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer and a fifth electrode layer arranged in sequence, wherein the first electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, and the at least one intermediate electrode layer includes the second electrode layer, the third electrode layer and the fourth electrode layer.

[0073] In some embodiments, the second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer and a fifth electrode layer arranged in sequence, wherein the first electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer includes the second electrode layer and the third electrode layer, and the fifth electrode layer serves as an additional electrode layer; or the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the second electrode layer, the fourth electrode layer and the fifth electrode layer serve as additional electrode layers; or the second electrode layer is The lower electrode layer, the fifth electrode layer is the upper electrode layer, the at least one intermediate electrode layer includes the third electrode layer and the fourth electrode layer, and the first electrode layer is an additional electrode layer; or the second electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the third electrode layer, and the first electrode layer and the fifth electrode layer are additional electrode layers; or the third electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the fourth electrode layer, and the first electrode layer and the second electrode layer are additional electrode layers.

[0074] For example, each of the additional electrode layers is electrically floating or connected to an additional power supply voltage, which is greater than one of the first power supply voltage and the second power supply voltage and less than the other of the first power supply voltage and the second power supply voltage.

[0075] For example, Figures 4A to 4C FIG. 4 shows an embodiment in which the second capacitor structure CS2 includes four electrode layers. Figures 5A to 5F An embodiment is shown in which the second capacitor structure CS2 includes five electrode layers. Figures 4A to 4C as well as Figures 5A to 5F The enlarged view of the second capacitor structure CS2 is shown, but the substrate and the first capacitor structure are not shown. It should be understood that except for the different number of electrode layers of the capacitor structure, the other features of the substrate and the first capacitor structure and the second capacitor structure are the same. Figure 1 Similar to what is shown.

[0076] refer to Figures 4A to 4CIn some embodiments, the second capacitor structure CS2 includes a first electrode layer 101, a second electrode layer 102, a third electrode layer 103 and a fourth electrode layer 104 arranged in sequence and spaced apart in a direction perpendicular to the main surface of the substrate, and an inter-electrode dielectric layer 90 is provided between each two adjacent electrode layers.

[0077] refer to Figures 5A to 5F In some embodiments, the second capacitor structure CS2 includes a first electrode layer 101, a second electrode layer 102, a third electrode layer 103, a fourth electrode layer 104 and a fifth electrode layer 105 arranged in sequence and spaced apart in a direction perpendicular to the main surface of the substrate, and an inter-electrode dielectric layer 90 is provided between each two adjacent electrode layers.

[0078] When the second capacitor structure CS2 includes three or more electrode layers, at least two sub-capacitors among the multiple sub-capacitors of the second capacitor structure are connected in series with each other; for example, all the sub-capacitors of the second capacitor structure are connected in series with each other; or some of the sub-capacitors of the second capacitor structure are connected in series with each other, and another part of the sub-capacitors can be connected in parallel with the aforementioned part of the sub-capacitors, thereby relatively increasing the capacitance of the capacitor structure while increasing the operating voltage of the capacitor structure.

[0079] For example, in some embodiments, the electrode layer closest to the substrate in the second capacitor structure CS2 serves as the lower electrode layer, while the electrode layer farthest from the substrate serves as the upper electrode layer, and all electrode layers between the upper and lower electrode layers serve as intermediate electrode layers. In this case, all sub-capacitors of the second capacitor structure are connected in series, which can maximize the operating voltage of the entire capacitor structure.

[0080] For example, reference Figure 4A In an embodiment in which the second capacitor structure CS2 includes four electrode layers, the first electrode layer 101 serves as a lower electrode layer Eb and is connected to the first power supply voltage PV1, for example, it can be connected to the first power supply voltage PV1 through a conductive member such as a second conductive via V2; the fourth electrode layer 104 serves as an upper electrode layer Et and is connected to the second power supply voltage PV2, for example, it can be connected to the second power supply voltage PV2 through a conductive member such as a second conductive via V2; it should be understood that Figure 4A The subsequent figures only schematically show the connection between the corresponding electrode layers and the first power supply voltage and the second power supply voltage, and do not indicate that the first power supply voltage terminal and the second power supply voltage terminal are directly arranged on the corresponding conductive through-holes; for the sake of simplicity of the figures, the conductive components between each conductive through-hole and the corresponding power supply voltage are not specifically shown.

[0081] For example, the second electrode layer 102 and the third electrode layer 103 are both intermediate electrode layers Em, and each may be electrically floating or connected to an intermediate power supply voltage (not shown). The intermediate power supply voltage is greater than one of the first power supply voltage PV1 and the second power supply voltage PV2, and less than the other of the first power supply voltage PV1 and the second power supply voltage PV2. For example, one of the first power supply voltage PV1 and the second power supply voltage PV2 is VSS, the other of the first power supply voltage PV1 and the second power supply voltage PV2 is VDD, and the intermediate power supply voltage may be the other power supply voltage greater than VSS and less than VDD.

[0082] For example, reference Figure 5A In an embodiment where the second capacitor structure CS2 includes five electrode layers, the first electrode layer 101 serves as a lower electrode layer Eb and is connected to a first power supply voltage PV1; the fifth electrode layer 105 serves as an upper electrode layer Et and is connected to a second power supply voltage PV2, for example, by a conductive member such as a second conductive via V2; the second electrode layer 102, the third electrode layer 103, and the fourth electrode layer 104 serve as intermediate electrode layers Em, and each of the intermediate electrode layers 102, 103, and 104 may be electrically floating or connected to a corresponding intermediate power supply voltage, where the intermediate power supply voltage is between the first power supply voltage PV1 and the second power supply voltage PV2, i.e., a power supply voltage greater than one of the first power supply voltage and less than the other of the first power supply voltage and the second power supply voltage. For example, one of the first power supply voltage PV1 and the second power supply voltage PV2 is VSS, and the other of the first power supply voltage PV1 and the second power supply voltage PV2 is VDD, and the intermediate power supply voltage may be the other power supply voltage greater than VSS and less than VDD. It should be understood that in the case of multiple intermediate electrode layers, the multiple intermediate electrode layers may all be electrically floating, or all connected to a corresponding intermediate power supply voltage, or some intermediate electrode layers may be electrically floating while other intermediate electrode layers may be connected to the intermediate power supply voltage.

[0083] In some implementations, the at least one intermediate electrode layer of the second capacitor structure includes multiple intermediate electrode layers, and the multiple intermediate connection layers are respectively connected to multiple intermediate power supply voltages, and the multiple intermediate power supply voltages are sequentially increasing or decreasing between the first power supply voltage and the second power supply voltage. In this way, it is ensured that the multiple sub-capacitors in the second capacitor structure are connected in series and the electric fields of the multiple sub-capacitors are in the same direction.

[0084] For example, in Figure 4AIn the illustrated embodiment, if both the second electrode layer 102 and the third electrode layer 103 are connected to an intermediate power supply voltage, the second electrode layer 102 is connected to a first intermediate power supply voltage, and the third electrode layer 103 is connected to a second intermediate power supply voltage that is different from the first intermediate power supply voltage. For example, if the first power supply voltage is VSS and the second power supply voltage is VDD, then the first intermediate power supply voltage and the second intermediate power supply voltage increase sequentially between VSS and VDD. That is, the first intermediate power supply voltage is greater than VSS and less than the second intermediate power supply voltage, and the second intermediate power supply voltage is greater than the first intermediate power supply voltage and less than VDD. In some embodiments, the voltage differences across the multiple sub-capacitors in the second capacitor structure can be substantially equal, so that each sub-capacitor can more stably and evenly share the overall voltage across the capacitor structure.

[0085] For example, in Figure 5A In the illustrated embodiment, when the second to fourth electrode layers 102 to 104 are all connected to an intermediate power supply voltage, these electrode layers are connected to different intermediate power supply voltages, and the intermediate power supply voltages connected to the second, third, and fourth electrode layers 102, 103, and 104 are sequentially decreasing or increasing. For example, the second electrode layer 102 is connected to a first intermediate power supply voltage, the third electrode layer 103 is connected to a second intermediate power supply voltage, and the fourth electrode layer 104 is connected to a third intermediate power supply voltage. For example, taking the first power supply voltage PV1 as VSS and the second power supply voltage PV2 as VDD, the first, second, and third intermediate power supply voltages sequentially increase between VSS and VDD. If the first power supply voltage PV1 is VDD and the second power supply voltage PV2 is VSS, the first, second, and third intermediate power supply voltages sequentially decrease between VDD and VSS.

[0086] In some embodiments, the second capacitor structure includes sub-capacitors connected in series and sub-capacitors connected in parallel, thereby increasing the overall operating voltage of the capacitor structure to meet product voltage requirements while increasing the capacitance of the capacitor structure.

[0087] For example, the second capacitor structure further includes one or more additional electrode layers located on a side of the lower electrode layer away from the upper electrode layer and / or on a side of the upper electrode layer away from the lower electrode layer. For example, the one or more additional electrodes and the lower electrode layer or every two adjacent electrode layers in the lower electrode layer form a third sub-capacitor, and the third sub-capacitor is connected in parallel with the second sub-capacitor.

[0088] In some embodiments, the one or more additional electrodes are electrically floating or connected to an additional power supply voltage, the additional power supply voltage being greater than one of the first power supply voltage and the second power supply voltage and less than the other of the first power supply voltage and the second power supply voltage.

[0089] refer to Figure 4B For example, in an embodiment where the second capacitor structure CS2 includes four electrode layers, the first electrode layer 101 serves as a lower electrode layer Eb, connected to a first power supply voltage PV1; the third electrode layer 103 serves as an upper electrode layer Et, connected to a second power supply voltage PV2; and the second electrode layer 102 serves as an intermediate electrode layer Em, which can be electrically floating or connected to another intermediate power supply voltage. Each adjacent two electrode layers from the first electrode layer 101 to the third electrode layer 103 and the inter-electrode dielectric layer 90 therebetween constitute a second sub-capacitor C2, and multiple second sub-capacitors C2 are connected in series. The fourth electrode layer 104 serves as an additional electrode layer Ea, and the fourth electrode layer 104, the adjacent third electrode layer 103, and the inter-electrode dielectric layer 90 therebetween constitute a third sub-capacitor C3. The third sub-capacitor C3 is connected in parallel with the second sub-capacitor C2.

[0090] In some embodiments, the fourth electrode layer 104 (i.e., the additional electrode layer Ea) may be electrically floating, or the additional electrode layer Ea may be connected to an additional power supply voltage that is between the first power supply voltage PV1 and the second power supply voltage PV2, i.e., greater than one of the first power supply voltage PV1 and the second power supply voltage PV2, and less than the other of the first power supply voltage PV1 and the second power supply voltage PV2. For example, the additional power supply voltage connected to the fourth electrode layer 104 and the intermediate power supply voltage connected to the second electrode layer 102 may be the same or different power supply voltages.

[0091] refer to Figure 4C In some embodiments, the second electrode layer 102 serves as a lower electrode layer Eb, connected to a first power supply voltage PV1; the fourth electrode layer 104 serves as an upper electrode layer Et, connected to a second power supply voltage PV2; and the third electrode layer 103 serves as an intermediate electrode layer Em, which can be electrically floating or connected to another intermediate power supply voltage. Each adjacent pair of electrode layers from the second electrode layer 102 to the fourth electrode layer 104 and the inter-electrode dielectric layer 90 therebetween form a second sub-capacitor C2, and multiple second sub-capacitors C2 are connected in series. The first electrode layer 101 serves as an additional electrode layer Ea, and the first electrode layer 101, the adjacent second electrode layer 102, and the inter-electrode dielectric layer 90 therebetween together form a third sub-capacitor C3. The third sub-capacitor C3 is connected in parallel with the second sub-capacitor C2.

[0092] In some embodiments, the first electrode layer 101 (i.e., the additional electrode layer Ea) may be electrically floating, or the additional electrode layer Ea may be connected to an additional power supply voltage that is between the first power supply voltage PV1 and the second power supply voltage PV2. For example, the additional power supply voltage connected to the first electrode layer 101 and the intermediate power supply voltage connected to the third electrode layer 103 may be the same or different power supply voltages.

[0093] Figures 5B to 5F In an embodiment in which the second capacitor structure includes five electrode layers, the second capacitor structure includes sub-capacitors connected in series and sub-capacitors connected in parallel.

[0094] refer to Figure 5B In some embodiments, the first electrode layer 101 serves as a lower electrode layer Eb, connected to a first power supply voltage PV1; the fourth electrode layer 104 serves as an upper electrode layer Et, connected to a second power supply voltage PV2; the second electrode layer 102 and the third electrode layer 103 serve as intermediate electrode layers Em, each of which can be electrically floating or connected to another intermediate power supply voltage. Each adjacent pair of electrode layers from the first electrode layer 101 to the fourth electrode layer 104, and the inter-electrode dielectric layer 90 therebetween, form a second sub-capacitor C2, and multiple second sub-capacitors C2 are connected in series. The fifth electrode layer 105 serves as an additional electrode layer Ea, and together with the adjacent fourth electrode layer 104 and the inter-electrode dielectric layer 90 therebetween, forms a third sub-capacitor C3. The third sub-capacitor C3 is connected in parallel with the multiple second sub-capacitors C2.

[0095] In some embodiments, the fifth electrode layer 105 (i.e., the additional electrode layer Ea) may be electrically floating or connected to an additional power supply voltage that is between the first power supply voltage PV1 and the second power supply voltage PV2, i.e., greater than one of the first power supply voltage and less than the other. For example, the additional power supply voltage connected to the fifth electrode layer 105 may be the same as or different from the intermediate power supply voltage connected to the third electrode layer 103.

[0096] refer to Figure 5C In some embodiments, the first electrode layer 101 serves as a lower electrode layer Eb, connected to a first power supply voltage PV1; the third electrode layer 103 serves as an upper electrode layer Et, connected to a second power supply voltage PV2; and the second electrode layer 102 serves as an intermediate electrode layer Em, which can be electrically floating or connected to another intermediate power supply voltage. Each adjacent pair of electrode layers from the first electrode layer 101 to the third electrode layer 103, and the inter-electrode dielectric layer 90 therebetween, form a second sub-capacitor C2, and multiple second sub-capacitors C2 are connected in series. The fourth electrode layer 104 and the fifth electrode layer 105 both serve as additional electrode layers Ea. The fifth electrode layer 105, the adjacent fourth electrode layer 104 (i.e., the two adjacent additional electrode layers), and the inter-electrode dielectric layer 90 therebetween collectively form a third sub-capacitor C3. The fourth electrode layer 104 (i.e., the additional electrode layer) and the adjacent third electrode layer 103 (i.e., the upper electrode layer Et) collectively form a third sub-capacitor C3. The two third sub-capacitors C3 may be connected in series with each other and in parallel with the second sub-capacitor C2.

[0097] That is, in this embodiment, multiple additional electrode layers Ea are provided on a side of the upper electrode layer Et that is away from the middle electrode layer Em. Adjacent additional electrode layers Ea and corresponding inter-electrode dielectric layers 90 among the multiple additional electrode layers Ea collectively constitute a third sub-capacitor C3. Furthermore, the additional electrode layers Ea adjacent to the upper electrode layer Et, the upper electrode layer Ea, and corresponding inter-electrode dielectric layers 90 also constitute a third sub-capacitor C3.

[0098] In some embodiments, the fourth electrode layer 104 and the fifth electrode layer 105 (i.e., the additional electrode layer Ea) can each be electrically floating or connected to an additional power supply voltage that is between the first power supply voltage PV1 and the second power supply voltage PV2. When multiple additional electrode layers are connected to the additional power supply voltage, the additional power supply voltages connected to the multiple additional electrode layers are different from one another and decrease or increase sequentially between the first power supply voltage and the second power supply voltage. For example, when the first power supply voltage PV1 is VSS and the second power supply voltage PV2 is VDD, the additional power supply voltage connected to the fourth electrode layer 104 is less than VDD and greater than VSS, and the additional power supply voltage connected to the fifth electrode layer 105 is less than the power supply voltage connected to the fourth electrode layer 104 and greater than VSS.

[0099] refer to Figure 5D In some embodiments, the second electrode layer 102 serves as a lower electrode layer Eb, connected to a first power supply voltage PV1; the fifth electrode layer 105 serves as an upper electrode layer Et, connected to a second power supply voltage PV2; the third electrode layer 103 and the fourth electrode layer 104 serve as intermediate electrode layers Em, each of which can be electrically floating or connected to another intermediate power supply voltage. Each adjacent pair of electrode layers from the second electrode layer 102 to the fifth electrode layer 105 and the inter-electrode dielectric layer 90 therebetween form a second sub-capacitor C2, and multiple second sub-capacitors C2 are connected in series. The first electrode layer 101 serves as an additional electrode layer Ea, and the first electrode layer 101, the adjacent second electrode layer 102, and the inter-electrode dielectric layer 90 therebetween together form a third sub-capacitor C3. The third sub-capacitor C3 is connected in parallel with the second sub-capacitors C2.

[0100] In some embodiments, the first electrode layer 101 (i.e., the additional electrode layer Ea) may be electrically floating or connected to an additional power supply voltage that is greater than one of the first power supply voltage PV1 and the second power supply voltage PV2 and less than the other of the first power supply voltage PV1 and the second power supply voltage PV2. For example, the additional power supply voltage connected to the first electrode layer 101 may be the same as or different from the intermediate power supply voltage connected to the third electrode layer 103.

[0101] refer to Figure 5EIn some embodiments, the second electrode layer 102 serves as a lower electrode layer Eb, connected to a first power supply voltage PV1; the fourth electrode layer 104 serves as an upper electrode layer Et, connected to a second power supply voltage PV2; and the third electrode layer 103 serves as an intermediate electrode layer Em, which can be electrically floating or connected to another intermediate power supply voltage. Each adjacent pair of electrode layers from the second electrode layer 102 to the fourth electrode layer 104, and the inter-electrode dielectric layer 90 therebetween, form a second sub-capacitor C2, and multiple second sub-capacitors C2 are connected in series. The first electrode layer 101 and the fifth electrode layer 105 both serve as additional electrode layers Ea, and the first electrode layer 101, the adjacent second electrode layer 102, and the inter-electrode dielectric layer 90 therebetween collectively form a third sub-capacitor C3. The fifth electrode layer 105, the adjacent fourth electrode layer 104, and the inter-electrode dielectric layer 90 therebetween collectively form a third sub-capacitor C3. The third sub-capacitor C3 is connected in parallel with the second sub-capacitor C2.

[0102] That is, in this embodiment, the additional electrode layer Ea is provided on the side of the lower electrode layer Eb away from the middle electrode layer Em and on the side of the upper electrode layer Et away from the middle electrode layer Em.

[0103] In some embodiments, the first electrode layer 101 and the fifth electrode layer 105 (i.e., the additional electrode layer Ea) can each be electrically floating or connected to an additional power supply voltage that is greater than one of the first power supply voltage PV1 and the second power supply voltage PV2 and less than the other of the first power supply voltage PV1 and the second power supply voltage PV2. For example, the additional power supply voltage connected to the first electrode layer 101 can be the same as or different from the intermediate power supply voltage connected to the third electrode layer 103; and the additional power supply voltage connected to the fifth electrode layer 105 can be the same as or different from the intermediate power supply voltage connected to the third electrode layer 103.

[0104] refer to Figure 5FIn some embodiments, the third electrode layer 103 serves as a lower electrode layer Eb, connected to a first power supply voltage PV1; the third electrode layer 103 serves as an upper electrode layer Et, connected to a second power supply voltage PV2; and the fourth electrode layer 104 serves as an intermediate electrode layer Em, which can be electrically floating or connected to another intermediate power supply voltage. Every two adjacent electrode layers from the third electrode layer 103 to the fifth electrode layer 105, and the inter-electrode dielectric layer 90 therebetween, form a second sub-capacitor C2, and multiple second sub-capacitors C2 are connected in series. The first electrode layer 101 and the second electrode layer 102 both serve as additional electrode layers Ea. The first electrode layer 101 and the adjacent second electrode layer 102 (i.e., the two adjacent additional electrode layers) and the inter-electrode dielectric layer 90 therebetween collectively form a third sub-capacitor C3. The second electrode layer 102 (i.e., the additional electrode layer) and the adjacent third electrode layer 103 (i.e., the lower electrode layer Eb) collectively form a third sub-capacitor C3. The two third sub-capacitors C3 can be connected in series and in parallel with the second sub-capacitor C2.

[0105] That is, in this embodiment, multiple additional electrode layers Ea are provided on a side of the lower electrode layer Eb that is away from the middle electrode layer Em. Adjacent additional electrode layers Ea form a third sub-capacitor C3, and additional electrode layers adjacent to the lower electrode layer and the lower electrode layer also form a third sub-capacitor C3.

[0106] In some embodiments, the first electrode layer 101 and the second electrode layer 102 (i.e., the additional electrode layer Ea) can each be electrically floating or connected to an additional power supply voltage that is between the first power supply voltage PV1 and the second power supply voltage PV2. When multiple additional electrode layers are connected to an intermediate power supply voltage, the intermediate power supply voltages connected to the multiple additional electrode layers are different from each other and can decrease or increase in sequence. For example, when the first power supply voltage PV1 is VSS and the second power supply voltage PV2 is VDD, the additional power supply voltage connected to the second electrode layer 102 can be greater than VSS, and the additional power supply voltage connected to the first electrode layer 101 can be greater than the additional power supply voltage connected to the second electrode layer 102, and both additional power supply voltages can be less than VDD.

[0107] exist Figure 4B and Figure 4C as well as Figures 5B to 5F In embodiments including additional electrode layers, when the additional electrode layer Ea is electrically floating, since the additional electrode layer Ea is close to the upper electrode layer Et or the lower electrode layer Eb, an induced electric field is generated between the additional electrode layer Ea and the adjacent electrode layer based on electrostatic induction, and the additional electrode layer Ea and the adjacent electrode layer constitute a third sub-capacitor C3 in parallel with the second sub-capacitor C2.

[0108] In some embodiments, the number of electrode layers in the first capacitor structure is the same as the number of electrode layers in the second capacitor structure; the electrode layers of the first capacitor structure CS1 are arranged on the same layer as the electrode layers of the second capacitor structure CS2. Therefore, in the embodiment in which the second capacitor structure includes four or five electrode layers, the first capacitor structure also includes four or five electrode layers.

[0109] Figure 6 An example is shown in which each electrode layer is connected to a power supply voltage when the first capacitor structure includes four electrode layers; Figure 7 The example of connecting each electrode layer to a power supply voltage when the first capacitor structure includes five electrode layers is shown. Figure 6 and Figure 7 The conductive via is only schematically shown to be connected to the power supply voltage, and it is not limited to the power supply voltage being directly located on the conductive via.

[0110] refer to Figure 6 In some embodiments, the first capacitor structure CS1 includes a first electrode layer 101, a second electrode layer 102, a third electrode layer 103 and a fourth electrode layer 104. The first electrode layer 101, the second electrode layer 102, the third electrode layer 103 and the fourth electrode layer 104 of the first capacitor structure CS1 are respectively Figures 4A to 4C The first electrode layer 101, the second electrode layer 102, the third electrode layer 103 and the fourth electrode layer 104 of the second capacitor structure CS2 shown in FIG are arranged on the same layer, and the inter-electrode dielectric layers in the first capacitor structure CS1 are also arranged on the same layer as the corresponding inter-electrode dielectric layers in the second capacitor structure CS2.

[0111] In some embodiments, in the first capacitor structure CS1, the first electrode layer 101 and the third electrode layer 103 can be electrically connected to each other and connected to the same first additional power supply voltage PV01, for example, they can be connected to each other through multiple first conductive vias V1 and conductive circuits and other conductive components, and connected to the first additional power supply voltage PV01; the second electrode layer 102 and the fourth electrode layer 104 can be electrically connected to each other and connected to the same second additional power supply voltage PV02, for example, they can be connected to each other through multiple first conductive vias V1 and conductive circuits and other conductive components, and connected to the second additional power supply voltage PV02.

[0112] refer to Figure 7 In some embodiments, the first capacitor structure CS1 includes a first electrode layer 101, a second electrode layer 102, a third electrode layer 103, a fourth electrode layer 104, and a fifth electrode layer 105. The first electrode layer 101, the second electrode layer 102, the third electrode layer 103, the fourth electrode layer 104, and the fifth electrode layer 105 of the first capacitor structure CS1 are respectively Figures 5A to 5FThe first electrode layer 101, the second electrode layer 102, the third electrode layer 103, the fourth electrode layer 104 and the fifth electrode layer 105 of the second capacitor structure CS2 shown in the figure are arranged on the same layer, and the inter-electrode dielectric layers in the first capacitor structure CS1 are also arranged on the same layer as the corresponding inter-electrode dielectric layers in the second capacitor structure CS2.

[0113] In some embodiments, in the first capacitor structure CS1, the first electrode layer 101, the third electrode layer 103, and the fifth electrode layer 105 can be electrically connected to each other and to the same first additional power supply voltage PV01. For example, they can be electrically connected to each other and to the first additional power supply voltage PV01 through a plurality of first conductive vias V1 and conductive traces. The second electrode layer 102 and the fourth electrode layer 104 can be electrically connected to each other and to the same second additional power supply voltage PV02. For example, they can be electrically connected to each other and to the second additional power supply voltage PV02 through a plurality of first conductive vias V1 and conductive traces.

[0114] In some embodiments, the electric field directions of every two adjacent first sub-capacitors in the multiple sub-capacitors of the first capacitor structure are opposite; and the electric field directions of at least two sub-capacitors in the multiple sub-capacitors of the second capacitor structure are the same.

[0115] For example, in various embodiments, the multiple first sub-capacitors C1 of the first capacitor structure CS1 are connected in parallel with each other, and the electric field directions of every two adjacent first sub-capacitors C1 are opposite; in the second capacitor structure CS2, the electric field directions of at least the multiple second sub-capacitors C2 connected in series among the multiple sub-capacitors are the same; when the second capacitor structure CS2 includes a third sub-capacitor C3 connected in parallel with the second sub-capacitor C2, the electric field direction of the third sub-capacitor C3 is opposite to the electric field direction of the second sub-capacitor C2.

[0116] In some embodiments, the substrate of the interposer is a semiconductor substrate, the first capacitor structure and the second capacitor structure are deep trench capacitors, and each has a portion embedded in the substrate.

[0117] In some embodiments, the adapter plate also includes: an interconnection structure, which is arranged on one side of the semiconductor substrate and includes a conductive component electrically connected to the corresponding electrode layers of the first capacitor structure and the second capacitor structure; and a substrate through-hole, which is embedded in the semiconductor substrate and electrically connected to the interconnection structure.

[0118] Return Reference Figure 1In some embodiments, the substrate 100 is a semiconductor substrate, for example, it may be or include a silicon substrate. The first capacitor structure CS1 and the second capacitor structure CS2 are deep trench capacitors, and each has a portion embedded in the substrate. For example, the substrate 100 has a first trench 81 and a second trench 82, and the first trench 81 and the second trench 82 extend from the main surface of the substrate 100 into the substrate 100 and may have approximately the same depth. The respective electrode layers and inter-electrode dielectric layers of the first capacitor structure CS1 and the second capacitor structure CS2 may each have a portion located in the corresponding trench, and may also include another portion located on the main surface of the substrate. In some embodiments, an isolation layer 85 is further provided between the first electrode layer 101 of each capacitor structure and the substrate 100 to isolate the capacitor structure from the semiconductor substrate.

[0119] In some embodiments, the interposer 200 can be used to interconnect other components within a package structure. For example, the interposer includes an interconnect structure 150 located on a semiconductor substrate. The interconnect structure 150 includes a dielectric structure 110 and a conductive structure at least partially embedded within the dielectric structure 110. The conductive structure includes conductive components connected to corresponding electrode layers and also includes conductive traces for interconnecting chips. A plurality of conductive vias 83 are embedded in the semiconductor substrate and electrically connected to the interconnect structure 150.

[0120] An embodiment of the present disclosure provides a packaging structure, comprising an adapter board, a chip module, and a packaging substrate according to any of the above embodiments; the chip module is arranged on one side of the adapter board, and the multiple chips in the chip module are interconnected with each other through the adapter board; the packaging substrate is arranged on a side of the adapter board away from the chip module, and is electrically connected to the chip module through the adapter board.

[0121] Figure 8 A schematic cross-sectional view illustrating a package structure according to some embodiments of the present disclosure is shown.

[0122] refer to Figure 8 For example, the package structure 500 includes an adapter plate 200, a chip module 11, and a package substrate 300. The adapter plate 200 can be any of the adapter plates described above, i.e., an adapter plate including corresponding first and second capacitor structures. The chip module 11 includes multiple chips 10 disposed on one side of the adapter plate 200, and the multiple chips 10 in the chip module 11 are interconnected via the adapter plate.

[0123] The number and type of each chip 10 in the chip module 11 can be selected according to product requirements; for example, the chip module 11 may include a system on chip (SoC), a digital signal processor (DSP) chip, a graphics processing unit (GPU), an application specific integrated circuit (ASIC) chip, a high bandwidth memory chip (HBM) and other memory chips, a central processing unit (CPU), a tensor processing unit (TPU), a neural network processor (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), a general-purpose graphics processing unit (GPGPU), a core module, an intelligent inference chip, an intelligent training chip, an edge computing GPU chip, a general-purpose CPU chip and one or more of a specific CPU chip.

[0124] The packaging substrate 300 is disposed on a side of the adapter board 200 away from the chip module 11 and is electrically connected to the chip module 11 through the adapter board 200 .

[0125] For example, the chip module 11 can be electrically connected to the adapter board 200 via conductive bumps 12. The conductive bumps 12 can be or include micro-bumps. Conductive connectors 22 are disposed on a side of the adapter board 200 away from the chip module 11 and are used to electrically connect the adapter board 200 to the package substrate 300. The conductive connectors 22 can be or include conductive bumps such as controlled collapsed chip connection (C4) bumps. Conductive terminals 32 are disposed on a side of the package substrate 300 away from the adapter board 200 and are used to electrically connect the package structure 500 to other external components. These external components can include, for example, printed circuit boards (PCBs).

[0126] In the embodiment of the present disclosure, by setting the first capacitor structure and the second capacitor structure in the adapter board, the demand for high-capacitance capacitors and the demand for high-working voltage capacitors can be met at the same time, and the two capacitor structures can be manufactured under the same process platform, thereby simplifying the process and saving manufacturing costs.

[0127] There are a few points to note:

[0128] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design.

[0129] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0130] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A transfer plate, characterized in that: include: substrate; as well as A first capacitor structure and a second capacitor structure are provided on the substrate, and each includes a plurality of electrode layers and an inter-electrode dielectric layer located between every two adjacent electrode layers, wherein every two adjacent electrode layers and the corresponding inter-electrode dielectric layer constitute a sub-capacitor; Wherein, the first capacitor structure includes a plurality of first sub-capacitors connected in parallel with each other; The second capacitor structure includes a plurality of second sub-capacitors connected in series, and includes a lower electrode layer, an upper electrode layer, and at least one intermediate electrode layer, wherein the at least one intermediate electrode layer is located between the lower electrode layer and the upper electrode layer, and each adjacent two electrode layers among the lower electrode layer, the upper electrode layer, and the at least one intermediate electrode layer and the corresponding inter-electrode dielectric layer constitute a second sub-capacitor; The multiple electrode layers and multiple inter-electrode dielectric layers of the first capacitor structure are respectively arranged on the same layer as the multiple electrode layers and multiple inter-electrode dielectric layers of the second capacitor structure, and the capacitance of the first capacitor structure is greater than the capacitance of the second capacitor structure, and the operating voltage of the second capacitor structure is higher than the operating voltage of the first capacitor structure.

2. The adapter plate according to claim 1, wherein: In the second capacitor structure, the lower electrode layer is configured to be connected to a first power supply voltage, the upper electrode layer is configured to be connected to a second power supply voltage, and the at least one intermediate electrode layer is each configured to be electrically floating or connected to an intermediate power supply voltage; and The first power supply voltage is different from the second power supply voltage, and the intermediate power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

3. The adapter plate according to claim 2, characterized in that: The at least one intermediate electrode layer of the second capacitor structure includes multiple intermediate electrode layers, and the multiple intermediate electrode layers are respectively connected to multiple intermediate power supply voltages, and the multiple intermediate power supply voltages increase or decrease in sequence between the first power supply voltage and the second power supply voltage.

4. The adapter plate according to claim 2, characterized in that: The second capacitor structure further includes one or more additional electrode layers located on a side of the lower electrode layer away from the upper electrode layer and / or a side of the upper electrode layer away from the lower electrode layer.

5. The adapter plate according to claim 4, characterized in that: The one or more additional electrode layers and the lower electrode layer or every two adjacent electrode layers in the lower electrode layer form a third sub-capacitor, and the third sub-capacitor is connected in parallel with the plurality of second sub-capacitors.

6. The adapter plate according to claim 4, characterized in that: The one or more additional electrode layers are electrically floating or connected to an additional power supply voltage, which is greater than one of the first power supply voltage and the second power supply voltage and less than the other of the first power supply voltage and the second power supply voltage.

7. The adapter plate according to any one of claims 1 to 6, characterized in that: In the plurality of electrode layers of the first capacitor structure, every two adjacent electrode layers are connected to different power supply voltages, and every two electrode layers separated by one electrode layer are connected to the same power supply voltage.

8. The adapter plate according to any one of claims 1 to 6, characterized in that: In the first sub-capacitor and the second sub-capacitor arranged in the same layer in the first capacitor structure and the second capacitor structure, the inter-electrode dielectric layer of the first sub-capacitor and the inter-electrode dielectric layer of the second sub-capacitor have the same thickness, and the relative area between the two electrode layers in the first sub-capacitor is the same as the relative area between the two electrode layers in the second sub-capacitor.

9. The adapter plate according to claim 2, wherein: The second capacitor structure includes a first electrode layer, a second electrode layer and a third electrode layer arranged in sequence, wherein the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, and the at least one intermediate electrode layer is the second electrode layer.

10. The adapter plate according to claim 2, wherein: The second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer arranged in sequence, the first electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, and the at least one intermediate electrode layer includes the second electrode layer and the third electrode layer.

11. The adapter plate according to claim 2, characterized in that: The second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer arranged in sequence; wherein the first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the second electrode layer, and the fourth electrode layer is an additional electrode layer; or The second electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the third electrode layer, and the first electrode layer is an additional electrode layer, The additional electrode layer is electrically floating or connected to an additional power supply voltage, and the additional power supply voltage is greater than one of the first power supply voltage and the second power supply voltage, and less than the other of the first power supply voltage and the second power supply voltage.

12. The adapter plate according to claim 2, characterized in that: The second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer and a fifth electrode layer arranged in sequence, wherein the first electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, and the at least one intermediate electrode layer includes the second electrode layer, the third electrode layer and the fourth electrode layer.

13. The adapter plate according to claim 2, characterized in that: The second capacitor structure includes a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer and a fifth electrode layer arranged in sequence, wherein the first electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer includes the second electrode layer and the third electrode layer, and the fifth electrode layer serves as an additional electrode layer; or The first electrode layer is the lower electrode layer, the third electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the second electrode layer, and the fourth electrode layer and the fifth electrode layer are additional electrode layers; or The second electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, the at least one intermediate electrode layer includes the third electrode layer and the fourth electrode layer, and the first electrode layer is an additional electrode layer; or The second electrode layer is the lower electrode layer, the fourth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the third electrode layer, and the first electrode layer and the fifth electrode layer are additional electrode layers; or The third electrode layer is the lower electrode layer, the fifth electrode layer is the upper electrode layer, the at least one intermediate electrode layer is the fourth electrode layer, and the first electrode layer and the second electrode layer are additional electrode layers.

14. The adapter plate according to claim 13, characterized in that: Each of the additional electrode layers is electrically floating or connected to an additional power supply voltage, which is greater than one of the first power supply voltage and the second power supply voltage and less than the other of the first power supply voltage and the second power supply voltage.

15. The adapter plate according to any one of claims 1-6 and 9-14, characterized in that: The electric fields of two adjacent first sub-capacitors in the plurality of sub-capacitors of the first capacitor structure are in opposite directions; The electric field directions of at least two sub-capacitors among the multiple sub-capacitors of the second capacitor structure are the same.

16. The adapter plate according to any one of claims 1-6 and 9-14, characterized in that: The substrate is a semiconductor substrate, the first capacitor structure and the second capacitor structure are deep trench capacitors, and each has a portion embedded in the substrate.

17. The adapter plate according to claim 16, characterized in that: Also includes: an interconnect structure, disposed on one side of the semiconductor substrate and comprising a conductive member electrically connected to corresponding electrode layers of the first capacitor structure and the second capacitor structure; as well as The substrate through-hole is embedded in the semiconductor substrate and electrically connected to the interconnection structure.

18. A packaging structure, characterized in that: comprising an adapter plate according to any one of claims 1 to 17; A chip module is provided on one side of the adapter board, and a plurality of chips in the chip module are interconnected with each other through the adapter board; and The packaging substrate is arranged on a side of the adapter board away from the chip module and is electrically connected to the chip module through the adapter board.

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