Time measuring unit and test machine

Abstract

The utility model relates to a time measuring unit and a testing machine, and the time measuring unit comprises a first sampling circuit which is connected with a grounding end and a first end of a to-be-tested device, carries out the voltage division sampling of a signal outputted by the first end of the to-be-tested device, and outputs a first sampling signal; the second sampling circuit is connected with the grounding end and the second end of the to-be-tested device, performs voltage division sampling on a signal output by the second end of the to-be-tested device, and outputs a second sampling signal; the signal processing circuit is connected with the first sampling circuit and the second sampling circuit, receives the first sampling signal and the second sampling signal, carries out subtraction processing, and outputs a processed signal; and the time measurement circuit is connected with the signal processing circuit, compares the processed signal with a preset voltage threshold value, and obtains a time parameter measurement result according to a comparison result.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a time measurement unit and a testing machine. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of devices under test (DUTs), eliminating defective products and ensuring the quality of semiconductor devices before they leave the factory. In addition to measuring the voltage and current of the DUT, the timing parameters of the DUT are also important indicators. The timing measurement unit in the test board primarily measures the frequency, period, rise (fall) time, and pulse width of the DUT signal.

[0003] In a traditional time measurement unit, the voltage between the two terminals of the DUT is sampled through voltage division. The resulting voltage division signal is then compared with the upper and lower voltage thresholds to generate a corresponding comparison waveform. The time between the two comparison waveforms is then recorded to measure the timing parameters of the DUT signal. If the DUT's ground terminal and the measurement unit's ground terminal are not connected to the same ground, a common-mode voltage may exist, affecting the measurement results and resulting in low measurement accuracy. Utility Model Content

[0004] Based on this, it is necessary to provide a time measurement unit and a test machine that can improve test accuracy to address the above problems.

[0005] A first aspect of the present application provides a time measurement unit, comprising:

[0006] a first sampling circuit connected to a ground terminal and a first terminal of a device under test, performing voltage division sampling on a signal outputted from the first terminal of the device under test, and outputting a first sampling signal;

[0007] a second sampling circuit connected to a ground terminal and the second terminal of the device under test, performing voltage division sampling on a signal output from the second terminal of the device under test, and outputting a second sampling signal;

[0008] a signal processing circuit connected to the first sampling circuit and the second sampling circuit, receiving the first sampling signal and the second sampling signal, performing subtraction processing on them, and outputting a processed signal;

[0009] The time measurement circuit is connected to the signal processing circuit, compares the processed signal with a preset voltage threshold, and obtains a time parameter measurement result according to the comparison result.

[0010] In one embodiment, the first sampling circuit includes a resistor R1, a resistor R2, a capacitor C1, and a capacitor C2, wherein a first end of the resistor R1 is connected to a first end of the device under test, a second end of the resistor R1 is connected to a first end of the resistor R2 and the signal processing circuit, a second end of the resistor R2 is connected to a ground end, the capacitor C1 is connected in parallel to the resistor R1, and the capacitor C2 is connected in parallel to the resistor R2.

[0011] In one embodiment, the second sampling circuit includes a resistor R3, a resistor R4, a capacitor C3, and a capacitor C4, wherein a first end of the resistor R3 is connected to a second end of the device under test, a second end of the resistor R3 is connected to a first end of the resistor R4 and the signal processing circuit, a second end of the resistor R4 is connected to a ground end, the capacitor C3 is connected in parallel with the resistor R3, and the capacitor C4 is connected in parallel with the resistor R4.

[0012] In one embodiment, the resistance value of the resistor R1 is consistent with the resistance value of the resistor R3 , and the resistance value of the resistor R2 is consistent with the resistance value of the resistor R4 .

[0013] In one embodiment, the capacitance of the capacitor C1 is consistent with the capacitance of the capacitor C3 , and the capacitance of the capacitor C2 is consistent with the capacitance of the capacitor C4 .

[0014] In one embodiment, the signal processing circuit includes a buffer BUFFER1, a buffer BUFFER2 and a subtractor, the buffer BUFFER1 is connected to the first sampling circuit and the subtractor, the buffer BUFFER2 is connected to the second sampling circuit and the subtractor, and the subtractor is connected to the time measurement circuit.

[0015] In one embodiment, the time measurement circuit includes a first comparator, a second comparator, and a processor, the first comparator is connected to the signal processing circuit and the processor, and the second comparator is connected to the signal processing circuit and the processor.

[0016] In one embodiment, the time measurement circuit further includes a first digital-to-analog converter and a second digital-to-analog converter, wherein the first digital-to-analog converter is connected to the first comparator, and the second digital-to-analog converter is connected to the second comparator.

[0017] In one embodiment, the processor is an FPGA, a CPU or an MCU.

[0018] A second aspect of the present application provides a testing machine, comprising the above-mentioned time measurement unit.

[0019] The above-mentioned time measurement unit and test machine, the first sampling circuit and the second sampling circuit are both connected to the ground terminal, and the signals at both ends of the device to be tested are sampled by voltage division, and then subtraction processing is performed through the signal processing circuit, which can effectively attenuate the common-mode voltage existing in the device to be tested, reduce the impact of the common-mode voltage on the measurement results, and improve the measurement accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a structural block diagram of a time measurement unit in one embodiment;

[0021] Figure 2 FIG. 4 is a structural principle diagram of a time measurement unit in one embodiment. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0024] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0025] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0026] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0027] In one embodiment, Figure 1 As shown, a time measurement unit is provided, including a first sampling circuit 110, a second sampling circuit 120, a signal processing circuit 130 and a time measurement circuit 140. The first sampling circuit 110 is connected to the ground terminal and the first terminal of the device under test (DUT), performs voltage division sampling on the signal output from the first terminal of the device under test (DUT), and outputs a first sampling signal; the second sampling circuit 120 is connected to the ground terminal and the second terminal of the device under test (DUT), performs voltage division sampling on the signal output from the second terminal of the device under test (DUT), and outputs a second sampling signal; the signal processing circuit 130 is connected to the first sampling circuit 110 and the second sampling circuit 120, receives the first sampling signal and the second sampling signal, performs subtraction processing on the signal, and outputs the processed signal; the time measurement circuit 140 is connected to the signal processing circuit 130, compares the processed signal with a preset voltage threshold, and obtains a time parameter measurement result based on the comparison result.

[0028] Specifically, the first sampling circuit 110 is connected to the first terminal of the device under test (DUT) and receives the high-end signal / low-end signal output by the DUT for voltage division sampling. The second sampling circuit 120 is connected to the second terminal of the DUT and receives the low-end signal / high-end signal output by the DUT for voltage division sampling. Because both the first sampling circuit 110 and the second sampling circuit 120 are connected to the ground terminal, during sampling, the high-end signal and the low-end signal output by the DUT are simultaneously voltage-divided and attenuated relative to the ground terminal, attenuating the signal amplitude to an appropriate level. The common-mode voltage of the DUT is also simultaneously attenuated. The first sampling circuit 110 and the second sampling circuit 120 can also use the same circuit structure and the same component parameters, so that the high-end signal and the low-end signal output by the DUT are voltage-divided and attenuated by the same multiple. After receiving the first and second sampling signals, the signal processing circuit 130 performs subtraction on the two signals through an internal subtractor, subtracting the common-mode voltage to obtain a processed signal. This signal is then transmitted as an accurate, attenuated test signal to the time measurement circuit 140. The time measurement circuit 140 compares the received signal with the high and low voltage thresholds, respectively, to obtain two comparison waveforms. It then measures the time between the two comparison waveforms to obtain a time parameter measurement result, completing the measurement of the signal time parameters on the device under test (DUT). The time measurement circuit 140 can store the time parameter measurement results in an external or local memory, or upload them to the host computer of the tester for performance analysis of the device under test (DUT).

[0029] The time measurement unit, with its first sampling circuit 110 and second sampling circuit 120 both connected to ground, performs voltage division sampling on the signals at both ends of the DUT. Signal processing circuit 130 then performs subtraction processing, effectively attenuating the common-mode voltage present on the DUT, reducing its impact on measurement results and improving measurement accuracy. By employing differential measurement, the DUT and the time measurement unit can be separated from each other, enabling accurate measurements even when the voltage on the DUT is high.

[0030] In one embodiment, Figure 2 As shown, the first sampling circuit 110 includes a resistor R1, a resistor R2, a capacitor C1, and a capacitor C2. The first end of the resistor R1 is connected to the first end of the device under test (DUT), the second end of the resistor R1 is connected to the first end of the resistor R2 and the signal processing circuit 130, and the second end of the resistor R2 is connected to the ground terminal. The capacitor C1 is connected in parallel with the resistor R1, and the capacitor C2 is connected in parallel with the resistor R2. The signal output from the first end of the device under test (DUT) is sampled by the resistors R1 and R2 and then transmitted to the signal processing circuit 130. The values of the capacitors C1 and C2 can be selected according to actual needs. For example, by selecting appropriate capacitors to match the zero and pole points of the signal, the influence of the parasitic capacitance of the wiring and the subsequent devices is eliminated, and the input bandwidth is improved. Furthermore, the second sampling circuit 120 includes resistors R3 and R4, capacitors C3 and C4. The first end of resistor R3 is connected to the second end of the device under test (DUT), the second end of resistor R3 is connected to the first end of resistor R4 and the signal processing circuit 130, and the second end of resistor R4 is connected to ground. Capacitor C3 is connected in parallel with resistor R3, and capacitor C4 is connected in parallel with resistor R4. The signal output from the second end of the device under test (DUT) is sampled by voltage division by resistors R3 and R4, and then transmitted to the signal processing circuit 130.

[0031] Among them, the resistance value of resistor R1 is consistent with the resistance value of resistor R3, and the resistance value of resistor R2 is consistent with the resistance value of resistor R4. The consistent resistance value can be the same resistance value or the resistance difference can be within the allowable difference range. Further, the capacitance value of capacitor C1 is consistent with the capacitance value of capacitor C3, and the capacitance value of capacitor C2 is consistent with the capacitance value of capacitor C4. Similarly, the consistent capacitance value can be the same capacitance value or the capacitance difference can be within the allowable difference range. By selecting parameters for the components of the first sampling circuit 110 and the second sampling circuit 120, the resistance value of resistor R1 is consistent with the resistance value of resistor R3, the resistance value of resistor R2 is consistent with the resistance value of resistor R4, the capacitance value of capacitor C1 is consistent with the capacitance value of capacitor C3, and the capacitance value of capacitor C2 is consistent with the capacitance value of capacitor C4. The high-end signal and the low-end signal of the device under test (DUT) are both attenuated by the same multiple. Since these two signals are divided by the ground terminal of the reference measurement unit, the common-mode voltage of the device under test (DUT) is also attenuated at the same time. The common-mode voltage can be subtracted by performing subtraction processing through the signal processing circuit 130 to ensure measurement accuracy.

[0032] In one embodiment, referring to Figure 2 The signal processing circuit 130 includes a buffer BUFFER1, a buffer BUFFER2 and a subtractor 132. The buffer BUFFER1 is connected to the first sampling circuit 110 and the subtractor 132. The buffer BUFFER2 is connected to the second sampling circuit 120 and the subtractor 132. The subtractor 132 is connected to the time measurement circuit 140.

[0033] Specifically, the input terminal + of buffer BUFFER1 is connected to the second end of resistor R1 and the first end of resistor R2 in first sampling circuit 110, the input terminal - of buffer BUFFER1 is connected to the output terminal of buffer BUFFER1, the output terminal of buffer BUFFER1 is connected to the input terminal + of subtractor 132, the input terminal + of buffer BUFFER2 is connected to the second end of resistor R3 and the first end of resistor R4 in second sampling circuit 120, the input terminal - of buffer BUFFER2 is connected to the output terminal of buffer BUFFER2, the output terminal of buffer BUFFER2 is connected to the input terminal - of subtractor 132, and the output terminal of subtractor 132 is connected to time measurement circuit 140. The first and second sampling signals, obtained after voltage division and sampling by first sampling circuit 110 and second sampling circuit 120, are transmitted to the input terminal + and input terminal - of subtractor 132, respectively, through buffer BUFFER1 and buffer BUFFER2. Subtractor 132 subtracts the two sampling signals, subtracts the common-mode voltage, and transmits the processed signals to time measurement circuit 140.

[0034] It is understandable that in other embodiments, the signal processing circuit 130 may also include only the subtractor 132 , and directly perform subtraction processing on the first sampling signal and the second sampling signal through the subtractor 132 .

[0035] Furthermore, the time measurement circuit 140 may specifically include a first comparator 142, a second comparator 144, and a processor 146. The first comparator 142 is connected to the signal processing circuit 130 and the processor 146, and the second comparator 144 is connected to the signal processing circuit 130 and the processor 146. The processor 144 is not limited to a single type and may be a functional device such as an FPGA (Field-Programmable Gate Array), an MCU (Microcontroller Unit), or a CPU (Central Processing Unit).

[0036] The first comparator 142 and the second comparator 144 are specifically connected to the output of the subtractor 132 in the signal processing circuit 130. The output of the subtractor 132 outputs the processed signal to the first comparator 142 and the second comparator 144. The first comparator 142 and the second comparator 144 respectively compare the signal with the corresponding voltage threshold, and output the comparison waveform to the processor 144. The processor 144 measures the time between the two comparison waveforms to complete the measurement of the signal timing parameters on the device under test (DUT). Both the first comparator 142 and the second comparator 144 can use high-speed comparators to improve signal processing efficiency.

[0037] In addition, the time measurement circuit also includes a first digital-to-analog converter (DAC1) and a second digital-to-analog converter (DAC2). The first digital-to-analog converter (DAC1) is connected to a first comparator 142, and the second digital-to-analog converter (DAC2) is connected to a second comparator 144. Specifically, the two inputs of the first comparator 142 are respectively connected to the first digital-to-analog converter DAC1 and the output of the subtractor 132, and the output of the first comparator 142 is connected to the processor 144. The two inputs of the second comparator 144 are respectively connected to the second digital-to-analog converter DAC2 and the output of the subtractor 132, and the output of the second comparator 144 is connected to the processor 144. The first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 can output analog signals to the first comparator 142 and the second comparator 144, respectively, to adjust the voltage thresholds of the first comparator 142 and the second comparator 144. For example, the first comparator 142 can compare the received signal with a high voltage threshold or a low voltage threshold and output a comparison waveform to the processor 144. The second comparator 144 can compare the received signal with a low voltage threshold or a high voltage threshold and output a comparison waveform to the processor 144. The processor 144 completes the measurement of the signal time parameters on the device under test DUT based on the two comparison waveforms.

[0038] In one embodiment, a tester is provided, including the aforementioned time measurement unit. The time measurement unit may be mounted on a test board associated with the tester, and receives signals output from both ends of the device under test (DUT) for measurement. The tester may also include a host computer connected to the time measurement unit and receiving the time parameter measurement results uploaded by the time measurement unit.

[0039] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A time measurement unit, characterized in that: include: a first sampling circuit connected to a ground terminal and a first terminal of a device under test, performing voltage division sampling on a signal outputted from the first terminal of the device under test, and outputting a first sampling signal; a second sampling circuit connected to a ground terminal and the second terminal of the device under test, performing voltage division sampling on a signal output from the second terminal of the device under test, and outputting a second sampling signal; a signal processing circuit connected to the first sampling circuit and the second sampling circuit, receiving the first sampling signal and the second sampling signal, performing subtraction processing on them, and outputting a processed signal; The time measurement circuit is connected to the signal processing circuit, compares the processed signal with a preset voltage threshold, and obtains a time parameter measurement result according to the comparison result.

2. The time measurement unit according to claim 1, characterized in that The first sampling circuit includes a resistor R1, a resistor R2, a capacitor C1, and a capacitor C2. The first end of the resistor R1 is connected to the first end of the device under test, the second end of the resistor R1 is connected to the first end of the resistor R2 and the signal processing circuit, the second end of the resistor R2 is connected to the ground end, the capacitor C1 is connected in parallel with the resistor R1, and the capacitor C2 is connected in parallel with the resistor R2.

3. The time measurement unit according to claim 2, characterized in that The second sampling circuit includes a resistor R3, a resistor R4, a capacitor C3, and a capacitor C4. The first end of the resistor R3 is connected to the second end of the device under test, the second end of the resistor R3 is connected to the first end of the resistor R4 and the signal processing circuit, the second end of the resistor R4 is connected to the ground end, the capacitor C3 is connected in parallel with the resistor R3, and the capacitor C4 is connected in parallel with the resistor R4.

4. The time measurement unit according to claim 3, characterized in that The resistance value of the resistor R1 is consistent with the resistance value of the resistor R3 , and the resistance value of the resistor R2 is consistent with the resistance value of the resistor R4 .

5. The time measurement unit according to claim 3, characterized in that The capacitance of the capacitor C1 is consistent with the capacitance of the capacitor C3 , and the capacitance of the capacitor C2 is consistent with the capacitance of the capacitor C4 .

6. The time measurement unit according to any one of claims 1 to 5, characterized in that: The signal processing circuit includes a buffer BUFFER1, a buffer BUFFER2 and a subtractor. The buffer BUFFER1 is connected to the first sampling circuit and the subtractor. The buffer BUFFER2 is connected to the second sampling circuit and the subtractor. The subtractor is connected to the time measurement circuit.

7. The time measurement unit according to any one of claims 1 to 5, characterized in that: The time measurement circuit includes a first comparator, a second comparator, and a processor. The first comparator is connected to the signal processing circuit and the processor, and the second comparator is connected to the signal processing circuit and the processor.

8. The time measurement unit according to claim 7, characterized in that The time measurement circuit further includes a first digital-to-analog converter and a second digital-to-analog converter, wherein the first digital-to-analog converter is connected to the first comparator, and the second digital-to-analog converter is connected to the second comparator.

9. The time measurement unit according to claim 7, characterized in that The processor is FPGA, CPU or MCU.

10. A testing machine, characterized in that: The device comprises the time measurement unit according to any one of claims 1 to 9.

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