Micro-display device with surfaces with different coarsening degrees

Abstract

The utility model discloses a micro-display device with surfaces with different coarsening degrees, and relates to the technical field of semiconductors. The micro display device comprises a driving wafer; the display module is arranged on the driving wafer, the display module comprises at least one pixel unit, one surface, far away from the driving wafer, of the pixel unit is an epitaxial layer surface, and the epitaxial layer surface comprises a first part surface with a first coarsening degree and a second part surface with a second coarsening degree, the surface of the first part and the surface of the second part are covered with a continuous common cathode layer; wherein the first coarsening degree is greater than the second coarsening degree. Based on the technical scheme, good ohmic contact can be formed between the surface of the epitaxial layer with a light coarsening degree and the common cathode layer, so that the photoelectric conversion efficiency of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a micro display device with surfaces having different degrees of roughening. Background Art

[0002] MicroLEDs are the core chips for AR (augmented reality) and VR (virtual reality) devices. Compared to technologies like LCOS (liquid crystal on silicon) and OLED (organic light-emitting diodes), MicroLEDs are considered the optimal solution due to their high resolution, low power consumption, high brightness, and long lifespan. To meet the miniaturization, high resolution, and high brightness requirements of AR / VR, a Si-based GaN (gallium nitride) epitaxial structure combined with CMOS wafer-level bonding has become a preferred solution.

[0003] Photoelectric conversion efficiency is a key parameter in evaluating the performance of electroluminescent devices such as Micro LEDs. It is primarily determined by internal quantum efficiency (IQE) and light extraction efficiency (LEE). IQE is primarily determined by the epitaxial growth technology and the properties of the epitaxial material. For example, the IQE of LED chips made with GaN epitaxial material currently exceeds 90%, approaching the theoretical limit and with very limited room for improvement. LEE, on the other hand, is primarily determined by the chip's surface properties and structure. The refractive index of the epitaxial material differs significantly from that of the interface medium. Due to the Fresnel loss effect and the law of total internal reflection, photons within certain angles are totally reflected back into the semiconductor at the interface between the epitaxial material and the interface medium, significantly limiting the device's LEE. Currently, the LEE of Micro LED chips ranges from 10% to 60%, leaving significant room for improvement. Surface roughening, which creates a rough surface on the light-emitting unit (LE), enhances light extraction by increasing the scattering effect of the LEE surface and is considered an effective method for improving LEE.

[0004] However, when using dry or wet methods to roughen micro-display devices, slight lattice damage, changes in lattice element occupancy, and other abnormalities often occur on the surface of the epitaxial layer. In this case, the common cathode layer is in direct contact with the epitaxial layer with a roughened structure, which can easily cause the ohmic contact between the two to deteriorate, that is, lead to an increase in surface contact resistance, and then lead to an increase in device voltage, which is not conducive to improving the final photoelectric conversion efficiency. Utility Model Content

[0005] The purpose of the present invention is to provide a micro display device with surfaces having different degrees of roughening, which can form a good ohmic contact with a common cathode layer, thereby improving the photoelectric conversion efficiency of the device.

[0006] In order to achieve the above-mentioned purpose of the utility model, the utility model proposes the following technical solutions:

[0007] In one aspect, a micro-display device having a surface with different degrees of roughening is provided, the micro-display device comprising:

[0008] Driver wafer;

[0009] A display module, the display module being disposed on the driver wafer, the display module comprising at least one pixel unit, wherein a surface of the pixel unit away from the driver wafer is an epitaxial layer surface, the epitaxial layer surface comprising a first surface portion having a first roughening degree and a second surface portion having a second roughening degree, wherein a continuous common cathode layer is provided on the first surface portion and the second surface portion;

[0010] The first roughening degree is greater than the second roughening degree.

[0011] In a possible implementation, the first portion of the surface is located at an edge portion of the epitaxial layer surface;

[0012] The second portion of the surface is located in a middle portion of the surface of the epitaxial layer.

[0013] In a possible implementation, the pattern corresponding to the first surface portion includes any one of the following:

[0014] Round, square and special-shaped patterns.

[0015] In a possible implementation manner, a first partial passivation layer is provided between part of the first partial surface and the common cathode layer.

[0016] In a possible implementation, a second partial passivation layer is provided between the common cathode layer and the sidewall of the pixel unit, and the first partial passivation layer is connected to the second partial passivation layer.

[0017] In a possible implementation, the second portion of the surface accounts for 15% to 25% of the area of the epitaxial layer surface.

[0018] In a possible implementation, the roughened unit cell size corresponding to the first portion of the surface is between 600 nm and 1000 nm.

[0019] In a possible implementation, a roughened unit cell size corresponding to the second portion of the surface is between 0 nm and 100 nm.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] Provided is a micro-display device having surfaces with different degrees of roughening. Pixel units are fabricated on a driver wafer. The surface of an epitaxial layer of the pixel unit adopts a non-entire surface roughening design and is further divided into a first surface portion and a second surface portion. The roughening degree of the first surface portion is greater than that of the second surface portion. These two surface portions further form ohmic contact with a common cathode layer. Compared with a solution in which the entire epitaxial layer is roughened to the same degree, good ohmic contact can be formed with the common cathode layer through the surface portion of the epitaxial layer with a lesser degree of roughening.

[0022] Furthermore, the first portion of the surface with a higher degree of roughening is set in the edge area of the epitaxial layer surface, and the second portion of the surface with a lower degree of roughening is set in the middle area. The epitaxial layer surface under this design is in contact with the common cathode layer, so that the current can be conducted from the center of the pixel as much as possible, thereby reducing the brightness loss of the edge part and improving the brightness; and ensuring that the light output of each pixel is concentrated in the middle area, optimizing the light crosstalk problem; and reducing the edge non-radiative composite light emission, reducing the half-wave width, and improving the light purity; and avoiding the current accumulation at the edge, thereby improving the service life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 1 is a schematic structural diagram of a micro-display device with surfaces of different degrees of roughening provided in an embodiment of the present application;

[0024] Figure 2 1 is a schematic structural diagram of another micro-display device with surfaces of different degrees of roughening provided in an embodiment of the present application;

[0025] Figure 3 1 is a schematic structural diagram of another micro-display device with surfaces of different degrees of roughening provided in an embodiment of the present application;

[0026] Figure 4 1 is a schematic structural diagram of another micro-display device with surfaces of different degrees of roughening provided in an embodiment of the present application;

[0027] Figure 5 This is a method provided in the embodiment of the present application. Figure 1 Schematic diagram of the device shown with the addition of metal reinforcement structure;

[0028] Figure 6 This is a method provided in the embodiment of the present application. Figure 3 Schematic diagram of the device shown with the addition of metal reinforcement structure;

[0029] Figure 7 is a flow chart of a method for preparing a micro display device provided in an embodiment of the present application;

[0030] Figure 8 This is a method for Figure 1 The device shown is a schematic diagram of the process of secondary roughening of the epitaxial layer surface;

[0031] Figure 9 This is a method for Figure 2 The device shown is a schematic diagram of the process of secondary roughening of the epitaxial layer surface;

[0032] Figure 10 This is a method for Figure 3 The device shown is a schematic diagram of the process of partially roughening the surface of the epitaxial layer;

[0033] Figure 11 This is a method for Figure 4 Schematic diagram of the process of partially roughening the surface of the epitaxial layer of the device shown.

[0034] Reference numerals:

[0035] 100-driving wafer, 200-display module, 10-pixel unit, 20-epitaxial layer surface, 21-first part surface, 22-second part surface, 30-common cathode layer, 41-first part passivation layer, 42-second part passivation layer, 50-mask layer, 60-anode contact, 70-cathode wiring area, 80-metal reinforcement structure. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the present invention more clear, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0037] In the description of the present invention, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0038] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on specific circumstances.

[0039] In traditional roughening processes, surface roughening technology is mostly full-surface roughening, which easily causes lattice damage to the surface of the epitaxial layer during the roughening process, resulting in poor ohmic contact between the common cathode layer and the epitaxial layer with the roughened structure.

[0040] In order to avoid the above problems, in an embodiment of the present application, a technical solution is proposed for roughening the surface of the epitaxial layer of the pixel unit to varying degrees, leaving a portion of space with a lesser degree of roughening for forming a good ohmic contact with the common cathode layer.

[0041] Next, the device structure proposed in this application is described.

[0042] First, the present invention provides a micro display device with different degrees of roughening of the surface, such as Figures 1 to 4 As shown, the micro display device includes:

[0043] A driving wafer 100; a display module 200, wherein the display module 200 is disposed on the driving wafer 100, and the display module 200 includes at least one pixel unit 10, wherein the side of the pixel unit 10 away from the driving wafer 100 is an epitaxial layer surface 20, and the epitaxial layer surface 20 includes a first partial surface 21 having a first roughening degree, and a second partial surface 22 having a second roughening degree, and a continuous common cathode layer 30 is covered on the first partial surface 21 and the second partial surface 22; wherein the first roughening degree is greater than the second roughening degree.

[0044] In an embodiment of the present application, a display module 200 is arranged on a driver wafer 100, and a pixel unit 10 corresponding to the anode contact 60 in the driver wafer 100 is arranged in the display module 200. The side of the pixel unit 10 away from the driver wafer 100 is an epitaxial layer surface 20. The epitaxial layer surface 20 adopts a non-whole-surface roughening design, which is further divided into a first partial surface 21 and a second partial surface 22. The two partial surfaces correspond to different degrees of roughening, respectively. These two partial surfaces further form an ohmic contact with the common cathode layer 30. Compared with the scheme of roughening the entire surface of the epitaxial layer to the same degree, a good ohmic contact can be formed with the common cathode layer 30 through this part of the epitaxial layer surface 20 with a lighter degree of roughening.

[0045] It is understood that the second portion of the surface 22 having a second roughness with a lower roughness can be as follows: Figure 1 、 2 As shown, the surface is roughened, and it can also be Figure 3 、 4 As shown, the surface is not roughened.

[0046] The driver wafer 100 may be an active design that is a combination of one or more thin film transistors (TFTs), low temperature polysilicon (LTPS), CMOS integrated circuits, high mobility transistors (HEMTs), and the like. Specifically, the driver wafer 100 is provided with a driver circuit, and the driver circuit is provided with at least one anode contact 60. The driver circuit may include an active, passive, or semi-passive control circuit. All anode contacts 60 included in the driver circuit may be arranged linearly or in an array, and any anode contact 60 may be located in the middle or at the edge of the driver wafer 100. This embodiment does not impose any restrictions on this.

[0047] The anode contacts 60 in the driver wafer 100 and the pixel units 10 may be in a one-to-one correspondence or a many-to-one correspondence, which is not limited in this application. In addition, in addition to the anode contacts 60, the driver wafer 100 may further include cathode contacts, and the common cathode layer 30 is also connected to the cathode contacts to form a cathode circuit for the pixel units 10. Figure 1 、 Figure 3 As shown, the driver wafer 100 may include only the anode contact 60, or, as shown in FIG. Figure 2 、 Figure 4 As shown, the driver wafer 100 may further include a cathode wiring region 70 , which may be a cathode grid or a cathode contact. The common cathode layer 30 is in contact with the cathode wiring region 70 .

[0048] In addition, for the driver wafer 100 including only the anode contact 60, a metal reinforcement structure 80 may be further provided on the common cathode layer 30 to increase the current expansion capability of the common cathode layer 30, for example, Figure 1 The device shown in FIG. 1 is provided with a metal reinforcement structure 80. Figure 5 The structure shown is for Figure 3 The device shown in FIG. 1 is provided with a metal reinforcement structure 80. Figure 6 The structure shown.

[0049] Among them, the degree of coarsening can be measured by the parameter of coarsening cell size, and the value of coarsening cell size is positively correlated with the degree of coarsening. The larger the value of coarsening cell size, the stronger the degree of coarsening. Therefore, the first degree of coarsening is greater than the second degree of coarsening, which can also be understood as the coarsening cell size corresponding to the first part surface 21 is greater than the coarsening cell size corresponding to the second part surface 22.

[0050] Among them, the common cathode layer 30 can use a transparent conductive film, which can be a combination of one or more of an ITO (Indium Tin Oxide) film, an AZO (Antimony doped Zinc Oxide) film, an ATO (Antimony doped Tin Oxide) film, and an FTO (Fluorine doped Tin Oxide) film. The transparent conductive film can also be a metal-doped ITO formed by annealing after plating a thin metal (such as Al, Au, Ag) on the ITO surface to enhance the current transmission capability of the common cathode layer 30.

[0051] In one possible implementation, Figures 1 to 6 As shown, the first portion surface 21 is located at the edge of the epitaxial layer surface 20 ; the second portion surface 22 is located at the middle of the epitaxial layer surface 20 .

[0052] In this implementation, the specific positions of the partial surfaces with different degrees of roughening in the epitaxial layer surface 20 are designed, the edge area is designed to have a higher degree of roughening (i.e., the first partial surface 21), and the middle area is designed to have a lower degree of roughening (i.e., the second partial surface 22).

[0053] Understandably, as Micro LEDs shrink in size, they can be considered to have significant edge effects. Specifically, the sidewall damage left by the etching process introduces a large number of surface defects, forming channels for non-radiative recombination on the surface, resulting in the following adverse effects:

[0054] (1) Brightness reduction problem: Sidewall damage leads to non-radiative recombination on the surface, reducing the effective emission of photons and thus reducing the brightness of the chip;

[0055] (2) Optical crosstalk: As chip size decreases, the density of pixel light sources increases, and the optical crosstalk problem between pixels becomes more serious;

[0056] (3) Wavelength consistency and stability issues: To achieve high-quality display requirements, the blue, green, and red LEDs must have consistent wavelengths and narrow half-peak widths, meaning purer colors. Non-radiative recombination in the edge regions not only reduces brightness but also generates light outside the target wavelength, increasing the half-wavelength width.

[0057] (4) Lifespan issue: Mainly in high current application scenarios, the pixel unit 10 is prone to edge current accumulation, which seriously affects the device's light efficiency and service life.

[0058] Therefore, in this implementation, the edge area of the epitaxial layer surface 20 is further roughened, and the degree of roughening in the middle area is reduced. The epitaxial layer surface 20 under this design is in contact with the common cathode layer 30, so that the current can be conducted from the center of the pixel as much as possible, thereby reducing the brightness loss of the edge part and improving the brightness; and ensuring that the light output of each pixel is concentrated in the middle area, optimizing the light crosstalk problem; and reducing the edge non-radiative composite light emission, reducing the half-wave width, and improving the light purity; and avoiding the current accumulation at the edge, thereby improving the service life of the device.

[0059] Furthermore, the pattern corresponding to the first surface portion 21 includes any one of the following: a circular pattern, a square pattern, and a special-shaped pattern. Accordingly, the second surface portion 22 is the surface area of the epitaxial layer surface 20 excluding the first surface portion 21 .

[0060] Furthermore, a first partial passivation layer 41 is provided between the first partial surface 21 and the common cathode layer 30. Figures 1 to 6 As shown, a first partial passivation layer 41 is provided in an area of the first partial surface 21 close to the side wall of the pixel unit 10. The first partial passivation layer 41 isolates part of the first partial surface 21 from the common cathode layer 30, thereby further avoiding poor ohmic contact between the two, resulting in an increase in surface contact resistance, and further causing the problem of increased device voltage.

[0061] In addition, a second partial passivation layer 42 is provided between the common cathode layer 30 and the sidewall of the pixel unit 10, and the first partial passivation layer 41 is connected to the second partial passivation layer 42. Figures 1 to 6 As shown, a second partial passivation layer 42 is attached to the side wall of the pixel unit 10 for insulating and passivating the pixel unit 10. When the first partial passivation layer 41 is arranged in an area close to the side wall of the pixel unit 10 in the first partial surface 21, the first partial passivation layer 41 and the second partial passivation layer 42 are connected and arranged accordingly.

[0062] The first partial passivation layer 41 and the second partial passivation layer 42 may be a single layer or a stack of insulating dielectric layers such as aluminum oxide, silicon nitride, or silicon oxide.

[0063] In a possible implementation, the second portion of the surface 22 accounts for 15% to 25% of the area of the epitaxial layer surface 20 .

[0064] In this implementation, in order to ensure that roughening improves brightness and that the common cathode layer 30 has good ohmic contact with the epitaxial layer surface 20, the area of the second portion of the surface 22 with a lighter degree of roughening is limited to the range of 15% to 25% of the area of the top of the pixel. While avoiding the situation where the area of the second portion of the surface 22 is too small, resulting in insufficient ohmic contact area and voltage increase, it also avoids the situation where the area of the second portion of the surface 22 is too large, resulting in insufficient roughening area to improve brightness.

[0065] In a possible implementation, the size of the roughened unit cell corresponding to the first surface portion 21 is between 600 nm and 1000 nm. With a larger size of the roughened unit cell, the light path is more likely to be refracted out rather than reflected back into the interior of the pixel unit 10 .

[0066] In a possible implementation, the size of the roughened unit cell corresponding to the second portion of the surface 22 is between 0 nm and 100 nm. The smaller size of the roughened unit cell can avoid affecting the ohmic contact.

[0067] In summary, the embodiments of the present application provide a micro-display device having surfaces with different degrees of roughening, in which pixel units are prepared on a driving wafer, and the surface of the epitaxial layer of the pixel unit adopts a non-whole-surface roughening design, which is further divided into a first part surface and a second part surface. The roughening degree of the first part surface is greater than the roughening degree of the second part surface. These two parts of the surface further form an ohmic contact with the common cathode layer. Compared with the scheme of roughening the entire surface of the epitaxial layer to the same degree, a good ohmic contact can be formed with the common cathode layer through the surface of the epitaxial layer with a lighter degree of roughening.

[0068] Furthermore, the first portion of the surface with a higher degree of roughening is set in the edge area of the epitaxial layer surface, and the second portion of the surface with a lower degree of roughening is set in the middle area. The epitaxial layer surface under this design is in contact with the common cathode layer, so that the current can be conducted from the center of the pixel as much as possible, thereby reducing the brightness loss of the edge part and improving the brightness; and ensuring that the light output of each pixel is concentrated in the middle area, optimizing the light crosstalk problem; and reducing the edge non-radiative composite light emission, reducing the half-wave width, and improving the light purity; and avoiding the current accumulation at the edge, thereby improving the service life of the device.

[0069] Next, the preparation method of the micro display device corresponding to the structure described in the above embodiment is described. Figure 7 As shown, the method for preparing a micro display device may include the following steps:

[0070] Step S1: Prepare the driving wafer.

[0071] Specifically, the driver wafer includes anode contacts in a vertical direction, and an insulating medium is provided around the anode contacts.

[0072] Step S2: preparing at least one pixel unit on the driver wafer, wherein a surface of the pixel unit away from the driver wafer is the surface of the epitaxial layer.

[0073] The specific preparation process of the pixel unit can be as follows:

[0074] (1) The compound wafer and the driver wafer are bonded and integrated through a bonding metal layer.

[0075] Specifically, bonding metal is deposited on the surfaces of the compound wafer and the driver wafer. At this time, the bonding metal on the surfaces of the two wafers is used to form a bonding metal layer, and the two wafers are integrated together through wafer-level hot pressing bonding.

[0076] For example, the compound wafer adopts the following structure for illustration. Practical applications include but are not limited to this structure. In some practical applications, the film layers of the compound wafer may be more complex, or there may be cross-use of materials. Typically, the compound wafer mainly includes P-type material, N-type material, and MQW active quantum wells and other functional layers sandwiched between the two:

[0077]

[0078] (2) The compound wafer is patterned and etched to obtain pixel units.

[0079] Specifically, after exposing the N-type ohmic contact layer in the compound wafer, the compound wafer is patterned and pixel-formed by using the semiconductor photolithography and etching process with the P-type ohmic contact layer in the compound wafer as the etching stop layer, and the prepared pixel unit corresponds to the anode contact in the driving wafer, and the following is obtained: Figure 5 or Figure 6 The structure shown.

[0080] Step S3: roughening the surface of the epitaxial layer of the pixel unit to form a first surface portion with a first roughening degree and a second surface portion with a second roughening degree, wherein the first roughening degree is greater than the second roughening degree.

[0081] In a possible implementation, the surface of the epitaxial layer is roughened twice to have different degrees of roughening. Figure 8 As shown, it shows the Figure 1 The device shown in FIG1 is a process of secondary roughening of the epitaxial layer surface, thereby having different degrees of roughening; Figure 9 As shown, it shows the Figure 2 The device shown is a process in which the epitaxial layer surface is roughened twice, resulting in different degrees of roughening.

[0082] Specifically, step S3 may include:

[0083] (1) The surface of the epitaxial layer is roughened for the first time, and the surface of the epitaxial layer is roughened to a second roughening degree.

[0084] Specifically, the surface of the epitaxial layer is roughened by a dry method or a wet method, and the surface of the pixel unit is roughened to a second roughening degree, which is lighter than the first roughening degree.

[0085] Among them, wet roughening can be performed by using KOH, H3PO4, NH3F, CH3COOH and various mixed roughening solutions, and dry roughening can be performed by using plasma gases such as Cl2, BCl3, HBr, Ar, etc. to etch the surface of the epitaxial layer.

[0086] (2) A first portion of the surface of the epitaxial layer is roughened for the second time to a first degree of roughening, and a portion of the surface of the epitaxial layer other than the first portion is the second portion of the surface.

[0087] Specifically, a second roughening is performed on a first portion of the surface of the epitaxial layer to roughen the surface to a first roughening degree, where the first roughening degree is heavier than the second roughening degree.

[0088] The above steps may specifically include:

[0089] (2.1) Performing corresponding patterned masking on the second portion of the surface to form a mask layer.

[0090] Specifically, a mask layer is formed on the second portion of the surface to prevent the second portion of the surface from being further roughened secondary, and the secondary roughening is limited to the first portion of the surface.

[0091] Among them, the mask layer can be completed by mask blocking, and the mask material used includes but is not limited to photoresist, silicon dioxide, aluminum oxide, etc.; the mask layer can also be completed by self-assembly, and a solution containing nano or micro and micro particles is spin-coated on the surface of the epitaxial layer for masking, such as using a solution containing SiO2, PS (polystyrene), PVP (polyvinyl pyrrolidone) and other micro particles for spin coating to form a nano array with uniform spacing, and this nano array can be used as a mask layer.

[0092] (2.2) Performing dry roughening or wet roughening on the remaining first portion of the surface to roughen the first portion of the surface to a first roughening degree.

[0093] Specifically, due to the existence of the mask layer, only the remaining first portion of the surface will be roughened during the secondary roughening, and the first portion of the surface will be roughened to a first roughening degree with a higher roughening degree.

[0094] Among them, wet roughening can be performed by using KOH, H3PO4, NH3F, CH3COOH and various mixed roughening solutions, and dry roughening can be performed by using plasma gases such as Cl2, BCl3, HBr, Ar, etc. to etch the surface of the epitaxial layer.

[0095] (2.3) Remove the mask layer.

[0096] The mask layer may be removed by wet chemical solution or dry bombardment, and the present application does not impose any limitation on the specific method of removing the mask layer.

[0097] In another possible implementation, the epitaxial layer surface includes a roughened first surface portion and an unroughened second surface portion, thereby having different degrees of roughening. Figure 10 As shown, it shows the Figure 3 The device shown in FIG. 1 is a process of partially roughening the surface of the epitaxial layer to have different degrees of roughening; Figure 11 As shown, it shows the Figure 4 The device shown is a process of partially roughening the surface of the epitaxial layer to have different degrees of roughening.

[0098] Specifically, step S3 may include:

[0099] (1) A first portion of the surface of the epitaxial layer is roughened to a first roughening degree, and the remaining second portion of the surface is not roughened and corresponds to a second roughening degree.

[0100] Specifically, only a first portion of the surface of the epitaxial layer is roughened to a first roughening degree, while a second portion of the surface is not roughened.

[0101] The above steps may specifically include:

[0102] (1.1) Performing corresponding patterned masking on the second portion of the surface to form a mask layer.

[0103] Specifically, a mask layer is formed on the second portion of the surface to prevent the second portion of the surface from being subsequently roughened, and the roughening is limited to the first portion of the surface.

[0104] Among them, the mask layer can be completed by mask blocking, and the mask material used includes but is not limited to photoresist, silicon dioxide, aluminum oxide, etc.; the mask layer can also be completed by self-assembly, and a solution containing nano or micro and micro particles is spin-coated on the surface of the epitaxial layer for masking, such as using a solution containing SiO2, PS (polystyrene), PVP (polyvinyl pyrrolidone) and other micro particles for spin coating to form a nano array with uniform spacing, and this nano array can be used as a mask layer.

[0105] (1.2) performing dry roughening or wet roughening on the remaining surface of the first portion to roughen the surface of the first portion to a first roughening degree.

[0106] Specifically, due to the existence of the mask layer, only the remaining first portion of the surface is roughened during the roughening process, and the first portion of the surface is roughened to a first roughening degree, while the second portion of the surface is not roughened.

[0107] Among them, wet roughening can be performed by using KOH, H3PO4, NH3F, CH3COOH and various mixed roughening solutions, and dry roughening can be performed by using plasma gases such as Cl2, BCl3, HBr, Ar, etc. to etch the surface of the epitaxial layer.

[0108] (1.3) Remove the mask layer.

[0109] The mask layer may be removed by wet chemical solution or dry bombardment, and the present application does not impose any limitation on the specific method of removing the mask layer.

[0110] Step S4: a continuous common cathode layer is provided on the first partial surface and the second partial surface.

[0111] Specifically, a continuous common cathode layer is formed on the first partial surface and the second partial surface by depositing a transparent conductive film, thereby forming an ohmic contact with the pixel unit.

[0112] In one possible implementation, before step S4, the following steps are further performed: an insulating dielectric is deposited on the surface of the pixel unit to form a second partial passivation layer attached to the side wall of the pixel unit and a first partial passivation layer on a portion of the upper surface of the pixel unit.

[0113] In this implementation, before preparing the common cathode layer, the pixel unit is first insulated and passivated to form a second partial passivation layer attached to the side wall of the pixel unit and a first partial passivation layer on a portion of the upper surface of the pixel unit. This first partial passivation layer can isolate the common cathode layer and a portion of the first partial surface, thereby further avoiding poor ohmic contact between the two, resulting in an increase in surface contact resistance, and further leading to the problem of increased device voltage.

[0114] In summary, the preparation method of the micro display device provided in the embodiment of the present application prepares pixel units on a driving wafer, and the surface of the epitaxial layer of the pixel unit adopts a non-whole-surface roughening design, which is further divided into a first part surface and a second part surface. The roughening degree of the first part surface is greater than the roughening degree of the second part surface. These two parts of the surface further form an ohmic contact with the common cathode layer. Compared with the scheme of roughening the entire surface of the epitaxial layer to the same degree, a good ohmic contact can be formed with the common cathode layer through this part of the epitaxial layer surface with a lighter degree of roughening.

[0115] All of the above optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the scope of protection of this application and will not be described in detail here.

[0116] It should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A micro-display device having a surface with different degrees of roughening, characterized in that: The micro display device comprises: Driver wafer; A display module, the display module being disposed on the driver wafer, the display module comprising at least one pixel unit, wherein a surface of the pixel unit away from the driver wafer is an epitaxial layer surface, the epitaxial layer surface comprising a first surface portion having a first roughening degree and a second surface portion having a second roughening degree, wherein a continuous common cathode layer is provided on the first surface portion and the second surface portion; The first roughening degree is greater than the second roughening degree.

2. The micro display device according to claim 1, characterized in that The first portion of the surface is located at an edge portion of the epitaxial layer surface; The second portion of the surface is located in a middle portion of the surface of the epitaxial layer.

3. The micro display device according to claim 2, characterized in that The pattern corresponding to the surface of the first portion includes any one of the following: Circle and square patterns.

4. The micro display device according to claim 2, wherein: A first partial passivation layer is provided between the first partial surface and the common cathode layer.

5. The micro display device according to claim 4, characterized in that: A second partial passivation layer is provided between the common cathode layer and the sidewall of the pixel unit, and the first partial passivation layer is connected to the second partial passivation layer.

6. The micro display device according to claim 1, wherein: The second portion of the surface accounts for 15% to 25% of the area of the epitaxial layer surface.

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