Packaging structure

Abstract

The utility model provides a packaging structure, which is applied to the technical field of semiconductors. In the packaging structure provided by the utility model, the partition shielding spacer is located between the adjacent chip assemblies arranged along the first direction, the partition shielding spacer comprises a plurality of shielding wire arcs, and each shielding wire arc is provided with a first wire arc section and a second wire arc section which extend along different directions and are connected with each other. Therefore, partition shielding is realized by arranging the partition shielding spacer between the adjacent chip assemblies, the area of the substrate occupied by the partition shielding device is reduced, the electromagnetic shielding effect is realized, the packaging process is simplified, the manufacturing period is shortened, and the purposes of reducing the cost and improving the yield are facilitated.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a packaging structure. Background Art

[0002] In existing system-level packaging (SLP) module structures, electromagnetic shielding structures are required to prevent electromagnetic interference between chips and components. Existing partitioned EMI shielding technologies (electromagnetic shielding technologies) typically employ metal pillars between components, metal trenches within the plastic package, or vertical metal wires between components. However, these various EMI shielding implementations suffer from complex packaging processes, long production cycles, high costs, and poor shielding effectiveness, resulting in ineffective electromagnetic shielding. Utility Model Content

[0003] The purpose of the present utility model is to provide a packaging structure, and specifically proposes a partition shielding spacer formed only by wire bonding, which can serve as an electromagnetic shielding wall between adjacent chip components to achieve an electromagnetic shielding effect, and simplifies the packaging process and shortens the production cycle, which is conducive to reducing costs and improving yields.

[0004] In order to achieve the above-mentioned purpose, the present invention provides a packaging structure, which may specifically include:

[0005] substrate;

[0006] A plurality of chip components are arranged on the surface of the substrate and spaced apart from each other along a first direction;

[0007] A plurality of partitioned shielding spacers are located between adjacent chip components, and the partitioned shielding spacers include a plurality of shielding arcs extending along the second direction, each of the shielding arcs having a first arc segment and a second arc segment extending in different directions and connected to each other;

[0008] A plastic packaging layer is located on the substrate and wraps the plurality of chip components and the plurality of partition shielding spacers.

[0009] In some optional examples, the first line arc segment extends along the second direction, and the second line arc segment extends along a third direction; wherein the first direction is perpendicular to the second direction, and the third direction is perpendicular to the plane in which the first direction and the second direction are located.

[0010] In some optional examples, the first line arc segment extends along the second direction, the second line arc segment extends along a fourth direction, the fourth direction is located between the third direction and the first direction, and the angle formed with the third direction is less than 90 degrees.

[0011] In some optional examples, a first arc segment of at least one of the shielding arcs of the partitioned shielding spacer intersects with a second arc segment of another shielding arc.

[0012] In some optional examples, an angle is provided between the first arc segment of the shielding arc and the second arc segment connected thereto, and the angle is a right angle.

[0013] In some optional examples, a top surface of a first arc segment of at least one of the shielding arcs of the partitioned shielding spacer is higher than a top surface of the plastic packaging layer.

[0014] In some optional examples, the packaging structure may further include:

[0015] A plurality of grounding pads are located on the substrate, and at least one grounding pad is provided on the substrate between adjacent chip components.

[0016] In some optional examples, a grounding pad is provided on the substrate between adjacent chip components, and all the shielding wire arcs of the partitioned shielding spacers located between the adjacent chip components are formed on the same grounding pad in a wire bonding manner.

[0017] In some optional examples, a plurality of grounding pads are provided on the substrate between adjacent chip components, and some of the shielding wire arcs of the partitioned shielding spacers located between the adjacent chip components are formed on the same grounding pad in a wire bonding manner.

[0018] In some optional examples, a plurality of the grounding pads are provided on the substrate between adjacent chip components, and the two welding points of at least one of the shielding wire arcs of the partitioned shielding spacer located between the adjacent chip components are distributed on different grounding pads.

[0019] In some optional examples, projections of at least some of the shielding wire arcs and their corresponding welding points of the partitioned shielding spacer in the first direction respectively overlap.

[0020] In some optional examples, the projection shape of at least part of the shielding wire arcs of the partitioned shielding spacer in the first direction is an arc shape.

[0021] In some optional examples, the arc-shaped projection of at least part of the shielding line arc of the partitioned shielding spacer in the first direction at least partially overlaps with the projection of the chip component in the first direction.

[0022] In some optional examples, the packaging structure further includes:

[0023] The metal shielding layer is arranged outside the plastic packaging layer and is in direct contact with at least one of the shielding wire arcs of the partition shielding spacer.

[0024] In some optional examples, the material of the shielding wire arc includes metal, and the metal is gold or copper.

[0025] In some optional examples, the chip assembly is a flip chip, a chip or a component, and the chip includes at least one of a filter chip, a duplexer chip and a multiplexer chip, and a power amplifier chip.

[0026] Compared with the prior art, the present invention has at least the following technical effects:

[0027] In the packaging structure provided by the present invention, partitioned shielding is achieved by arranging a partitioned shielding spacer having a first line arc segment and a second line arc segment extending in different directions and connected to each other between adjacent chip components, thereby reducing the area of ​​the substrate occupied by the partitioned shielding device, and the component that plays a shielding role in the partitioned shielding spacer is a shielding line arc with both a horizontal width and a vertical width formed only by a wire bonding method. That is, while achieving the electromagnetic shielding effect, it also achieves the purpose of simplifying the packaging process and shortening the production cycle, and ultimately helps to reduce costs and improve yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the present application but do not constitute a limitation of the present application. In the accompanying drawings:

[0029] Figure 1 This is an example diagram of a packaging structure provided in an embodiment of the present invention when the adjacent chip components 200 are flip chips and chips or components electrically connected to the substrate 100 through surface mounting technology;

[0030] Figure 2 This is an example diagram of a packaging structure provided in an embodiment of the present invention when all adjacent chip components 200 are flip-chips;

[0031] Figure 3 This is an example diagram of a packaging structure provided in an embodiment of the present invention when all adjacent chip assemblies 200 are chips or components electrically connected to the substrate 100 through surface mount technology;

[0032] Figure 4 For Figure 1 An exemplary diagram of a packaging structure after a metal shielding layer 600 is added;

[0033] Figure 5 For Figure 2An exemplary diagram of a packaging structure after a metal shielding layer 600 is added;

[0034] Figure 6 For Figure 3 An exemplary diagram of a packaging structure after a metal shielding layer 600 is added;

[0035] Figure 7 for Figure 2 A partial exemplary diagram of the package structure shown is projected in the first direction D1;

[0036] Figure 8 for Figure 3 A partial exemplary diagram of the package structure shown is projected in the first direction D1;

[0037] Figure 9 This is an exemplary diagram of the cross-sectional structure of the partition shielding spacer 300 provided in an embodiment of the present utility model in the second direction D2;

[0038] Figure 10 This is an exemplary diagram of the cross-sectional structure of the partition shielding spacer 300 provided in an embodiment of the present utility model in the second direction D2;

[0039] Figure 11 This is an exemplary diagram of the cross-sectional structure of the partition shielding spacer 300 provided in an embodiment of the present utility model in the second direction D2;

[0040] Figure 12 This is an exemplary diagram of the cross-sectional structure of the partition shielding spacer 300 provided in an embodiment of the present utility model in the second direction D2;

[0041] Figure 13 This is an exemplary diagram of the cross-sectional structure of the partition shielding spacer 300 provided in an embodiment of the present utility model in the second direction D2;

[0042] Figure 14 This is an exemplary diagram of the cross-sectional structure of the partition shielding spacer 300 provided in an embodiment of the present utility model in the second direction D2;

[0043] Figure 15 This is an exemplary diagram of the cross-sectional structure of the partition shielding spacer 300 provided in an embodiment of the present utility model in the second direction D2;

[0044] Figure 16 for Figure 15 An exemplary diagram of a partitioned shielding spacer 300 projected in a first direction D1 is shown.

[0045] Wherein, the accompanying drawings are marked as follows:

[0046] 10-Packaging structure; 100-Substrate; 200-Chip assembly; 300-Partition shielding spacer; 310-Shielding wire arc; 310.1-First wire arc segment of the shielding wire arc; 310.2-Second wire arc segment of the shielding wire arc; 320-Solder point; 400-Ground pad; 500-Plastic encapsulation layer; 600-Metal shielding layer; D1-First direction; D2-Second direction; D3-Third direction; D4-Fourth direction.

[0047] In the drawings, like components are given like reference numerals, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0048] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] The terms used in this utility model are for the purpose of describing specific embodiments only and are not intended to limit this utility model. Unless otherwise defined in this application document, technical or scientific terms used in this utility model should have the ordinary meaning understood by a person of ordinary skill in the art to which this utility model belongs. The terms "first," "second," and similar terms used in this utility model specification and claims do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not indicate a limitation of quantity, but rather indicate the presence of at least one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "upper / upper layer" and / or "lower / lower layer" are for convenience only and are not limited to a single position or spatial orientation. Terms such as "include" or "comprising" mean that the elements or structures preceding "include" or "comprising" include the elements or structures listed after "include" or "comprising" and their equivalents, and do not exclude other elements or structures. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can also include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0050] For ease of unified description, the present invention defines a first direction, a second direction, and a third direction hereinafter, and defines directions D1, D2, D3, and D4 in the accompanying drawings of the specification, wherein the first direction corresponds to D1 in the accompanying drawings of the specification (hereinafter referred to as the first direction D1), which is a direction parallel to the surface of a substrate, wherein the substrate is a substrate material used to form the packaging structure proposed by the present invention; the second direction corresponds to D2 in the accompanying drawings of the specification (hereinafter referred to as the second direction D2), which is perpendicular to the first direction D1, and the plane in which the second direction D2 and the first direction D1 lie is parallel to the surface of the substrate; the third direction corresponds to D3 in the accompanying drawings of the specification (hereinafter referred to as the third direction D3), which is perpendicular to both the second direction D2 and the first direction D1, and the third direction D3 and the second direction D2 are located in the same plane; the fourth direction corresponds to D4 in the accompanying drawings of the specification (hereinafter referred to as the fourth direction D4), which is between the third direction D3 and the first direction D1, and forms an angle with the third direction D3 or the first direction D1, and the angle is less than 90 degrees.

[0051] The core idea of ​​the present invention is to provide a packaging structure and specifically propose a partition shielding spacer formed only by wire bonding, which can serve as an electromagnetic shielding wall between adjacent chip components to achieve an electromagnetic shielding effect, and simplify the packaging process and shorten the production cycle, which is conducive to reducing costs and improving yields.

[0052] For details, please refer to Figure 1 , Figure 1 This is a schematic diagram of the packaging structure provided in an embodiment of the present utility model.

[0053] like Figure 1 As shown, in an embodiment of the present invention, the packaging structure 10 includes: a substrate 100, a plurality of chip components 200, a plurality of partition shielding spacers 300, a plurality of grounding pads 400, and a plastic layer 500 located on the substrate 100 and wrapping the plurality of chip components 200 and the plurality of partition shielding spacers 300.

[0054] In this embodiment, the substrate 100 is any suitable substrate material known in the art, for example, it can be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited to this. The material of the shielding wire arc includes metal, and the metal is gold or copper, but not limited to this. The material of the plastic encapsulation layer 500 includes but is not limited to epoxy resin.

[0055] The chip assembly 200 can specifically be a flip chip, a chip or a component, and the chip includes at least one of a filter chip, a duplexer chip and a multiplexer chip and a power amplifier chip, and the electrical connection method between the multiple chip assemblies 200 and the substrate 100 can be a commonly used semiconductor packaging process such as WB (wire bonding), FC (flip chip) or SMT (surface mount technology).

[0056] The multiple chip components 200 can be specifically arranged on the surface of the substrate 100 along the first direction D1, and a partition shielding spacer 300 is respectively arranged between two adjacent chip components 200. The partition shielding spacer 300 is extended along the second direction D2 and is grounded and conductive through the grounding pad 400 located on the substrate 100. The plastic encapsulation layer 500 is located on the substrate 100 and wraps the multiple chip components 200 and the multiple partition shielding spacers 300.

[0057] See also Figures 2 and 3 , and combined with Figure 1 , Figures 1 to 3 1 and 2 show various exemplary package structures when the package structure 10 includes different types of chip components 200. Figures 1 to 3 As shown, when the chip assembly 200 is a flip chip, it can be electrically connected to the substrate 100 through solder balls or solder columns. When the chip assembly 200 is electrically connected to the substrate 100 through surface mounting technology, some components in the chip assembly 200 also need to be connected to the ground pads on the substrate 100 through metal wire arcs through connecting pads (such as pads located on the chip assembly 200). It should be understood that the embodiment of the present invention shown in FIG. Figures 1 to 3 Only two chip assemblies 200 spaced apart from each other along the first direction D1 are shown for exemplary purposes. In other embodiments, three or more chip assemblies 200 may be included, and the present invention is not limited thereto.

[0058] Furthermore, each of the partitioned shielding spacers 300 may include a plurality of shielding arcs 310 extending as a whole along the second direction D2, and each shielding arc 310 includes a first arc segment and a second arc segment extending in different directions and connected to each other, and the angle between the connected first arc segment and the second arc segment may be ≤90 degrees. Preferably, the angle between the first arc segment of the shielding arc 310 and the second arc segment connected thereto is 90 degrees (a right angle). Specifically, the first arc segment may extend along the second direction D2, and the second arc segment may extend along a third direction D3, or the first arc segment may extend along the second direction D2, and the second arc segment may extend along a fourth direction D4. Furthermore, the extension direction and length of the first arc segment and the second arc segment in the plurality of shielding arcs 310 in each of the partitioned shielding spacers 300 may be the same or different, but are not limited thereto. At the same time, there may be some intersections between the multiple shielding wire arcs 310 in each of the partitioned shielding spacers 300, such as the first wire arc segment of the shielding wire arc 310 intersecting with the second wire arc segment of another shielding wire arc, or the shielding wire arcs 310 may not intersect with each other, but this is not limited to.

[0059] It should be understood that since the partition shielding spacer 300 in the embodiment of the present invention is extended along the second direction D2 and arranged between two adjacent chip components 200, the cross-sectional structure obtained along the first direction D1 is Figures 1 to 3 Only a portion of the shielding arc 310 and the corresponding ground pad 400 can be seen when all the welding points of all the shielding arcs 310 in the partitioned shielding spacer 300 are located on the same straight line extending along the second direction D2. Since the first arc segment of the shielding arc 310 extends along the second direction D2, and the second arc segment can extend along the third direction D3 or the fourth direction D4, Figure 1 3 is a schematic structural diagram of the first arc segment of each shielding arc 310 in the partition shielding spacer 300 extending along the second direction D2 and the second arc segment thereof extending along the third direction D3 in the first direction D1. Figure 2 and Figure 3 : is a schematic structural diagram in the first direction D1 when the first arc segment of each shielding arc 310 in the partitioned shielding spacer 300 extends along the second direction D2, and the second arc segment thereof extends along the fourth direction D4, and the angles between the fourth direction D4 and the second direction D2 extended by the second arc segments of some of the shielding arcs 310 are different, wherein Figure 2 and Figure 3 The difference is that the lengths of the second arc segments of the plurality of shielding arcs 310 in the fourth direction D4 are different, and Figure 3The top surface of the second arc segment of at least one shielding arc 310 in the fourth direction D4 is higher than the top surface of the plastic layer 500 .

[0060] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the package structure 10 of the present invention may also have other aspects and is not limited to the above. The following will further describe other embodiments or variations of the package structure 10 of the present invention. In order to simplify the description, the following description mainly details the differences between the embodiments and does not repeat the similarities. In addition, the same components in the various embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the various embodiments.

[0061] See also Figures 4 to 6 , Figures 4 to 6 For Figures 1 to 3 The package structure 10 shown in the figure is provided with three exemplary figures after the metal shielding layer 600 is added. Figures 4 to 6 As shown in the figure, the packaging structure 10 in the embodiment of the present invention is similar to the above-mentioned embodiments 1 to 3. Figure 3 The structure of the packaging structure 10 in the corresponding embodiment is substantially the same, such as also including: a substrate 100, a plurality of chip components 200, a plurality of partition shielding spacers 300, a plurality of grounding pads 400, and a plastic layer 500 located on the substrate 100 and wrapping the plurality of chip components 200 and the plurality of partition shielding spacers 300. The same parts are not repeated here. The main difference between the packaging structure 10 of this embodiment and the aforementioned embodiment is that the packaging structure 10 also includes: a metal shielding layer 600 covering the outside of the plastic layer 500. In addition, the top surface of the first line arc segment of the shielding wire arc 310 in the partition shielding spacer 300 extending along the second direction D2 may be higher than the top surface of the metal shielding layer 600, such as Figure 6 As shown, it may also be lower than the top surface of the metal shielding layer 600, such as Figure 5 As shown, it may also be flush with the top surface of the plastic packaging layer 500 , thereby directly contacting the metal shielding layer 600 , but the present invention is not limited thereto.

[0062] It should be noted that when the second arc segment of the shielding arc 310 extends along the fourth direction D4, different lengths of the second arc segment will result in different projections of the partitioned shielding spacer 300 in the first direction D1. Figure 7 or Figure 8As shown, when the second arc segments of the plurality of shielding arcs 310 of the partitioned shielding spacer 300 extend along the fourth direction D4, the projection shape of each shielding arc 310 in the first direction D1 may be an arc, but is not limited thereto. Furthermore, the arc-shaped projections of the plurality of shielding arcs 310 of the partitioned shielding spacer 300 may at least partially overlap with the projection of the chip assembly 200 in the first direction D1, as shown in FIG. Figure 8 As shown, it can also be non-overlapping, such as Figure 7 As shown, but not limited to.

[0063] For ease of understanding, the following will take the extension of the second line arc segment along the third direction D3 as an example, and combine with the schematic diagram of the cross-sectional structure of the partition shielding spacer 300 in the second direction D2 to introduce various examples of the partition shielding spacer 300 provided by the present invention.

[0064] See also Figures 9 to 14 , Figures 9 to 14 These are various exemplary views of the cross-sectional structure of the partition shielding spacer 300 in the second direction D2 provided in the embodiment of the present invention, such as Figures 9 to 14 As shown, the partitioned shielding spacer 300 provided in the embodiment of the present invention includes a plurality of shielding wire arcs 310 extending along the second direction D2, and each of the shielding wire arcs 310 has a first wire arc segment 310.1 extending along the second direction D2 and a second wire arc segment 310.2 extending along the third direction D3 and adjacent to the first wire arc segment 310.1, so that each of the shielding wire arcs 310 has a certain height in the second direction D2 and the third direction D3, thereby improving the density of the shielding wire arcs 310 in the partitioned shielding spacer 300 and enhancing the electromagnetic shielding effect of the partitioned shielding spacer 300.

[0065] In an embodiment of the present invention, an angle is provided between the first arc segment 310.1 of the shielding wire arc 310 and the second arc segment 310.2 adjacent thereto, and the angle is a right angle, so that the structure formed by each shielding wire arc 310 and the substrate 100 is a regular quadrilateral, such as a square or a rectangle, and the shapes of the multiple shielding wire arcs 310 in each of the partitioned shielding spacers 300 can be the same or different, and the lengths of the first arc segment 310.1 and the second arc segment 310.2 of the multiple shielding wire arcs 310 can be the same or different, but are not limited to this.

[0066] As an example, the first arc segment 310.1 of at least one of the shielding arcs 310 of the partitioned shielding spacer 300 in the present invention intersects with the second arc segment 310.2 of another of the shielding arcs 310, that is, the multiple shielding arcs 310 in each partitioned shielding spacer 300 may not intersect with each other, such as Figure 4 As shown, there may also be intersections between all (or part) shielding arcs 310, such as Figure 5 As shown, but not limited to this.

[0067] It should be understood that the shielding wire arcs 310 of the partitioned shielding spacer 300 in the present invention are all formed on the corresponding grounding pad 400 by bonding, and each of the shielding wire arcs 310 can be electrically connected to the grounding pad 400 through two welding points 320, and the welding points 320 of multiple shielding wire arcs 310 of the partitioned shielding spacer 300 can be distributed on the same grounding pad 400, or on different grounding pads 400, but not limited to this.

[0068] As an example, Figure 9 As shown, combined with Figures 1 to 3 In the present invention, a grounding pad 400 may be provided on the substrate 100 between the adjacent chip components 200, and all the shielding wire arcs 310 of the partitioned shielding spacer 300 located between the adjacent chip groups 200 are formed on the same grounding pad 400 in a wire bonding manner, that is, the two welding points 320 of each shielding wire arc 310 of the partitioned shielding spacer 300 are distributed on the same grounding pad 400.

[0069] As another example, Figures 10 to 14 As shown, combined with Figures 1 to 3 In the present invention, a plurality of grounding pads 400 may be provided on the substrate 100 between the adjacent chip components 200, and part of the shielding wire arcs 310 of the partitioned shielding spacer 300 located between the adjacent chip components 200 are formed on the same grounding pad 400 by bonding, that is, the solder points of a part of the shielding wire arcs 310 in the partitioned shielding spacer 300 may be distributed on the same grounding pad 400, or the two solder points of each shielding wire arc 310 in the partitioned shielding spacer 300 may be distributed on different grounding pads 400, or the two solder points of a part of the shielding wire arcs 310 in the partitioned shielding spacer 300 may be distributed on different grounding pads 400, but it is not limited to this.

[0070] It should be understood that the above Figures 9 to 14Only the various connection relationships between the solder joints 320 and the ground pads 400 are shown when the plurality of shielding wire arcs 310 in the partition shielding spacer 300 do not intersect. In other embodiments, when the solder joints 320 of the shielding wire arcs 310 and the ground pads 400 are intersected, Figures 9 to 14 In the connection manner shown, the corresponding multiple shielding wire arcs 310 may partially or completely overlap (intersect), but are not limited to this.

[0071] It should be understood that the multiple shielding wire arcs 310 and their respective corresponding welding points 320 of the partitioned shielding spacer 300 in the embodiment of the present invention can be located on the same straight line extending along the second direction D2, or on different straight lines extending along the second direction D2, but are not limited to this. When the multiple shielding wire arcs 310 and their respective corresponding welding points 320 of the partitioned shielding spacer 300 are located on the same straight line extending along the second direction D2, the corresponding projections of the shielding wire arcs 310 and their corresponding welding points 320 in the first direction D1 overlap.

[0072] It should be understood that, ideally, the length of the first arc segment 310.1 of the shielding arc 310 in the partition shielding spacer 300 in the second direction D2 can be 0, that is, the shape of the shielding arc 310 is along the third direction D3 (such as Figure 15 In this configuration, the partition shielding spacer 300 is shaped as a straight line segment extending in the third direction D3 or the fourth direction D4 (not shown). In this configuration, the partition shielding spacer 300 is shaped as a straight line segment extending in the first direction D1, and the projection of the straight line segment extending in the third direction D3 or the fourth direction D4 is also only a straight line segment, such as Figure 16 shown.

[0073] It should be noted that the methods, processes and materials involved in this utility model are all existing technologies.

[0074] To sum up, in the packaging structure provided by the present invention, partitioned shielding is achieved by arranging a partitioned shielding spacer having a first line arc segment and a second line arc segment extending in different directions and connected to each other between adjacent chip components, thereby reducing the area of ​​the substrate occupied by the partitioned shielding device, and the component that plays a shielding role in the partitioned shielding spacer is a shielding line arc with both a horizontal width and a vertical width formed only by wire bonding. That is, while achieving the electromagnetic shielding effect, it also achieves the purpose of simplifying the packaging process and shortening the production cycle, and ultimately helps to reduce costs and improve yield.

[0075] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A packaging structure, characterized in that: include: substrate; A plurality of chip components are arranged on the surface of the substrate and spaced apart from each other along a first direction; A plurality of partitioned shielding spacers are located between adjacent chip components, and the partitioned shielding spacers include a plurality of shielding arcs extending along the second direction, each of the shielding arcs having a first arc segment and a second arc segment extending in different directions and connected to each other; A plastic packaging layer is located on the substrate and wraps the plurality of chip components and the plurality of partition shielding spacers.

2. The packaging structure according to claim 1, wherein: The first line arc segment extends along the second direction, and the second line arc segment extends along a third direction; wherein the first direction is perpendicular to the second direction, and the third direction is perpendicular to the plane where the first direction and the second direction are located.

3. The packaging structure according to claim 2, wherein: The first arc segment extends along the second direction, and the second arc segment extends along a fourth direction. The fourth direction is located between the third direction and the first direction, and forms an angle with the third direction that is less than 90 degrees.

4. The packaging structure according to claim 2 or 3, wherein: The first arc segment of at least one of the shielding arcs of the partitioned shielding spacer intersects with the second arc segment of another shielding arc.

5. The packaging structure according to claim 2 or 3, wherein: An angle is formed between the first arc segment of the shielding arc and the second arc segment connected thereto, and the angle is a right angle.

6. The packaging structure according to claim 2 or 3, wherein: The top surface of the first arc segment of at least one of the shielding arcs of the partitioned shielding spacer is higher than the top surface of the plastic packaging layer.

7. The packaging structure according to claim 2 or 3, characterized in that: Also includes: A plurality of grounding pads are located on the substrate, and at least one grounding pad is provided on the substrate between adjacent chip components.

8. The packaging structure according to claim 7, wherein: A grounding pad is provided on the substrate between adjacent chip components, and all the shielding line arcs of the partition shielding spacers located between the adjacent chip components are formed on the grounding pad in a wire bonding manner.

9. The packaging structure according to claim 7, wherein: A plurality of grounding pads are provided on the substrate between adjacent chip components, and part of the shielding arcs of the partitioned shielding spacers between the adjacent chip components are formed on the same grounding pad in a bonding manner.

10. The packaging structure according to claim 7, wherein: A plurality of grounding pads are provided on the substrate between adjacent chip components, and two welding points of at least one shielding wire arc of the partitioned shielding spacer located between the adjacent chip components are distributed on different grounding pads.

11. The packaging structure according to claim 10, wherein: The projections of at least some of the shielding wire arcs and their corresponding welding points of the partitioned shielding spacer in the first direction respectively overlap.

12. The packaging structure according to claim 10, wherein: The projection shape of at least a portion of the shielding wire arcs of the partitioned shielding spacer in the first direction is an arc shape.

13. The packaging structure according to claim 12, wherein: The arc-shaped projections of at least a portion of the shielding line arcs of the partitioned shielding spacer in the first direction at least partially overlap with the projections of the chip assembly in the first direction.

14. The packaging structure according to claim 1, wherein: Also includes: The metal shielding layer is arranged outside the plastic packaging layer and is in direct contact with at least one of the shielding wire arcs of the partition shielding spacer.

15. The packaging structure according to claim 1, wherein: The chip assembly is a flip chip, a chip or a component, and the chip includes at least one of a filter chip, a duplexer chip and a multiplexer chip, and a power amplifier chip.

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