High-precision timestamp capturing and synchronizing device of bus network end equipment

Abstract

The utility model relates to a high-precision timestamp capturing and synchronizing device of bus network end equipment, belongs to the technical field of timestamp capturing and synchronizing, and solves the problems of low synchronizing precision and insufficient fault-tolerant capability of the device in the prior art. Comprising a high-precision clock module; an input detection circuit; the counting clock signal end of the hardware counter is connected with the output end of the high-precision clock module; a trigger logic module, the A input end of a first NAND gate is connected with the output end of the input detection circuit, the B input end of the first NAND gate is used for receiving a capture control level signal, and the output end of the first NAND gate is connected with the enabling end of the hardware counter; the input end A of the third NAND gate is connected with a synchronizing signal, and the input end B of the third NAND gate is connected with the overflow signal output end of the hardware counter; and the output enabling end of the timestamp register is connected with the output end of the third NAND gate of the trigger logic module. And high-precision timestamp capture and synchronization are realized.

Description

Technical Field

[0001] The utility model relates to the technical field of time stamp capture and synchronization, in particular to a high-precision time stamp capture and synchronization device for bus network terminal equipment. Background Art

[0002] In modern bus networks, accurate timestamp capture of network data and network clock synchronization are crucial for device reliability and real-time performance. They can be used to prevent and analyze network attacks, support legal and criminal investigations, monitor and optimize network performance, and verify data consistency and integrity.

[0003] Traditional time synchronization methods are subject to challenges in accuracy due to network jitter and signal delays. This is particularly true when faced with complex network topologies and high data rates. Furthermore, effectively handling network failures and ensuring device fault tolerance present challenges. Utility Model Content

[0004] In view of the above analysis, the present invention aims to provide a high-precision timestamp capture and synchronization device for bus network terminal equipment, so as to solve the problems of low synchronization accuracy and insufficient fault tolerance of the device in the prior art.

[0005] The purpose of this utility model is mainly achieved through the following technical solutions:

[0006] High-precision clock module, outputting clock signal at the output end;

[0007] Input detection circuit, the input end is used to connect to an external signal source, and the output end is used to output a high level when the input end receives an external signal;

[0008] Hardware counter, the counting clock signal end is connected to the output end of the high-precision clock module;

[0009] A trigger logic module, wherein the A input terminal of the first NAND gate is connected to the output terminal of the input detection circuit, the B input terminal of the first NAND gate is used to receive the capture control level signal, and the output terminal of the first NAND gate is connected to the enable terminal of the hardware counter; the A input terminal of the third NAND gate is connected to the synchronization signal, and the B input terminal of the third NAND gate is connected to the overflow signal output terminal of the hardware counter;

[0010] The timestamp register has a parallel bit input terminal connected to the parallel bit output terminal of the hardware counter, an output enable terminal connected to the output terminal of the third NAND gate of the trigger logic module, and an output terminal for outputting timestamp data.

[0011] Based on the further improvement of the above device, it also includes a dynamic window adjustment module; wherein,

[0012] The SPI communication end of the dynamic window adjustment module is used to receive an external capture control signal, and the voltage output end is connected to the B input end of the first NAND gate of the trigger logic module, and outputs a capture control level signal based on the external capture control signal.

[0013] Based on the further improvement of the above device, the dynamic window adjustment module includes a chip AD5541AARMZ-REEL7 and a resistor R8, pin 2 of the chip AD5541AARMZ-REEL7 is a voltage output terminal, pin 4 is a voltage reference terminal, and the SPI communication terminal includes an SPI communication chip select terminal, an SPI communication clock terminal and an SPI communication data terminal, wherein pin 5 of the chip is the SPI communication chip select terminal, pin 6 is the SPI communication clock terminal, and pin 7 is the SPI communication data terminal; the voltage reference terminal of the dynamic window adjustment module is connected to the device power supply through the resistor R8.

[0014] Based on the further improvement of the above device, it also includes a redundant fault-tolerant module, which includes an undervoltage comparator and an overvoltage comparator; wherein,

[0015] The voltage input end of the redundant fault-tolerant module is connected to an external power supply; the voltage output end is connected to the device power supply, which is used to power the high-precision clock module, the trigger logic module, and the dynamic window adjustment module; the undervoltage comparator input end is used to input the undervoltage threshold; the overvoltage comparator input end is used to input the overvoltage threshold; the gate drive output end of the external n-channel MOSFET is used to connect to the gate of the external n-channel MOSFET, and the n-channel MOSFET is connected to the voltage output end, and the voltage output is turned off when the external power supply is less than the undervoltage threshold or greater than the overvoltage threshold.

[0016] Based on the further improvement of the above device, the redundant fault-tolerant module includes a chip LTC4365ITS8#PBF, a resistor R15, a resistor R11, a resistor R12, a resistor R13, and a resistor R14;

[0017] Pin 7 of the LTC4365ITS8#PBF chip is a voltage output terminal, pin 2 is an undervoltage comparator input terminal, pin 3 is an overvoltage comparator input terminal, pin 5 is a power-off control input terminal, pin 6 is a fault indication output terminal, and pin 8 is a gate drive output terminal of an external n-channel MOSFET; the power-off control input terminal is used to receive an external power supply on / off control signal to control the on / off of the voltage output terminal; the fault indication output terminal is connected to the device power supply through a resistor R15, and is used to output a detection signal of the input power supply status to the outside; the input terminal of the undervoltage comparator is connected to one end of the resistor R14, the input terminal of the overvoltage comparator is connected to one end of the resistor R12, the other end of the resistor R14 is connected to one end of the resistor R13 and the device power supply, the other end of the resistor R12 is connected to one end of the resistor R11 and the device power supply, and the other ends of the resistors R11 and R13 are grounded.

[0018] Based on the further improvement of the above device, the synchronization signal is output by the synchronization signal output terminal of the PTP synchronization module; wherein,

[0019] The synchronization signal output end of the PTP synchronization module is connected to the A input end of the third NAND gate and the A input end of the fourth NAND gate of the trigger logic module; the B input end of the fourth NAND gate is connected to the output end of the input detection circuit, and the output end of the fourth NAND gate is connected to the count reset end of the hardware counter; the management data transmission end and the management data clock end are respectively used to connect to the external control module.

[0020] Based on the further improvement of the above device, the PTP synchronization module includes a chip DP83640, a diode D2 and a resistor R10. Pin 25 of the chip is the synchronization signal output terminal, pin 30 is the management data transmission terminal, and pin 31 is the management data clock terminal; the management data transmission terminal is also connected to the cathode of the diode D2 through the resistor R10, and the anode of the diode D2 is connected to the device power supply.

[0021] Based on the further improvement of the above device, the trigger logic module includes chip 74LS00;

[0022] Pin 1 of the chip 74LS00 is the A input of the first NAND gate, pin 2 is the B input of the first NAND gate, and pin 3 is the output of the first NAND gate; pin 4 is the A input of the second NAND gate, pin 5 is the B input of the second NAND gate, and pin 6 is the output of the second NAND gate; pin 9 is the A input of the third NAND gate, pin 10 is the B input of the third NAND gate, and pin 8 is the output of the third NAND gate; pin 12 is the A input of the fourth NAND gate, pin 13 is the B input of the fourth NAND gate, and pin 1 is the output of the fourth NAND gate; wherein,

[0023] The A input of the second NAND gate is connected to the clock signal output by the high-precision clock module, the B input is connected to the device power supply, and the output of the second NAND gate is connected to the register clock end of the hardware counter and the clock end of the timestamp register.

[0024] Based on further improvements of the above device, the hardware counter includes chip 74LS590; pin 12 of the chip 74LS590 is an enable terminal, pin 11 is a counting clock signal terminal, pin 10 is a counting reset terminal, pin 13 is a register clock terminal, and pin 9 is an overflow signal output terminal.

[0025] Based on the further improvement of the above device, the timestamp register includes a chip SN74HC574DWR, and pin 1 of the chip SN74HC574DWR is an output enable terminal, and pin 11 is a clock terminal.

[0026] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0027] 1. Traditional devices usually rely on hardware to achieve time synchronization, which requires replacing counters or adding complex logic circuits. The utility model uses the counter overflow signal and PTP synchronization signal to correct the time without changing the hardware counter, achieving high-precision time synchronization, simplifying hardware design and reducing costs.

[0028] 2. Redundant fault-tolerant modules are used to provide overvoltage, undervoltage and reverse connection protection for the device, avoiding damage to the device caused by power supply anomalies and improving system reliability and safety.

[0029] 3. Use dynamic window adjustment module to control the detection window, avoid interference caused by noise and invalid data, and improve capture accuracy and flexibility.

[0030] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following content, and some advantages will become apparent from the description or be understood through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the text and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are only used to illustrate specific embodiments and are not considered to limit the present invention. Throughout the accompanying drawings, the same reference symbols represent the same components.

[0032] Figure 1 This is a structural diagram of a high-precision timestamp capture and synchronization device for a bus network terminal device shown in one embodiment of the present utility model;

[0033] Figure 2 This is a circuit diagram of a high-precision time stamp capture and synchronization device for a bus network terminal device shown in another embodiment of the present utility model;

[0034] Reference numerals:

[0035] 11-High-precision clock module; 12-Input detection circuit; 13-Hardware counter; 14-Trigger logic module; 15-Timestamp register; 16-Dynamic window adjustment module; 17-Redundant fault-tolerant module; 18-PTP synchronization module. DETAILED DESCRIPTION

[0036] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0037] A specific embodiment of the present utility model discloses a high-precision time stamp capture and synchronization device for a bus network terminal device, such as Figure 1 Shown, including:

[0038] High-precision clock module 11, output terminal outputs clock signal;

[0039] An input detection circuit 12, wherein the input terminal is used to connect to an external signal source, and the output terminal is used to output a high level when the input terminal receives an external signal;

[0040] Hardware counter 13, the counting clock signal terminal is connected to the output terminal of the high-precision clock module;

[0041] A trigger logic module 14, wherein the A input terminal of the first NAND gate is connected to the output terminal of the input detection circuit, the B input terminal of the first NAND gate is used to receive the capture control level signal, and the output terminal of the first NAND gate is connected to the enable terminal of the hardware counter; the A input terminal of the third NAND gate is connected to the synchronization signal, and the B input terminal of the third NAND gate is connected to the overflow signal output terminal of the hardware counter;

[0042] The timestamp register 15 has a parallel bit input terminal connected to the parallel bit output terminal of the hardware counter, an output enable terminal connected to the output terminal of the third NAND gate of the trigger logic module, and an output terminal for outputting timestamp data.

[0043] Specifically, the high-precision clock module provides a stable, high-precision clock signal for the entire device. The output clock signal serves as the reference for the hardware counter and timestamp register. The clock input of the input trigger logic module and the hardware counter drives the generation of timing and timestamps, and provides a stable clock signal for the crystal oscillator of the PTP synchronization module.

[0044] Specifically, the input detection circuit is used to detect the start and end of the data frame. When the frame end condition is detected, it outputs an inverted signal of the frame start signal to indicate that the frame has ended; at the same time, it provides reliable signal isolation to ensure that the input signal does not interfere with the normal operation of the device.

[0045] The device of this embodiment further includes a dynamic window adjustment module 16; wherein,

[0046] The SPI communication terminal of the dynamic window adjustment module is used to receive an external capture control signal, and the voltage output terminal is connected to the B input terminal of the first NAND gate of the trigger logic module, and outputs a capture control level signal based on the external capture control signal; the module dynamically adjusts the time capture window according to the real-time status of the network to ensure that invalid or noisy data is not recorded, is used to determine the specific capture time end, and dynamically adjusts it according to the traffic, jitter or delay in the network, thereby improving the accuracy and reliability of timestamp capture.

[0047] The device of this embodiment further includes a redundant fault-tolerant module 17, which includes an undervoltage comparator and an overvoltage comparator; wherein,

[0048] The voltage input end of the redundant fault-tolerant module is connected to an external power supply; the voltage output end is connected to the device power supply, which is used to power the high-precision clock module, trigger logic module, and dynamic window adjustment module; the undervoltage comparator input end is used to input the undervoltage threshold; the overvoltage comparator input end is used to input the overvoltage threshold; the gate drive output end of the external n-channel MOSFET is used to connect to the gate of the external n-channel MOSFET, and the n-channel MOSFET is connected to the voltage output end. When the external power supply is less than the undervoltage threshold or greater than the overvoltage threshold, the voltage output is turned off to protect the power supply circuit and ensure that when the input power supply has overvoltage, undervoltage and reverse connection faults, the device can automatically disconnect the power supply and provide a fault alarm signal, thereby enhancing the reliability of the device.

[0049] The synchronization signal is output from the synchronization signal output terminal of the PTP synchronization module;

[0050] The synchronization signal output terminal of the PTP synchronization module 18 is connected to the A input terminal of the third NAND gate of the trigger logic module, the A input terminal of the fourth NAND gate, and the synchronization signal receiving terminal of the external control module; the B input terminal of the fourth NAND gate is connected to the output terminal of the input detection circuit, and the output terminal of the fourth NAND gate is connected to the count reset terminal of the hardware counter; the management data transmission terminal and the management data clock terminal are respectively used to connect to the external control module. The PTP synchronization module receives the network time from the bus network through the Ethernet interface, and the PTP synchronization signal is synchronized with the network time; the management data clock terminal is used to provide a clock signal for the management data transmission terminal; the management data transmission terminal is used to obtain accurate network time from the PTP synchronization module and transmit it to the external control module.

[0051] Specifically, the trigger logic module 14 includes chip 74LS00;

[0052] Pin 1 of the chip 74LS00 is the A input of the first NAND gate, pin 2 is the B input of the first NAND gate, and pin 3 is the output of the first NAND gate; pin 4 is the A input of the second NAND gate, pin 5 is the B input of the second NAND gate, and pin 6 is the output of the second NAND gate; pin 9 is the A input of the third NAND gate, pin 10 is the B input of the third NAND gate, and pin 8 is the output of the third NAND gate; pin 12 is the A input of the fourth NAND gate, pin 13 is the B input of the fourth NAND gate, and pin 1 is the output of the fourth NAND gate; wherein,

[0053] The A input of the second NAND gate is connected to the clock signal output by the high-precision clock module, the B input is connected to the device power supply, and the output of the second NAND gate is connected to the register clock end of the hardware counter and the clock end of the timestamp register.

[0054] Specifically, the hardware counter 13 includes a chip 74LS590; pin 12 of the chip 74LS590 is an enable terminal, pin 11 is a counting clock signal terminal, pin 10 is a counting reset terminal, pin 13 is a register clock terminal, and pin 9 is an overflow signal output terminal, which also transmits the overflow signal to an external control module.

[0055] Specifically, the timestamp register 15 includes a chip SN74HC574DWR, of which pin 1 is an output enable terminal and pin 11 is a clock terminal. When the trigger logic module receives the PTP synchronization signal and the hardware counter overflow signal, it controls the output enable terminal of the timestamp register to enable, thereby achieving timestamp synchronization and counter overflow processing.

[0056] Another specific embodiment of the present invention is as follows Figure 2 As shown:

[0057] The high-precision clock module 11 includes a chip SIT8920AM-81-33E-29, and pin 3 is a clock output terminal.

[0058] The input detection circuit 12 includes a chip, TLP2355. Pin 1 receives an external signal source, and pin 5 is an output terminal connected to the A input terminal of the first NAND gate of the trigger logic module. When an external signal is received, the output terminal outputs a high level to the A input terminal of the first NAND gate of the trigger logic module. The chip TLP2355 is also a high-speed optical coupler that can effectively isolate the input signal from the internal circuit of the device, preventing high voltage or interference in the input signal from affecting the normal operation of the device. The function of the optical coupler is to convert the input electrical signal into an optical signal for transmission, and then restore it to an electrical signal after isolation, thereby ensuring the signal integrity of the device in complex electromagnetic environments.

[0059] The dynamic window adjustment module 16 includes a chip AD5541AARMZ-REEL7 and a resistor R8. Pin 2 of the chip AD5541AARMZ-REEL7 is a voltage output terminal, and pin 4 is a voltage reference terminal, which controls the output range of the output voltage; the SPI communication terminal includes an SPI communication chip select terminal, an SPI communication clock terminal, and an SPI communication data terminal, wherein pin 5 of the chip is an SPI communication chip select terminal, pin 6 is an SPI communication clock terminal, and pin 7 is an SPI communication data terminal; pin 8 is a DAC update port, which controls the update time of the voltage output terminal; the voltage reference terminal of the dynamic window adjustment module is connected to the device power supply through the resistor R8.

[0060] The redundant fault-tolerant module 17 includes a chip LTC4365ITS8#PBF, a resistor R15, a resistor R11, a resistor R12, a resistor R13, and a resistor R14;

[0061] Pin 7 of the LTC4365ITS8#PBF chip is a voltage output terminal, pin 2 is an undervoltage comparator input terminal, pin 3 is an overvoltage comparator input terminal, pin 5 is a power-off control input terminal, pin 6 is a fault indication output terminal, and pin 8 is a gate drive output terminal of an external n-channel MOSFET; the power-off control input terminal is used to receive an external power supply on / off control signal to control the on / off of the voltage output terminal; the fault indication output terminal is connected to the device power supply through a resistor R15, and is used to output a detection signal of the input power supply status to the outside; the input terminal of the undervoltage comparator is connected to one end of the resistor R14, the input terminal of the overvoltage comparator is connected to one end of the resistor R12, the other end of the resistor R14 is connected to one end of the resistor R13 and the device power supply, the other end of the resistor R12 is connected to one end of the resistor R11 and the device power supply, and the other ends of the resistors R11 and R13 are grounded.

[0062] The PTP synchronization module 18 includes a DP83640 chip, a diode D2, and a resistor R10. Pin 25 of the chip is the synchronization signal output terminal, pin 30 is the management data transmission terminal, and pin 31 is the management data clock terminal. Pin 7 is used to transmit an interrupt signal to the external control module. The management data transmission terminal is also connected to the cathode of diode D2 via resistor R10, and the anode of diode D2 is connected to the device power supply. The PTP synchronization module receives the network time from the bus network through an Ethernet interface and accurately synchronizes with the network time, ensuring that the device time is consistent with the external network time.

[0063] The trigger logic module 14 includes a chip 74LS00, wherein pin 1 is the A input terminal of the first NAND gate, pin 2 is the B input terminal of the first NAND gate, and pin 3 is the output terminal of the first NAND gate; pin 4 is the A input terminal of the second NAND gate, pin 5 is the B input terminal of the second NAND gate, and pin 6 is the output terminal of the second NAND gate; pin 9 is the A input terminal of the third NAND gate, pin 10 is the B input terminal of the third NAND gate, and pin 8 is the output terminal of the third NAND gate; pin 12 is the A input terminal of the fourth NAND gate, pin 13 is the B input terminal of the fourth NAND gate, and pin 1 is the output terminal of the fourth NAND gate; wherein,

[0064] The A input of the second NAND gate is connected to the clock signal output by the high-precision clock module, the B input is connected to the device power supply, and the output of the second NAND gate is connected to the register clock end of the hardware counter and the clock end of the timestamp register.

[0065] The hardware counter 13 includes a chip 74LS590, pin 12 is an enable terminal, pin 11 is a counting clock signal terminal, pin 10 is a counting reset terminal, pin 13 is a register clock terminal, and pin 9 is an overflow signal output terminal, which also transmits the overflow signal to an external control module.

[0066] The timestamp register 15 includes a chip SN74HC574DWR, whose pin 1 is an output enable terminal and pin 11 is a clock terminal. When the trigger logic module receives the PTP synchronization signal and the hardware counter overflow signal, it controls the output enable terminal of the timestamp register to enable, realizing timestamp synchronization and counter overflow processing.

[0067] It should be noted that, in this embodiment, decoupling capacitor C12 and capacitor C16 are added to the voltage input ends of the high-precision clock module and the redundant fault-tolerant module, respectively; filter capacitor C11, capacitor C15, and capacitor C13 are added to the ground ends of the high-precision clock module, input detection circuit, and redundant fault-tolerant module, respectively; and filter capacitor C14 is added to the connection point of resistor R12 and resistor R14.

[0068] During implementation, the device is powered on and the redundant fault-tolerant module detects the input voltage. If the input voltage is normal, the external n-channel MOSFET turns on, and the redundant fault-tolerant module's voltage output provides power to the device. The high-precision clock module outputs a stable clock signal, which is provided to the hardware counter, trigger logic module, and PTP synchronization module. The PTP synchronization module is initialized, receives the network time from the bus network through the Ethernet interface, and provides a synchronization signal. The second NAND gate outputs the clock signal to the timestamp register.

[0069] Furthermore, the input detection circuit monitors the external signal. When the input signal is detected, the input detection circuit outputs a high level. For example, the input signal indicates the start of the data frame. If there is a capture control level signal at the output end of the dynamic window adjustment module at this time, that is, the output is a high level, the first NAND gate outputs a low level, then the hardware counter is enabled and starts counting. The second NAND gate outputs a clock signal to the clock end of the hardware counter register, indicating that the count value of the hardware counter can be latched, and the hardware counter parallel bit output end Q0-Q7 transmits the current count value to the timestamp register. When the PTP synchronization signal and the hardware counter overflow signal are both high, the third NAND gate outputs a low level to enable the output of the timestamp register, and the data in the timestamp register is read.

[0070] Furthermore, when the input detection circuit detects a frame end signal and the PTP synchronization module outputs a synchronization signal, the count reset end of the hardware counter receives a low-level signal from the output end of the fourth NAND gate, and the hardware counter is reset to prepare for the next count.

[0071] Furthermore, if the redundant fault-tolerant module detects a voltage anomaly, the gate drive output of the external n-channel MOSFET turns off the external n-channel MOSFET, thereby cutting off the power supply of the device. At the same time, the fault indication output outputs a fault signal to the external control module, and the external control module can stop data acquisition and issue an alarm.

[0072] It should be noted that the external control module monitors the overflow signal output of the hardware counter through interrupts or polling, and immediately reads the current hardware counter count value and overflow times when the PTP synchronization signal arrives. At the same time, it obtains accurate network time from the PTP synchronization module by managing the data transmission end. The time deviation Δt is calculated using the difference between the device time and the network time. In the subsequent timestamp reading, the external control module uses the following formula to correct the total value of the hardware counter to obtain the synchronization timestamp:

[0073] Device total value = overflow times × hardware counter maximum value + current hardware counter value synchronization timestamp = device total value - Δt

[0074] In this way, high-precision timestamp capture is achieved and synchronized with the network time.

[0075] It should be noted that the PTP synchronization signal is synchronized with the network time, and the hardware counter's counting starting point is consistent with the synchronization reference point provided by the network time. Exemplarily, the synchronization reference point is provided by upper-layer software and hardware. The hardware counter's count value establishes a direct correspondence with the network time, thereby achieving time synchronization. When the PTP synchronization module outputs a synchronization signal, the hardware counter is reset and the clock is synchronized. Since both the hardware counter and the timestamp register remain consistent with the network time, synchronization is achieved for all timing-related modules within the device.

[0076] Compared with the prior art, the device provided in this embodiment uses the overflow signal of the counter and the PTP synchronization signal to correct the time without changing the hardware counter, thereby achieving high-precision time synchronization, simplifying the hardware design, and reducing costs. By adding a redundant fault-tolerant module, the device is provided with overvoltage, undervoltage, and reverse connection detection for the input voltage, thereby avoiding damage to the device caused by power supply anomalies and improving the reliability and safety of the system. A dynamic window adjustment module is added to control the detection window, avoid interference caused by noise and invalid data, and improve capture accuracy and flexibility.

[0077] The present invention merely requires connecting the various devices having corresponding functions through the connection relationships provided in the embodiments of the present invention, and does not involve any improvements to the software. The connection methods between the various hardware devices having corresponding functions can be implemented by those skilled in the art using existing technologies and will not be described in detail here.

[0078] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the protection scope of the present invention.

Claims

1. A timestamp capture and synchronization device, characterized in that: include: High-precision clock module, outputting clock signal at the output end; Input detection circuit, the input end is used to connect to an external signal source, and the output end is used to output a high level when the input end receives an external signal; Hardware counter, the counting clock signal end is connected to the output end of the high-precision clock module; A trigger logic module, wherein the A input terminal of the first NAND gate is connected to the output terminal of the input detection circuit, the B input terminal of the first NAND gate is used to receive the capture control level signal, and the output terminal of the first NAND gate is connected to the enable terminal of the hardware counter; the A input terminal of the third NAND gate is connected to the synchronization signal, and the B input terminal of the third NAND gate is connected to the overflow signal output terminal of the hardware counter; The timestamp register has a parallel bit input terminal connected to the parallel bit output terminal of the hardware counter, an output enable terminal connected to the output terminal of the third NAND gate of the trigger logic module, and an output terminal for outputting timestamp data.

2. The timestamp capture and synchronization device according to claim 1, characterized in that: It also includes a dynamic window adjustment module; wherein, The SPI communication end of the dynamic window adjustment module is used to receive an external capture control signal, and the voltage output end is connected to the B input end of the first NAND gate of the trigger logic module, and outputs a capture control level signal based on the external capture control signal.

3. The timestamp capture and synchronization device according to claim 2, characterized in that: The dynamic window adjustment module includes a chip AD5541AARMZ-REEL7 and a resistor R8. Pin 2 of the chip AD5541AARMZ-REEL7 is a voltage output terminal, pin 4 is a voltage reference terminal, and the SPI communication terminal includes an SPI communication chip select terminal, an SPI communication clock terminal, and an SPI communication data terminal. Among them, pin 5 of the chip is the SPI communication chip select terminal, pin 6 is the SPI communication clock terminal, and pin 7 is the SPI communication data terminal; the voltage reference terminal of the dynamic window adjustment module is connected to the device power supply through the resistor R8.

4. The timestamp capture and synchronization device according to claim 1, characterized in that: It also includes a redundant fault-tolerant module, which includes an undervoltage comparator and an overvoltage comparator; wherein, The voltage input end of the redundant fault-tolerant module is connected to an external power supply; the voltage output end is connected to the device power supply, which is used to power the high-precision clock module, the trigger logic module, and the dynamic window adjustment module; the undervoltage comparator input end is used to input the undervoltage threshold; the overvoltage comparator input end is used to input the overvoltage threshold; the gate drive output end of the external n-channel MOSFET is used to connect to the gate of the external n-channel MOSFET, and the n-channel MOSFET is connected to the voltage output end, and the voltage output is turned off when the external power supply is less than the undervoltage threshold or greater than the overvoltage threshold.

5. The timestamp capture and synchronization device according to claim 4, characterized in that: The redundant fault-tolerant module includes a chip LTC4365ITS8#PBF, a resistor R15, a resistor R11, a resistor R12, a resistor R13, and a resistor R14; Pin 7 of the LTC4365ITS8#PBF chip is a voltage output terminal, pin 2 is an undervoltage comparator input terminal, pin 3 is an overvoltage comparator input terminal, pin 5 is a power-down control input terminal, pin 6 is a fault indication output terminal, and pin 8 is a gate drive output terminal for an external n-channel MOSFET; the power-down control input terminal is used to receive an external power on / off control signal to control the on / off of the voltage output terminal; The fault indication output end is connected to the device power supply through the resistor R15, and is used to output a detection signal of the input power supply status to the outside; the input end of the undervoltage comparator is connected to one end of the resistor R14, the input end of the overvoltage comparator is connected to one end of the resistor R12, the other end of the resistor R14 is connected to one end of the resistor R13 and the device power supply, the other end of the resistor R12 is connected to one end of the resistor R11 and the device power supply, and the other ends of the resistors R11 and R13 are grounded.

6. The timestamp capture and synchronization device according to claim 1, characterized in that: The synchronization signal is output by the synchronization signal output terminal of the PTP synchronization module; wherein, The synchronization signal output end of the PTP synchronization module is connected to the A input end of the third NAND gate and the A input end of the fourth NAND gate of the trigger logic module; the B input end of the fourth NAND gate is connected to the output end of the input detection circuit, and the output end of the fourth NAND gate is connected to the count reset end of the hardware counter; the management data transmission end and the management data clock end are respectively used to connect to the external control module.

7. The timestamp capture and synchronization device according to claim 6, characterized in that: The PTP synchronization module includes a chip DP83640, a diode D2 and a resistor R10. Pin 25 of the chip is a synchronization signal output terminal, pin 30 is a management data transmission terminal, and pin 31 is a management data clock terminal; the management data transmission terminal is also connected to the cathode of the diode D2 through the resistor R10, and the anode of the diode D2 is connected to the device power supply.

8. The timestamp capture and synchronization device according to claim 6, characterized in that: The trigger logic module includes a chip 74LS00; Pin 1 of the chip 74LS00 is the A input of the first NAND gate, pin 2 is the B input of the first NAND gate, and pin 3 is the output of the first NAND gate; pin 4 is the A input of the second NAND gate, pin 5 is the B input of the second NAND gate, and pin 6 is the output of the second NAND gate; pin 9 is the A input of the third NAND gate, pin 10 is the B input of the third NAND gate, and pin 8 is the output of the third NAND gate; pin 12 is the A input of the fourth NAND gate, pin 13 is the B input of the fourth NAND gate, and pin 1 is the output of the fourth NAND gate; wherein, The A input of the second NAND gate is connected to the clock signal output by the high-precision clock module, the B input is connected to the device power supply, and the output of the second NAND gate is connected to the register clock end of the hardware counter and the clock end of the timestamp register.

9. The timestamp capture and synchronization device according to claim 1, characterized in that: The hardware counter includes a chip 74LS590; pin 12 of the chip 74LS590 is an enable terminal, pin 11 is a counting clock signal terminal, pin 10 is a counting reset terminal, pin 13 is a register clock terminal, and pin 9 is an overflow signal output terminal.

10. The timestamp capture and synchronization device according to claim 1, characterized in that: The timestamp register includes a chip SN74HC574DWR, wherein pin 1 of the chip SN74HC574DWR is an output enable terminal and pin 11 is a clock terminal.

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