Device

Abstract

The present disclosure relates to a device. A device includes: a first layer having a first side and a second side; a second layer underlying the first layer and coupled to a second face of the first layer; a plurality of fingers on a first side of the first layer, each finger corresponding to a gate of a plurality of transistors; and a plurality of trenches in the first layer, each trench including a conductive element electrically coupling the fingers to the second layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. FR2309400, filed on September 7, 2023, entitled “Dispositifélectronique”, which is hereby incorporated by reference to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly to electronic devices including transistors. Background Art

[0004] Many electronic devices include transistors, and more particularly common-gated transistors. Common-gate transistors are transistors whose gates are coupled (preferably connected) together so that the transistors are controlled by the same control voltage. For example, such transistors may be elementary transistors, i.e., small transistors all of the same size that are coupled together to form the equivalent of a larger transistor. Thus, the gates of the elementary transistors are coupled (preferably connected) together, the drains of the elementary transistors are coupled (preferably connected) together, and the sources of the elementary transistors are coupled (preferably connected) together.

[0005] It would be beneficial to ensure that the transistors receive the same control voltage and receive it at the same time. Utility Model Content

[0006] One embodiment provides a device including trenches that each include a conductive element configured to electrically couple fingers of a transistor gate located on a first side of a first layer to a second layer extending on a second side of the first layer.

[0007] Another embodiment provides a method of fabricating a device, including forming trenches, the trenches each including a conductive element configured to electrically couple fingers of a transistor gate located on a first side of a first layer to a second layer extending on a second side of the first layer.

[0008] According to an embodiment, the second layer is configured to be biased to a control voltage of the transistor.

[0009] According to an embodiment, transistors are arranged in rows, transistors in the same row are coupled together through their gates via the same finger, the rows are arranged in columns, the columns are separated by trenches, and the conductive element of each trench separates the two columns and is coupled to one end of each finger of the two columns.

[0010] According to an embodiment, each column is located between two trenches, each finger being coupled at one end to a conductive element of one of the two trenches and at the other end to a conductive element of the other of the two trenches.

[0011] According to an embodiment, the first layer is made of GaN, AlN or AlGaN.

[0012] According to an embodiment, the device includes a semiconductor substrate on a second side of the first layer, the substrate forming the second layer.

[0013] According to an embodiment, each trench comprises a cavity extending through the first layer, the bottom of the cavity comprises the substrate, and the conductive element comprises a third conductive layer extending over the walls and bottom of the cavity.

[0014] According to an embodiment, the device includes a semiconductor substrate on the second side of the first layer, a face of the substrate furthest from the first layer being covered with a fourth conductive layer, the fourth layer forming the second layer.

[0015] According to an embodiment, the third layer is made of metal.

[0016] According to an embodiment, each trench comprises a cavity extending through the first layer, the bottom of the cavity being located at the face of the substrate closest to the first layer, the conductive element comprising a third conductive layer extending over the walls and bottom of the cavity and a portion located in the substrate in contact with the third layer and in contact with the fourth layer.

[0017] According to an embodiment, the third layer is separated from the first layer by a fifth insulating layer.

[0018] According to an embodiment, the substrate is made of silicon or of silicon carbide.

[0019] According to an embodiment, each conductive element is coupled to a finger through tracks and vias of an interconnect network.

[0020] According to an embodiment, a device includes a first layer having a first side and a second side, and a second layer located below the first layer and coupled to the second side of the first layer. The device includes a plurality of fingers located on a first side of the first layer, each finger corresponding to a gate of a plurality of transistors, and a plurality of trenches located in the first layer, each including a conductive element electrically coupling the finger to the second layer.

[0021] According to an embodiment, a method of manufacturing a device includes forming a first layer on a second layer, and forming a plurality of fingers on a first side of the first layer, each finger corresponding to a collective gate of a plurality of transistors. The method includes forming a plurality of trenches extending from the first side of the first layer to the second side of the first layer, and forming a corresponding conductive element in each trench to electrically couple the plurality of fingers to the second layer.

[0022] According to an embodiment, a device includes a semiconductor substrate, a semiconductor layer on the semiconductor substrate, and a first transistor group. The device includes a first finger extending in a first direction on the semiconductor layer and corresponding to a collective gate of the first transistor group, a second transistor group, and a second finger extending in the first direction on the semiconductor layer and corresponding to the collective gate of the second transistor group. The device includes a trench in the semiconductor layer between the first finger and the second finger, and a conductive element in the trench that contacts the semiconductor substrate and electrically couples the first finger and the second finger to the semiconductor substrate.

[0023] According to one aspect of the present disclosure, a device is provided, comprising: a first layer having a first side and a second side; a second layer located below the first layer and coupled to the second side of the first layer; a plurality of fingers on a first side of the first layer, each finger corresponding to a gate of a plurality of transistors; and a plurality of trenches in the first layer, each trench including a conductive element that electrically couples the finger to the second layer.

[0024] According to an embodiment of the present disclosure, the second layer is configured to be biased to a control voltage of the transistor.

[0025] According to an embodiment of the present disclosure, transistors are arranged in rows, transistors in the same row have a collective gate corresponding to the same finger, the rows are arranged in columns, the columns are separated by trenches, and the conductive element of each trench separates the two columns and is coupled to one end of each finger of the fingers of the two columns.

[0026] According to an embodiment of the present disclosure, wherein each column is located between two trenches, each finger is coupled at one end to a conductive element of one of the two trenches and at another end to a conductive element of the other of the two trenches.

[0027] According to an embodiment of the present disclosure, the first layer is GaN, AlN or AlGaN.

[0028] According to an embodiment of the present disclosure, the second layer is a semiconductor substrate.

[0029] According to an embodiment of the present disclosure, each trench includes a cavity extending through the first layer, the bottom of the cavity exposing the substrate, and the conductive element includes a third conductive layer extending over the wall and the bottom of the cavity.

[0030] According to an embodiment of the present disclosure, the device includes a fourth conductive layer located on the bottom of the second layer and separated from the first layer by the second layer, wherein the second layer is a semiconductor substrate.

[0031] According to an embodiment of the present disclosure, the third layer is metal.

[0032] According to an embodiment of the present disclosure, each trench includes a cavity extending through the first layer, the bottom of the cavity is located at the surface of the substrate closest to the first layer, and the conductive element includes a third conductive layer extending over the wall and bottom of the cavity and a portion located in the substrate, in contact with the third layer and in contact with the fourth layer.

[0033] According to an embodiment of the present disclosure, the third layer is separated from the first layer by a fifth layer of insulating material.

[0034] According to an embodiment of the present disclosure, the semiconductor substrate is silicon or made of silicon carbide.

[0035] According to an embodiment of the present disclosure, each conductive element is coupled to a finger through tracks and vias of an interconnect network.

[0036] According to another aspect of the present disclosure, a method for manufacturing a device is provided, comprising: forming a first layer on a second layer; forming a plurality of fingers on a first side of the first layer, each finger corresponding to a collective gate of a plurality of transistors; forming a plurality of trenches extending from the first side of the first layer to the second side of the first layer; and forming a corresponding conductive element in each trench to electrically couple the plurality of fingers to the second layer.

[0037] According to an embodiment of the present disclosure, the second layer is configured to be biased to a control voltage of the transistor.

[0038] According to an embodiment of the present disclosure, the method includes forming a metal interconnect structure electrically coupling each finger to at least one of the conductive elements.

[0039] According to an embodiment of the present disclosure, transistors are arranged in rows, transistors in the same row have a collective gate corresponding to the same finger, the rows are arranged in columns, the columns are separated by trenches, and the conductive element of each trench separates the two columns and is coupled to one end of each finger of the two columns.

[0040] According to another aspect of the present disclosure, a device is provided, including: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a first transistor group; a first finger extending in a first direction on the semiconductor layer and corresponding to a collective gate of the first transistor group; a second transistor group; a second finger extending in the first direction on the semiconductor layer and corresponding to a collective gate of the second transistor group; a trench in the semiconductor layer between the first finger and the second finger; and a conductive element in the trench that contacts the semiconductor substrate and electrically couples the first finger and the second finger to the semiconductor substrate.

[0041] According to an embodiment of the present disclosure, the device includes a conductive layer located below and in contact with a semiconductor substrate.

[0042] According to an embodiment of the present disclosure, the device includes an electrical contact extending through the semiconductor layer, the semiconductor substrate, and contacting the conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments, which are given by way of illustration and not limitation, with reference to the accompanying drawings, in which

[0044] In the picture:

[0045] Figure 1 schematically illustrates a transistor according to an embodiment;

[0046] Figure 2 schematically illustrates an electronic device according to an embodiment;

[0047] Figure 3 schematically illustrates an electronic device according to an embodiment;

[0048] Figure 4 illustrates a portion of an electronic device according to an embodiment;

[0049] Figure 5 The diagram shows a Figure 4 Another part of the electronic device;

[0050] Figure 6 An electronic device according to an embodiment is shown; and

[0051] Figure 7 The diagram shows a Figure 6 Another part of the electronic device. DETAILED DESCRIPTION

[0052] In the various drawings, similar features are indicated by similar reference numerals. In particular, common structural and / or functional features among multiple embodiments may have the same reference numerals and may be configured with the same structure, dimensions, and material properties.

[0053] For clarity, only the operations and elements that are helpful for understanding the embodiments described herein are shown and described in detail.

[0054] Unless otherwise stated, when two elements are referred to as being connected together, this means a direct connection without any intervening elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0055] In the following disclosure, unless otherwise stated, when absolute position qualifiers such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as terms "above", "below", "high", "low", etc., or directional qualifiers such as "horizontal", "vertical", etc. are mentioned, reference is made to the orientation shown in the accompanying drawings.

[0056] Unless otherwise indicated, the expressions "approximately," "substantially," and "substantially" all mean within 10%, preferably within 5%.

[0057] Figure 1 An example of a transistor 10 of an electronic device is schematically illustrated. The electronic device includes, for example, a chip in which the transistor is formed.

[0058] The transistor 10 is a GaN-based transistor, preferably a metal oxide semiconductor field effect transistor (MOSFET). The transistor 10 may alternatively be a Schottky gate transistor.

[0059] The device includes a substrate 12. The transistor 10 is formed on the substrate 12. The substrate 12 is made of a semiconductor material, such as silicon.

[0060] The device comprises a layer 14 made of gallium nitride. Layer 14 is situated on the upper face of substrate 12 and preferably in contact with the upper face. Layer 14 is formed, for example, by epitaxy from substrate 12. Layer 14 may alternatively correspond to a stack of layers comprising a layer made of GaN and layers made of AlN and AlGaN.

[0061] Layer 14 includes, for example, source and drain regions of transistor 10 . Figure 1 The different regions of transistor 10 are not shown.

[0062] The device comprises a contact element 16, for example made of metal, arranged on and preferably in contact with the source region of the transistor 10. The element 16 is arranged, for example, on the layer 14, for example in contact with the layer, more precisely in contact with the source region located in the layer 14. The element 16 is preferably arranged on the upper face of the layer 14, preferably in contact with the upper face.

[0063] Similarly, the device comprises a contact element 18, for example made of metal, disposed on and preferably in contact with the drain region of transistor 10. Element 18 is disposed, for example, on layer 14, for example in contact with said layer, more precisely in contact with the drain region situated in layer 14. Element 18 is preferably disposed on the upper face of layer 14, preferably in contact with said upper face.

[0064] Transistor 10 also includes a gate region 20. Region 20 is preferably made of a semiconductor material, such as gallium nitride for a Schottky gate, or an insulating material, such as SiO2, SiN, or Al2O3 for an insulated gate. Region 20 is preferably disposed on and in contact with the upper surface of layer 14. The gate region is located, for example, between elements 16 and 18.

[0065] The device further comprises a contact element 22 , for example made of metal, disposed on the gate region 20 of the transistor 10 and preferably in contact with the gate region.

[0066] The lower face of the substrate 12 , ie the face opposite to the upper face, is for example covered by, and preferably in contact with, a conductive layer (not shown), such as a metal layer.

[0067] The device also includes an interconnection network (not shown). In other words, the device includes an insulating layer (not shown) that covers the upper face of the device, and therefore covers the upper face of layer 14, region 20 and elements 16, 18, 22. Said layer (not shown) includes conductive tracks and conductive vias (not shown) for providing connections between elements of the device or between the device and external devices.

[0068] Figure 2 Schematically illustrates an example of an electronic device 24. More precisely, Figure 2 A top view of a set of transistors 26 is schematically illustrated. Figure 2 An example of an arrangement of transistors in an electronic device 24 is shown, and the connections of the transistor gates are illustrated more precisely.

[0069] Device 24 includes a plurality of transistors 26. Transistors 26 are connected to, for example, Figure 1 . However, transistor 26 may be another type of gallium nitride transistor, i.e., another type of transistor whose drain and source regions are located in the gallium nitride layer. Thus, transistor 26 may be, for example, a MOSFET transistor or a p-GaN gate transistor that is a Schottky gate transistor.

[0070] Transistors 26 are, for example, basic transistors. Transistors 26 are, for example, all identical. Transistors 26 have a common gate. In other words, the gates of all transistors 26 are coupled to each other, preferably connected to each other. The drains of all transistors are, for example, coupled together, preferably connected together. The sources of all transistors are, for example, coupled together, preferably connected together.

[0071] exist Figure 2, each transistor 26 is represented by a source contact element 28, a drain contact element 30, and a gate contact element 32. Elements 28 and 30 correspond to, for example, Figure 1 Element 16 and Figure 1 Element 18. Element 32 corresponds to, for example Figure 1 Component 22.

[0072] The transistors 26 of the device are arranged in rows 34. More precisely, the transistors 26 of a row 34 are arranged in such a way that the pads 28 and 30 respectively form parallel rows. The different rows 34 are arranged parallel to each other.

[0073] The contact elements 32 of the transistors 26 of the same row 34 comprise portions of the same conductive track 35, in other words, the same finger 35. In other words, the device comprises, for each row 34, a conductive track 35 corresponding, for example, to a conductive track of the interconnection network of the device. The track 35 extends opposite each transistor and is coupled (preferably connected) to the gate region of each transistor 26 of the corresponding row 34. Thus, the transistors of the same row 34 are coupled (preferably connected) together via the gates.

[0074] exist Figure 2 In the example shown in , device 24 includes a pad 36 for applying a control voltage, ie, a voltage supplied to all gates of transistors 26. Thus, pad 36 receives the control voltage from a voltage source (not shown).

[0075] Device 24 also includes a conductive track 38. Track 38 is also coupled (preferably connected) to pad 36. Track 38 is, for example, a conductive track or metallization of the device's interconnect network. Track 38 is thus connected to pad 36, for example, via a conductive via. Track 38 is thus biased by a control voltage.

[0076] The track 38 extends in a first direction. The fingers extend in another direction, e.g. Figure 2 , extending in a direction perpendicular to the direction of the track 38. The rows 34 of transistors 26 extend along a second direction.

[0077] Rail 38 is coupled (preferably connected) to all rails 35 to supply control voltage to all transistors 26 .

[0078] During device operation, biasing of the gate of transistor 26 is provided by pad 36 and rails 35 and 38. However, in devices with a large number of transistors and a large number of fingers, there is a long delay between the moment a control voltage is applied to pad 36, and thereby to one end of rail 38 near pad 36, and the moment the other end of rail 38 is biased. This delay, caused by the resistivity of rail 38, can be problematic, particularly during current peaks, which can then be concentrated on a few rows 34, rather than distributed across all transistors.

[0079] Figure 3 Schematically illustrates an embodiment of an electronic device 40. More precisely, Figure 3 A top view of a set of transistors 26 is schematically illustrated. Figure 3 An example of an arrangement of transistors in an electronic device is illustrated, and more precisely the connection of transistor gates is illustrated.

[0080] and Figure 2 Like the device 24 shown in FIG, the device 40 includes a plurality of transistors 26. The transistors 26 correspond to, for example, Figure 1 However, transistor 26 may be another type of transistor based on gallium nitride, or a type of transistor based on AlGaN or aluminum nitride (AlN), i.e., another type of transistor whose drain and source regions are located in the gallium nitride layer.

[0081] and Figure 2 Similarly, transistors 26 are, for example, basic transistors. Transistors 26 are, for example, all identical. Transistors 26 have a common gate. In other words, the gates of all transistors 26 are coupled (preferably connected) to each other.

[0082] exist Figure 3 In, with Figure 2 Similarly, each transistor 26 is represented by a source contact element 28, a drain contact element 30, and a gate contact element 32. Elements 28 and 30 correspond to, for example, Figure 1 Element 16 and Figure 1 Element 18 shown in FIG. Element 32 corresponds to, for example Figure 1 Component 22 shown in FIG.

[0083] and Figure 2 Similar to device 24 of FIG. , device 40 includes rows 34 of transistors 26. Figure 2 Similarly, transistors 26 of row 34 are arranged in such a way that pads 28 and 30 respectively form parallel rows. Different rows 34 are arranged parallel to each other.

[0084] The contact elements of the transistors 26 of the same row 34 comprise portions of the same conductive track 35, in other words, the same finger 35. In other words, the device comprises, for each row 34, a conductive track 35 corresponding, for example, to a conductive track of the device's interconnection network. Track 35 extends opposite each transistor and is coupled (preferably connected) to the gate region of each transistor 26 of the corresponding row 34. Thus, the transistors of the same row 34 are coupled (preferably connected) together via their gates. The drains of all transistors of a row are, for example, coupled (preferably connected) together. The sources of all transistors of a row are, for example, coupled (preferably connected) together.

[0085] To make the representation clear, Figure 3 In the example shown in , each row 34 includes three transistors. A row may include any number of transistors 26, for example at least ten transistors.

[0086] exist Figure 3 In the example shown in FIG, rows 34 of transistors are arranged in columns 41. Columns 41 extend, for example, in a direction perpendicular to the direction in which the rows extend. Thus, the tracks 35 of the rows of the same column 41 are parallel to one another and are separated from one another by rows of elements 28 or rows of elements 30. Columns 41 are parallel to one another. The device includes at least one column, for example, at least three columns.

[0087] exist Figure 3 In the example shown in FIG, device 40 includes a pad 42 for applying a control voltage (i.e., a voltage supplied to all gates of transistors 26). Thus, pad 42 receives the control voltage from a voltage source (not shown). Pad 42 is preferably located outside the area where transistor 26 is located. More generally, the device may include multiple pads 42, for example, located at different locations around transistor 26.

[0088] The device comprises a conductive or semiconductive layer ( Figure 3 (not shown), the conductive or semiconductive layer extends from the lower side of the gallium nitride layer where the source and drain regions are located. Figure 1 The region 20 in the example shown in FIG is preferably separated from the conductive or semiconductive layer by the gallium nitride layer. The track 35 is also preferably separated from the conductive or semiconductive layer by the gallium nitride layer.

[0089] A conducting or semiconducting layer (not shown) preferably extends opposite the entire area of ​​the device in which the transistors are located. Thus, all transistors are positioned opposite said layer.

[0090] The conductive or semiconductive layer (not shown) is biased to a control voltage. The conductive or semiconductive layer is, for example, coupled (preferably connected) to a pad 42, more precisely, to the lower end of the pad 42. Thus, the pad 42 preferably extends from the upper side of the chip forming the transistor to the lower side of the chip. The upper end of the pad 42 is, for example, coupled (preferably connected) to an interconnection network to receive the control voltage. The lower end of the pad 42 is coupled (preferably connected) to the conductive or semiconductive layer, which is thereby biased to the control voltage.

[0091] According to another embodiment, device 40 does not include pad 42. The conductive or semiconductive layer (not shown) is then coupled to the control voltage source without crossing substrate 12, for example, by contacting another device. The conductive or semiconductive layer (not shown) is coupled to the control voltage source via cavity 56, for example, through layer 54.

[0092] Device 40 includes trenches 44. Each column 41 is separated from an adjacent column 41 by a trench 44. Preferably, each column is located between two trenches 44. Each trench 44 preferably extends along all sets 34 of transistors 26. In other words, each trench 44 extends from a track 35 of the first set 34 of a column to a track 35 of the last set 34 of a column.

[0093] Each trench 44 penetrates at least the gallium nitride layer where the source region and the drain region are located, and reaches the conductive or semiconductive layer.

[0094] Each trench 44 comprises a conductive element extending to the semiconductive or conductive layer and coupled, directly or through an interconnecting network of conductive tracks and conductive vias, to the tracks 35 of the set 34 of columns 41 located on either side of the trench 44. Thus, at least one end of each track 34 is coupled (preferably connected) to the conductive or semiconductive layer through the conductive element in the trench 44.

[0095] Preferably, each column is located between two grooves 44. Thus, said two ends of each track 35 are preferably coupled (preferably connected) to the conductive or semiconductive layer through the conductive elements of the grooves 44 located on both sides of the column 41.

[0096] The conductive element of each trench 44 is electrically insulated from the gallium nitride layer.

[0097] The biasing of the conductive or semiconductive layer is preferably performed by a plurality of pads 42. Thus, the entire layer is biased to a control voltage. Thus, compared to Figure 2 The transistors 26 shown in FIG are connected to the pads 36, and the set of transistors 26 is closer to the trench 44 that supplies the control voltage. Although there may be a short delay between transistors in the same row 34, the delay is smaller than Figure 2Furthermore, the distance between the transistors 26 at the same position on different rows and the conductive or semiconductive layer is the same.

[0098] Figure 4 A portion of an embodiment of an electronic device 50 is shown in more detail. More precisely, Figure 4 The chip of the device 50 is shown as follows Figure 3 The groove 44 is, for example, along Figure 3 Cross-sectional view of plane AA.

[0099] The device 50, more precisely a chip, comprises a substrate 52. The substrate 52 corresponds to, for example Figure 1 The substrate 12 is preferably made of a semiconducting material, such as silicon or silicon carbide. The substrate 52 is made of a different material than the layer 54.

[0100] Device 50 includes, for example, a conductive layer (not shown) extending over a lower face of substrate 52 .

[0101] The device 50 comprises a layer 54 of gallium nitride. The thickness of the layer 54 is, for example, greater than 4 μm. The layer 54 corresponds to, for example Figure 1 Thus, Figure 3 The source and drain regions of transistor 26 shown in FIG are preferably located in layer 54. Layer 54 extends over the upper face of substrate 52. Layer 54 is in contact with layer 52, for example.

[0102] Layer 54 includes a cavity 56 extending from at least the upper face of layer 54 to the lower face of layer 54. Cavity 56 reaches the upper face of substrate 52. Thus, the bottom of cavity 56 includes part of the upper face of substrate 52.

[0103] Device 50 includes an insulating layer 58. Layer 58 covers the sidewalls of cavity 56. Layer 58 covers, for example, a peripheral portion of the portion of substrate 52 that forms the bottom of the cavity. A central portion of the portion of substrate 52 that forms the bottom of the cavity is not covered by layer 58. Layer 58 at least partially covers, for example, the upper face of layer 54, for example, at least the portion of the upper face of layer 54 that surrounds cavity 56.

[0104] Device 50 includes an interconnect network. In other words, device 50 includes a stack 60 of insulating layers covering the upper face of the chip. The insulating layers of stack 60 include conductive tracks and conductive vias for providing connections between components of device 50 or between device 50 and external devices.

[0105] The device 50 comprises an electrically conductive element 62 , for example made of metal. The electrically conductive element 62 corresponds, for example, to a metallization layer M0 of the interconnection network, ie to the conductive track layer closest to the layer 54 .

[0106] Element 62 extends at least over the entire height of trench 56. More precisely, element 62 reaches the bottom of cavity 56 and contacts substrate 52 via the central portion of the portion of substrate 52 that forms the bottom of the cavity. Element 62 extends over the walls of the cavity, more precisely, over layer 58 covering the walls of the cavity. Furthermore, element 62 extends, for example, over a portion of the upper face of layer 54 surrounding cavity 56, more precisely, over a portion of layer 58 covering the upper face of layer 54 surrounding cavity 56, preferably on both sides of trench 44. Element 62 preferably does not contact layer 54. Element 62 is preferably completely separated from layer 54 by insulating layer 58.

[0107] exist Figure 4 In the example shown in FIG, element 62 does not fill cavity 56, and element 62 is covered by insulating material in cavity 56. Alternatively, element 62 may fill cavity 56 above layer 58.

[0108] Device 50 also includes a track 64. Track 64 is, for example, located in a coating layer, such as layer M1, that is higher than element 62. Track 64 preferably extends over the entire length of groove 44. Preferably, the entire groove 44 is thus covered by track 64. Element 62 and track 64 are connected by vias 66. For example, element 62 and track 64 are connected by vias located on both sides of the groove, for example, by having substantially the same number of vias 66 on one side of the groove as on the other side of the groove.

[0109] exist Figure 4 , the device 50 includes, for example, a conductive track 68. The track 68 corresponds to, for example Figure 3 The fingers 35 are shown in FIG. Track 38 is located, for example, in metallization layer M0. Track 68 extends, for example, over layer 58 and is in contact with layer 58.

[0110] exist Figure 4 In the example shown in FIG, only one track 68 is shown. In practice, there may be as many tracks 68 as there are fingers 35, i.e., as many rows 34. For a groove 44 located between two rows 34, the track 64 is coupled to the fingers 35 on both sides of the groove by means of through-holes 66.

[0111] As a variant, the element 62 is not coupled to the track 68 via the track 64 and the through-hole 66. The track 68 may be a continuation of the element 62 and thus in contact with it.

[0112] The method of manufacturing the device 50 includes, for example:

[0113] forming a substrate 52;

[0114] If appropriate, a conductive layer (not shown) is formed on the lower surface of the substrate 52;

[0115] forming layer 54, for example by epitaxy;

[0116] etching layer 54 to form cavity 56;

[0117] forming a layer 58 over the entire structure;

[0118] Etching a portion of layer 58 located at the center of the bottom of cavity 56;

[0119] depositing conductive elements 62;

[0120] annealing to form an electrical connection between the element 62 and the substrate (52); and

[0121] Form an interconnected network.

[0122] Figure 5 A more detailed diagram Figure 4 Another part of the device 50 of the embodiment shown in . More precisely, Figure 5 Pictured Figure 3 The pad 42 shown in FIG and the pad 70 for applying the drain voltage. The pad 70 is not shown in FIG. Figure 3 The pads 42 and 70 are located with Figure 4 , and is located in the same device 50 as that shown in FIG. Figure 5 The structure shown in Figure 4 Therefore, Figure 5 The structure shown in FIG. 5 includes substrate 52 , layer 54 , and layer 58 . Figure 5 The structure shown in also includes an interconnection network (not shown). In other words, Figure 5 The structure shown in FIG. 6 comprises a stack of insulating layers 60 ( Figure 5 (not shown), the stack comprises conductive tracks and conductive vias.

[0123] Device 50 includes a cavity 72 in layer 54. Cavity 72 extends from at least the upper face of layer 54 to the lower face of layer 54. Cavity 72 reaches the upper face of substrate 52. Thus, the bottom of cavity 72 includes part of the upper face of substrate 52.

[0124] Layer 58 covers the sidewalls of cavity 72. Layer 58 covers, for example, a peripheral portion of the portion of substrate 52 that forms the bottom of cavity 72. At least a central portion of the portion of substrate 52 that forms the bottom of cavity 72 is not covered by layer 58. Layer 58, for example, at least partially covers the upper face of layer 54, for example, covers at least the portion of the upper face of layer 54 that surrounds cavity 72.

[0125] exist Figure 5 , the device 50 includes a pad 42, such as a bonding pad Figure 3 The pad 42 is preferably made of a conductive material, such as metal, for example Figure 4 72. The solder pad 42 is formed of the same material as the element 62 shown in FIG. The solder pad 42 fills the cavity 72, preferably completely fills the cavity 72. The solder pad 42 preferably covers the portion of the layer 58 that is located in the cavity 72. The solder pad 42 is in contact with the substrate 52, more precisely, with the portion of the substrate 52 that forms the bottom of the cavity 72. The solder pad preferably extends from the upper face of the substrate 52 to at least the level of the opening of the cavity 72, preferably up to a level higher than the opening of the cavity 72. Thus, the solder pad 42 includes a portion that is located outside the cavity 72.

[0126] Pad 42 is coupled (preferably connected) to a voltage source that supplies Figure 3 The pads 42 are coupled (preferably connected) to said voltage source, for example via an interconnection network (not shown), more precisely via conductive tracks and conductive vias of the interconnection network (not shown).

[0127] Device 50 also includes a pad 70. Pad 70 is made of a conductive material, such as metal, such as the same material as pad 42, such as Figure 4 6. The solder pad 70 passes through layer 58 to layer 54. The solder pad 70 is thereby in contact with layer 54, preferably with the upper face of layer 54.

[0128] Pad 70 is coupled (preferably connected) to a voltage source that supplies Figure 3 The drain voltage of transistors 26 of row 34 shown in is coupled (preferably connected) to said voltage source, for example via an interconnection network (not shown), more precisely via conductive tracks and conductive vias of the interconnection network (not shown).

[0129] The device 50 includes, for example, a plurality of Figure 5 The pad 42 is preferably located at Figure 3 Similarly, device 50 includes, for example, a plurality of transistors 26 in combination with Figure 5 The pad 70 is preferably located at Figure 3 Around the plurality of transistors 26 shown in .

[0130] Figure 6 A portion of another embodiment of the electronic device 74 is shown in more detail. More precisely, Figure 6 The chip of device 74 is shown as follows Figure 3 The groove 44 is, for example, along Figure 3 Cross-sectional view of plane AA.

[0131] Device 74 includes the same elements as those of device 50. These elements will not be described in detail. Thus, device 74 includes substrate 52, layer 54, cavity 56, insulating layer 58, conductive element 62, and an interconnect network including stack 60 of insulating layers, conductive tracks 64, 68, and conductive vias 66.

[0132] Device 74 further comprises a conductive layer 76, for example made of metal, covering the lower face of substrate 52. Layer 76 is, for example, in contact with the lower face of substrate 52. Layer 76 extends at least opposite each trench 44.

[0133] Device 74 also includes layer 77. Layer 77 is an insulating layer. Layer 77 separates layer 76 from substrate 52. Layer 77, for example, contacts substrate 52 via its top surface and contacts layer 76 via its bottom surface. Thus, layer 76 and substrate 52 are not in contact.

[0134] For each trench 44, device 74 includes a conductive element 78, such as one made of metal, located in substrate 52. Element 78 spans substrate 52 and layer 77. Element 78 extends from the upper surface of substrate 52 to the lower surface of layer 77. The lower surface of element 78 contacts layer 76. Element 78 is located opposite the corresponding trench 44 and contacts it. More precisely, the upper surface of element 78 at least partially contacts element 62. The upper surface of element 78 contacts, for example, layer 58, such as the portion of layer 58 that extends above the bottom of cavity 56. Element 78 is sized such that element 62 does not contact substrate 52, and such that element 78 does not contact layer 54. In other words, the dimensions of element 78, in the plane of the upper surface of substrate 52, are less than or equal to the dimensions of the bottom of cavity 56. Furthermore, the dimensions of layer 58 , and more precisely of the portion of layer 58 covering the bottom of cavity 56 , are such that the central portion of the bottom of cavity 56 not covered by layer 58 is entirely constituted by element 78 .

[0135] The device further comprises a layer 79. The layer 79 laterally surrounds the element 78. Thus, the layer 79 separates the element 78 from the substrate 52. Thus, the element 78 is not in contact with the substrate 52.

[0136] exist Figure 6 In the embodiment shown in FIG, layer 76 is biased to Figure 3 The control voltage of transistor 26 is shown in FIG. Thus, Figure 3 The finger 35 shown in FIG. 3 (corresponding to, for example, Figure 6 Track 68 shown in FIG is biased by means of conductive elements 78 and 62. Substrate 52 is biased, for example, to a source voltage, and layer 54 is biased, for example, to a drain voltage.

[0137] In one embodiment, Figure 6The device does not include element 78. Cavity 56 is then formed through layer 54 and substrate 52. The upper face of layer 76 then forms the bottom of cavity 56.

[0138] Examples and references for methods of manufacturing device 74 Figure 4 The method described is the same, except for the step of forming substrate 52 , which then includes forming element 78 .

[0139] Figure 7 A more detailed diagram Figure 6 Another part of the embodiment of the device 74 shown in FIG. More precisely, Figure 7 There are illustrated a pad 42 for applying a control voltage, a pad 80 for applying a source voltage, and a pad 70 for applying a drain voltage.

[0140] Pads 42, 70 and 80 are located with Figure 6 , and is located in the same device 74 as that shown in FIG. Figure 7 The structure shown in Figure 6 Therefore, Figure 7 The structure shown in FIG. 5 includes substrate 52 , layer 54 , layer 77 , layer 58 , and layer 76 . Figure 7 The structure shown in also includes an interconnection network (not shown). In other words, Figure 7 The structure shown in FIG. 6 comprises a stack of insulating layers 60 ( Figure 7 (not shown), the stack comprises conductive tracks and conductive vias.

[0141] Pad 70 and Figure 5 Thus, pad 70 passes through layer 58 and contacts layer 54. Pad 70 is coupled (preferably connected) to a voltage source that supplies Figure 3 The drain voltage of transistors 26 of row 34 shown in is coupled (preferably connected) to said voltage source, for example via an interconnection network (not shown), more precisely via conductive tracks and conductive vias of the interconnection network (not shown).

[0142] Pad 80 and Figure 5 Thus, pad 80 is located in a cavity that passes through layer 54 to reach substrate 52. Pad 80 is separated from layer 54 by insulating layer 58. Pad 80 is in contact with substrate 52. Pad 80 is in contact with substrate 52. Figure 5 The difference between the pad 42 shown in FIG is that the pad 80 receives a source voltage. In other words, the pad 80 is coupled (preferably connected) to a voltage source that supplies Figure 3The pad 80 is coupled (preferably connected) to said voltage source, for example via an interconnection network (not shown), more precisely via conductive tracks and conductive vias of the interconnection network (not shown).

[0143] Figure 7 The pad 42 shown in FIG. Figure 5 The pad 80 shown in FIG. 8 is identical to the pad 42 and comprises a conductive portion 42a, for example made of metal, filling the cavity through the layers 54 and 77 to the level of the lower face of the layer 54. The pad 42 comprises a conductive portion 42b, for example made of metal, located in the substrate 52. The portion 42b is for example Figure 6 . Portion 42b extends from the upper face of substrate 52 to the lower face of substrate 52. The upper face of portion 42b is in contact with portion 42a, and the lower face of portion 42b is in contact with layer 76. The upper face of portion 42b is in contact with layer 58, for example. The dimensions of portion 42b are such that portion 42b does not contact layer 54, but only contacts portion 42a and, if appropriate, layer 58. The dimensions of portion 42b are such that portion 42a does not contact substrate 52, for example.

[0144] Pad 42 is coupled (preferably connected) to a voltage source that supplies Figure 3 The pads 42 are coupled (preferably connected) to said voltage source, for example via an interconnection network (not shown), more precisely via conductive tracks and conductive vias of the interconnection network (not shown).

[0145] The device also includes a layer 82. The layer 82 laterally surrounds the element 42b. Thus, the layer 82 separates the element 42b from the substrate 52. Therefore, the element 42b does not contact the substrate 52.

[0146] Combine Figures 3 to 7 The described embodiments are destined, for example, to be present in a power conversion circuit, for example in a vehicle, for example in an automobile.

[0147] An advantage of the described embodiment is that the delay between the application of the control voltage or the change of the control voltage and the receipt of the control voltage or the receipt of the control change is short.

[0148] Another advantage of the described embodiments is that current peaks of the control voltage are less likely to damage transistors the more quickly the peaks are shared over a large number of transistors.

[0149] Another advantage of the described embodiment is that it does not result in any modification of the transistors.

[0150] A number of embodiments and variations have been described, and those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations.

[0151] Finally, based on the functional description provided above, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.

[0152] A device (50, 74) includes trenches (44), each of the trenches (44) including a conductive element (62, 78) configured to electrically couple a finger (35) of a transistor gate (26) located on a first side of a first layer (54) to a second layer (52, 76) extending on a second side of the first layer (54).

[0153] A method of fabricating a device (50, 74) includes forming trenches (44), the trenches (44) each including a conductive element (62, 78) configured to electrically couple a finger (35) of a transistor gate (26) located on a first side of a first layer (54) to a second layer (52, 76) extending on a second side of the first layer (54).

[0154] The second layer (52, 76) is configured to be biased to a control voltage of the transistor (26).

[0155] The transistors (26) are arranged in rows (34), and the transistors (26) in the same row (34) are coupled together through their gates via the same finger (35). The rows (34) are arranged in columns (41), and the columns (41) are separated by trenches (44). The conductive elements (62, 78) of each trench (44) separate the two columns (41) and are coupled to one end of each finger (35) of the two columns.

[0156] Each column (41) is located between two trenches (44), and each finger (35) is coupled at one end to a conductive element (62, 78) of one of the two trenches (44) and at the other end to a conductive element (62, 78) of the other of the two trenches (44).

[0157] The first layer (54) is made of GaN, AlN or AlGaN.

[0158] The device (50, 74) includes a semiconductor substrate (52) on a second side of the first layer (54), the substrate (52) forming the second layer.

[0159] Each trench (44) includes a cavity (56) extending through the first layer (54), the bottom of the cavity (56) including the substrate (52), and the conductive element (62) includes a third conductive layer (62) extending over the walls and bottom of the cavity (56).

[0160] The device (50, 74) comprises a semiconductor substrate (52) located on the second side of the first layer (54), the surface of the substrate (52) furthest from the first layer (54) being covered with a fourth conductive layer (76), the fourth layer (76) forming the second layer.

[0161] The third layer (76) is made of metal.

[0162] Each trench (44) includes a cavity (56) extending through the first layer (54), the bottom of the cavity (56) being located at the face of the substrate (52) closest to the first layer (54), the conductive element (62, 78) including a third conductive layer (62) extending over the walls and bottom of the cavity and a portion (78) located in the substrate (52) in contact with the third layer (62) and in contact with the fourth layer (76).

[0163] The third layer (62) is separated from the first layer (54) by a fifth insulating layer (58).

[0164] The substrate (52) is made of silicon or silicon carbide.

[0165] Each conductive element (62, 78) is coupled to a finger (35) through an interconnect network of tracks and vias.

[0166] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to encompass all possible embodiments along with the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A device, characterized in that include: a first layer having a first side and a second side; a second layer below the first layer and coupled to a second side of the first layer; a plurality of fingers on a first side of the first layer, each finger corresponding to a gate of a plurality of transistors; and A plurality of trenches in the first layer, each trench including a conductive element electrically coupling the finger to the second layer.

2. The device according to claim 1, characterized in that The second layer is configured to be biased to a control voltage of the transistor.

3. The device according to claim 1, characterized in that The transistors are arranged in rows, and the transistors in the same row have a collective gate corresponding to the same finger. The rows are arranged in columns, and the columns are separated by trenches. The conductive element of each trench separates the two columns and is coupled to one end of each finger in the fingers of the two columns.

4. The device according to claim 3, characterized in that Wherein each column is located between two trenches, each finger is coupled at one end to a conductive element of one of the two trenches and at another end to a conductive element of the other of the two trenches.

5. The device according to claim 1, wherein The first layer is GaN, AlN or AlGaN.

6. The device according to claim 1, characterized in that The second layer is a semiconductor substrate.

7. The device according to claim 6, characterized in that Each trench includes a cavity extending through the first layer, the bottom of the cavity exposing the substrate, and the conductive element includes a third conductive layer extending over the wall of the cavity and the bottom of the cavity.

8. The device according to claim 1, wherein The invention comprises a fourth conductive layer located on the bottom of the second layer and separated from the first layer by the second layer, wherein the second layer is a semiconductor substrate.

9. The device according to claim 8, characterized in that The third layer is metal.

10. The device according to claim 8, characterized in that Each trench includes a cavity extending through the first layer, the bottom of the cavity being located at the surface of the substrate closest to the first layer, and the conductive element includes a third conductive layer extending over the wall and bottom of the cavity and a portion located in the substrate in contact with the third layer and in contact with the fourth layer.

11. The device according to claim 8, characterized in that The third layer is separated from the first layer by a fifth layer of insulating material.

12. The device according to claim 6, characterized in that The semiconductor substrate is made of silicon or silicon carbide.

13. The device according to claim 1, wherein Each conductive element is coupled to a finger through an interconnect network of tracks and vias.

14. A device, characterized in that include: semiconductor substrates; a semiconductor layer on a semiconductor substrate; a first transistor group; a first finger extending in a first direction on the semiconductor layer and corresponding to a collective gate of the first transistor group; a second transistor group; a second finger extending in the first direction on the semiconductor layer and corresponding to the collective gate of the second transistor group; a trench in the semiconductor layer between the first finger and the second finger; and A conductive element in the trench contacts the semiconductor substrate and electrically couples the first finger and the second finger to the semiconductor substrate.

15. The device according to claim 14, wherein The device includes a conductive layer located below the semiconductor substrate and in contact with the semiconductor substrate.

16. The device according to claim 15, wherein An electrical contact is included that extends through the semiconductor layer, the semiconductor substrate, and contacts the conductive layer.

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