Wafer and wafer unit

Abstract

The utility model discloses a wafer and a wafer unit, and relates to the technical field of wafers. The semiconductor device comprises a semiconductor substrate, a plurality of functional areas are arranged in the semiconductor substrate, the semiconductor substrate is provided with a first surface and a second surface which are oppositely distributed, a plurality of dielectric layers are arranged on the first surface, circuit areas are arranged in the dielectric layers, a plurality of grooves are formed in the semiconductor substrate, and the circuit areas are arranged in the grooves. A groove is formed in the middle of the dielectric layer, a cutting channel is formed between every two adjacent dielectric layers, the cutting channels are communicated with the groove and form a cutting groove, a protruding part is arranged in the cutting groove, the cutting groove is divided into two isolation grooves which are distributed oppositely and are both in an L shape through the protruding part, and the isolation grooves are filled with isolation media. According to the invention, during cutting, through the isolation medium filled in the isolation groove, cracks can be prevented from diffusing to the functional area to cause damage to the functional area, so that damage to the chip is avoided, and the chip is more practical.

Description

Technical Field

[0001] The present application relates to the field of wafer technology, and in particular to a wafer and a wafer unit. Background Art

[0002] A wafer refers to a silicon chip used to manufacture silicon semiconductor integrated circuits. Due to its round shape, it is called a wafer. A wafer generally includes a semiconductor substrate, a functional area, and a dielectric layer. The functional area and the dielectric layer are both located on the semiconductor substrate. During the chip production process, the wafer needs to be cut into multiple wafer units. In the prior art, when the wafer is cut, cracks are easily formed at the cutting point. The cracks are easily spread to the functional area and cause damage to the functional area, thereby causing damage to the chip. Therefore, a wafer and a wafer unit are proposed. Utility Model Content

[0003] The purpose of this application is to solve the technical problem that when cutting a wafer, cracks are easily formed at the cutting point, and the cracks are easily spread to the functional area and cause damage to the functional area, thereby causing damage to the chip. This application provides a wafer and a wafer unit.

[0004] In order to achieve the above-mentioned purpose, this application specifically adopts the following technical solutions:

[0005] A wafer includes a semiconductor substrate, wherein multiple functional areas are arranged in the semiconductor substrate, the semiconductor substrate has a first surface and a second surface distributed oppositely, multiple dielectric layers are provided on the first surface, and a circuit area is provided in the dielectric layer. Multiple grooves are constructed on the semiconductor substrate, and cutting paths are formed between two adjacent dielectric layers. The cutting paths are connected to the grooves to form cutting grooves. A protrusion is provided in the cutting groove, and the protrusion separates the cutting groove into two isolation grooves distributed oppositely and both constructed in an L shape. The isolation groove is filled with isolation dielectric.

[0006] Furthermore, the entrance of the cutting path is structured in an outwardly expanding cone shape.

[0007] Furthermore, a cutting mark is constructed on the raised portion.

[0008] Furthermore, the isolation medium is made of polyimide.

[0009] Furthermore, the isolation dielectric covers a side of the dielectric layer away from the semiconductor substrate.

[0010] Furthermore, an insulating adhesive layer is provided on the second surface, a base plate is bonded to the insulating adhesive layer, a sticky material layer is provided on one side of the base plate, and a covering layer is bonded to the sticky material layer.

[0011] Furthermore, a plurality of convex rings are provided on opposite sides of the base plate.

[0012] A wafer unit comprises the above-mentioned wafer.

[0013] The beneficial effects of the present application are as follows: during cutting, the present application can prevent cracks from spreading to the functional area and causing damage to the functional area through the isolation medium filled in the isolation groove, thereby avoiding damage to the chip, and is therefore more practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the cross-sectional structure of this application;

[0015] Figure 2 This application Figure 1 Enlarged view of point A in the middle;

[0016] Figure 3 This application Figure 1 Enlarged view of point B in the middle;

[0017] Figure 4 This application Figure 1 Enlarged view of point C in the middle.

[0018] Figure numerals: 1, semiconductor substrate; 2, functional area; 3, dielectric layer; 4, circuit area; 5, groove; 6, cutting road; 7, raised portion; 8, isolation medium; 9, cutting mark; 10, insulating adhesive layer; 11, base material; 12, adhesive material layer; 13, coating layer; 14, raised ring. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0020] like Figures 1-4 As shown, a wafer proposed in one embodiment of the present application includes a semiconductor substrate 1, wherein a plurality of functional regions 2 are provided in the semiconductor substrate 1, and electronic devices such as transistors are provided in the functional regions 2. The semiconductor substrate 1 has a first surface and a second surface that are relatively distributed. A plurality of dielectric layers 3 are provided on the first surface. The semiconductor substrate 1 serves to support the dielectric layer 3. A circuit region 4 is provided in the dielectric layer 3. A conductive structure is formed in the circuit region 4. The conductive structure can be connected to the electronic devices in the functional region 2 to serve as a lead, thereby electrically connecting the electronic devices to devices outside the chip. A plurality of grooves 5 are constructed on the semiconductor substrate 1. The depth of the grooves 5 is greater than the depth of the functional region 2. The grooves 5 are constructed in an inverted T shape. A cutting path 6 is formed between two adjacent dielectric layers 3. The cutting path 6 is connected to the grooves 5 and forms a cutting groove. A protrusion 7 is provided in the cutting groove. The top surface of the protrusion 7 is on the same horizontal plane as the top surface of the dielectric layer 3. The cutting groove is divided into two isolation grooves that are relatively distributed and both have an L-shape by the protrusion 7. The isolation groove is filled with an isolation dielectric 8.

[0021] During chip production, the isolation groove is filled with an isolation medium 8. When the wafer needs to be cut into multiple wafer units, the raised portion 7 is used as a cutting reference for cutting. The cutting process can be performed by mechanical cutting or laser cutting. During the cutting process, the isolation medium 8 filled in the isolation groove can prevent cracks from spreading to the functional area 2 and causing damage to the functional area 2, thereby avoiding chip damage.

[0022] In summary, during cutting, the present application can prevent cracks from spreading to the functional area 2 and causing damage to the functional area 2 by filling the isolation medium 8 in the isolation groove, thereby avoiding damage to the chip, and is therefore more practical.

[0023] like Figure 3 As shown, in some embodiments, the entrance of the cutting road 6 is configured to be tapered outward;

[0024] As mentioned above, when filling the isolation medium 8 into the isolation groove, the inlet of the cutting path 6 is configured to be tapered outward, which facilitates the filling of the isolation medium 8 and makes the operation more convenient.

[0025] like Figure 3 As shown, in some embodiments, a cutting mark 9 is configured on the raised portion 7;

[0026] With reference to the above, during cutting, by setting the cutting marking line 9, the cutting process is made more convenient and more accurate.

[0027] like Figure 2-Figure 3 As shown, in some embodiments, the isolation medium 8 is made of polyimide, which refers to a type of polymer containing an imide ring on the main chain and is one of the organic polymer materials with the best comprehensive performance;

[0028] Referring to the above, polyimide is selected as the material of the isolation medium 8. When the isolation medium 8 is filled, it can be spin-coated. At the same time, when cutting, it can be done by mechanical cutting without laser cutting, thereby reducing cutting costs.

[0029] like Figure 2 As shown, in some embodiments, the isolation dielectric 8 covers the side of the dielectric layer 3 away from the semiconductor substrate 1. This design can increase board-level stress and enhance the reliability of solder joints.

[0030] like Figure 4 As shown, in some embodiments, an insulating adhesive layer 10 is provided on the second surface, a base plate 11 is bonded to the insulating adhesive layer 10, an adhesive material layer 12 is provided on one side of the base plate 11, and a covering layer 13 is bonded to the adhesive material layer 12;

[0031] Referring to the above, during the chip production process, an insulating adhesive layer 10 is coated on the second surface, and the base material 11 is bonded to the insulating adhesive layer 10. After the insulating adhesive layer 10 is cured, a sticky material layer 12 is coated on the base material 11, and then the covering layer 13 is bonded to the sticky material layer 12. After the cutting is completed, ultraviolet irradiation or high-temperature heating is used to reduce the viscosity of the sticky material layer 12, and then the covering layer 13 is torn off from the sticky material layer 12 to achieve the packaging of the wafer unit. Compared with the existing technology, which requires multiple glue dispensing on the back of the wafer during packaging, it is more convenient.

[0032] like Figure 4 As shown, in some embodiments, a plurality of convex rings 14 are provided on opposite sides of the base plate 11, and the convex rings 14 are hexagonal in structure;

[0033] Referring to the above, when the base material 11 is bonded to the insulating adhesive layer 10, the provision of multiple convex rings 14 can increase the bonding area between the base material 11 and the insulating adhesive layer 10, thereby improving the connection strength. When the adhesive material layer 12 is coated on the base material 11, the provision of multiple convex rings 14 can increase the bonding area between the base material 11 and the adhesive material layer 12, thereby further improving the connection strength.

[0034] A wafer unit comprises the above-mentioned wafer.

[0035] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer comprising a semiconductor substrate (1), wherein a plurality of functional regions (2) are provided in the semiconductor substrate (1), wherein the semiconductor substrate (1) has a first surface and a second surface that are relatively distributed, wherein a plurality of dielectric layers (3) are provided on the first surface, wherein a circuit region (4) is provided in the dielectric layer (3), wherein: A plurality of grooves (5) are constructed on the semiconductor substrate (1), a cutting path (6) is formed between two adjacent dielectric layers (3), the cutting path (6) is connected to the groove (5) and forms a cutting groove, a protrusion (7) is provided in the cutting groove, and the protrusion (7) separates the cutting groove into two relatively distributed isolation grooves, both of which are L-shaped, and the isolation groove is filled with an isolation medium (8).

2. The wafer according to claim 1, wherein: The entrance of the cutting path (6) is in the shape of a cone that expands outwards.

3. The wafer according to claim 1, wherein: A cutting mark (9) is formed on the raised portion (7).

4. The wafer according to claim 1, wherein: The material of the isolation medium (8) is polyimide.

5. The wafer according to claim 1, wherein: The isolation medium (8) covers the side of the dielectric layer (3) away from the semiconductor substrate (1).

6. The wafer according to claim 1, wherein: An insulating adhesive layer (10) is provided on the second surface, a base plate (11) is bonded to the insulating adhesive layer (10), an adhesive material layer (12) is provided on one side of the base plate (11), and a coating layer (13) is bonded to the adhesive material layer (12).

7. The wafer according to claim 6, wherein: A plurality of convex rings (14) are provided on opposite sides of the base plate (11).

8. Wafer unit, characterized in that Comprising the wafer as described in any one of claims 1-7.

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