Intelligent watchdog shielding circuit

Abstract

The utility model discloses an intelligent watchdog shielding circuit. The intelligent watchdog shielding circuit comprises two triodes and two resistors, one pin of the resistor R51 is connected with a No.1 pin D3.3 V of the serial debugging interface P10; the other pin of the resistor R51 is connected with a No.2 pin DBENA of a serial debugging interface P10, and is also connected with a collector electrode of the triode Q1 and a base electrode of the triode Q2 at the same time; a base electrode of the triode Q1 is connected with a pin 1 nRST of the watchdog chip U14 through a resistor R53; a collector electrode of the triode Q2 is connected with a pin 7 NRST of the microcontroller U13; and emitters of the triode Q1 and the triode Q2 are connected with the ground GND. The intelligent watchdog shielding circuit has the beneficial effects that the intelligent watchdog shielding circuit is realized by using a simplified design and fewest components, the use is flexible, the debugging is convenient, and the product testing time is saved; the watchdog function can be automatically started after debugging is finished, and the system has the advantages of being stable in performance, high in reliability, high in cost performance, high in environment adaptability and the like.

Description

Technical Field

[0001] The utility model relates to a protection circuit, in particular to a circuit which can intelligently shield a watchdog when connected to a simulator. Background Art

[0002] In embedded systems with programmable power supplies, a watchdog is often required to ensure the system can be reset properly in the event of an abnormality. A watchdog is essentially a counter that can be reset after a specified period of time. When the watchdog is enabled, the counter begins counting automatically. If it is not reset after a specified period of time, the watchdog generates a reset signal to restart the system.

[0003] Programmable power supplies typically use an independent watchdog chip. This type of watchdog features a feed pin (typically connected to a GPIO) and a reset pin (typically connected to RESET). If the feed pin's voltage level doesn't change within a certain timeframe, the reset pin changes state, resetting the MCU. The advantage of this type of watchdog is that it requires no configuration, is ready for use upon power-up, and offers strong system resilience. However, its disadvantage is that it cannot be disabled, limiting its flexibility. Hardware simulation often requires setting breakpoints for debugging, and in these cases, the watchdog can reset due to a failure to feed the watchdog in time, preventing simulation from continuing. While it's possible to disable the watchdog macro at the start of simulation, this is cumbersome and poses a safety hazard if the watchdog is forgotten to be re-enabled after debugging. Therefore, the best approach is to disable the watchdog under specific conditions for simulation debugging, re-enabling it automatically when simulation is no longer needed. Utility Model Content

[0004] The utility model is an intelligent watchdog shielding circuit designed to solve the above technical problems.

[0005] The technical solution adopted by the utility model to solve its technical problems is:

[0006] An intelligent watchdog shielding circuit includes two transistors Q1 and Q2 and two resistors R51 and R53; one pin of the resistor R51 is connected to pin 1 D3.3V of a serial debug interface P10; the other pin of the resistor R51 is connected to pin 2 DBENA of the serial debug interface P10, and is also connected to the collector of the transistor Q1 and the base of the transistor Q2; the base of the transistor Q1 is connected to pin 1 nRST of a watchdog chip U14 through resistor R53; the collector of the transistor Q2 is connected to pin 7 NRST of a microcontroller U13; and the emitters of the transistors Q1 and Q2 are connected to ground GND.

[0007] The intelligent watchdog shielding circuit, pin 1 D3.3V of the serial debug interface P10 is simultaneously connected to pins 1, 24, 36 and 48 of the microcontroller U13; pin 3 of the serial debug interface P10 is connected to the ground GND; pin 4 SWDIO of the serial debug interface P10 is connected to pin 34 of U13; pin 5 SWCLK of the serial debug interface P10 is connected to pin 37 of U13.

[0008] The intelligent watchdog shielding circuit, the 7-pin NRST of the microcontroller U13 is connected to the 1-pin nRST of the watchdog chip U14 through the resistor R48.

[0009] In the intelligent watchdog shielding circuit, the NRST pin 7 of the microcontroller U13 is connected to the pin 1 of the reset interface P11, and the pin 2 of P11 is connected to the ground GND.

[0010] In the intelligent watchdog shielding circuit, both the transistor Q1 and the transistor Q2 are NPN transistors.

[0011] The working principle of this utility model is as follows: By designing a special circuit and utilizing the conductive principle of NPN transistors Q1 and Q2, when an external emulator is connected, the DBENA terminal is turned on, and the current generated by the 3.3V voltage flows through the DBENA terminal through transistor Q1 to Q2 and then to the GND terminal. At this time, the NRST terminal remains in a high-level state, and the watchdog timer does not reset. When the external emulator is disconnected, the DBENA terminal is turned off, and the current generated by the 3.3V voltage flows through the NRST terminal through transistor Q2 to the GND terminal, and the watchdog timer operates normally.

[0012] The beneficial effects of the utility model are: using a simplified design and a minimum of components to realize an intelligent watchdog shielding circuit, which is flexible to use, convenient to debug, and saves product testing time; the watchdog function can be automatically enabled after debugging is completed, and it has the characteristics of stable performance, high reliability, high cost performance, and strong environmental adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the circuit principle block diagram of the utility model;

[0014] Figure 2 This is a schematic diagram of the watchdog circuit used in this utility model;

[0015] Figure 3 This is the wiring schematic diagram of the pin header of the utility model;

[0016] Figure 4 This is the schematic diagram of the watchdog reset circuit of the utility model;

[0017] Figure 5 This is an example MCU schematic diagram used in this utility model. DETAILED DESCRIPTION

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] like Figure 1 、 2 As shown in Figure 5, the utility model provides an intelligent watchdog shielding circuit, which includes two transistors Q1 and Q2 and two resistors R51 and R53; one pin of the resistor R51 is connected to pin 1 D3.3V of the serial debug interface P10; the other pin of the resistor R51 is connected to pin 2 DBENA of the serial debug interface P10, and is also connected to the collector of the transistor Q1 and the base of the transistor Q2; the base of the transistor Q1 is connected to pin 1 nRST of the watchdog chip U14 through the resistor R53; the collector of the transistor Q2 is connected to pin 7 NRST of the microcontroller U13; the emitters of the transistors Q1 and Q2 are connected to the ground GND.

[0020] like Figure 3 As shown, in the intelligent watchdog shielding circuit, pin 1 D3.3V of the serial debug interface P10 is simultaneously connected to pins 1, 24, 36 and 48 of the microcontroller U13; pin 3 of the serial debug interface P10 is connected to the ground GND; pin 4 SWDIO of the serial debug interface P10 is connected to pin 34 of U13; and pin 5 SWCLK of the serial debug interface P10 is connected to pin 37 of U13.

[0021] The intelligent watchdog shielding circuit, the 7-pin NRST of the microcontroller U13 is connected to the 1-pin nRST of the watchdog chip U14 through the resistor R48; the model of the microcontroller U13 is GD32F103CBT6.

[0022] like Figure 4 As shown, in the intelligent watchdog shielding circuit, pin 7 (NRST) of microcontroller U13 is connected to pin 1 of reset interface P11, and pin 2 of P11 is connected to ground (GND). For example, if a button is used for reset, simply connect one end of the button to the NRST pin and the other end to ground or the negative power supply to complete the circuit loop. When the button is pressed, the NRST pin receives a low-level signal, triggering a reset. The watchdog chip U14 is SGM823.

[0023] In the intelligent watchdog shielding circuit, the transistor Q1 and the transistor Q2 are both NPN transistors, and their model is BCW66G.

[0024] When the intelligent watchdog shielding circuit is connected to an external simulator, the DBENA terminal in the circuit is conductive, and current flows through transistor Q1 to the GND terminal. At this time, the NRST terminal connected to it remains high, and the watchdog function does not operate. When the external simulator is disconnected, the DBENA terminal is not conductive, and current flows through transistor Q2 to the GND terminal, allowing the watchdog function to operate normally.

[0025] The present invention is not limited to the above-mentioned optimal implementation mode. Any other product identical or similar to the present invention derived by anyone under the inspiration of the present invention shall fall within the protection scope of the present invention.

Claims

1. An intelligent watchdog shielding circuit, comprising two transistors Q1 and Q2 and two resistors R51 and R53; characterized in that: One pin of the resistor R51 is connected to pin 1 D3.3V of the serial debug interface P10; the other pin of the resistor R51 is connected to pin 2 DBENA of the serial debug interface P10, and is also connected to the collector of the transistor Q1 and the base of the transistor Q2; the base of the transistor Q1 is connected to pin 1 nRST of the watchdog chip U14 through the resistor R53; the collector of the transistor Q2 is connected to pin 7 NRST of the microcontroller U13; the emitters of the transistors Q1 and Q2 are connected to the ground GND.

2. The intelligent watchdog shielding circuit according to claim 1, wherein: Pin 1 D3.3V of the serial debug interface P10 is simultaneously connected to pins 1, 24, 36 and 48 of the microcontroller U13; pin 3 of the serial debug interface P10 is connected to the ground GND; pin 4 SWDIO of the serial debug interface P10 is connected to pin 34 of U13; pin 5 SWCLK of the serial debug interface P10 is connected to pin 37 of U13.

3. The intelligent watchdog shielding circuit according to claim 1, wherein: The 7th pin NRST of the microcontroller U13 is connected to the 1st pin nRST of the watchdog chip U14 through the resistor R48.

4. The intelligent watchdog shielding circuit according to claim 1, wherein: Pin 7 NRST of the microcontroller U13 is connected to pin 1 of the reset interface P11, and pin 2 of P11 is connected to ground GND.

5. The intelligent watchdog shielding circuit according to claim 1, wherein: The transistor Q1 and the transistor Q2 are both NPN transistors.

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