High-temperature aging test equipment for silicon photosemiconductor

Abstract

The utility model discloses a silicon photosemiconductor high-temperature aging test device, which relates to the technical field of chip aging test, and comprises an aging test host, a temperature control host, a monitoring host and a sealed heating cavity, a plurality of signal transmission interfaces are arranged at the top of the aging test host, an interface conversion plate is arranged above the signal transmission interfaces, and the interface conversion plate is connected with the temperature control host. The interface conversion board is provided with a chip test interface, one end of the chip test interface is connected with the signal transmission interface, the other end is used for accessing a to-be-tested chip, and the aging test host is internally at least provided with a power supply, a control board and a detection board connected with the chip plug socket; the sealed heating cavity is fixedly connected to the top of the aging test host, a heating device and a temperature sensor are arranged in the sealed heating cavity, a door body is arranged at the top of the sealed heating cavity, the temperature control host is connected with the sealed heating cavity, and the monitoring host is connected with the aging test host and the temperature control host. According to the utility model, the problem of low working performance of the test board in a high-temperature environment is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip aging testing, in particular to a silicon photonic semiconductor high-temperature aging testing device. Background Art

[0002] Market demand for semiconductor products is increasing, and with it, the requirements for product quality and reliability are also rising. Semiconductor burn-in testing can simulate chip usage conditions in various environments before chip production and product testing. Through methods such as accelerated testing, it can detect chip performance degradation, predict chip lifespan and stability, and ensure product quality and reliability. However, current testing solutions generally consist of two parts: a standard high-temperature burn-in chamber and a custom-developed signal test board. Chip burn-in conditions vary, with temperatures typically ranging from 60°C, 85°C, 125°C, and 150°C. The signal test board must be placed in a high-temperature burn-in chamber during use. However, prolonged exposure of the signal board to high temperatures can lead to the following issues: reduced board lifespan; inability of the chips within the board to operate stably at high temperatures; and significant degradation of board performance at high temperatures. Furthermore, standard high-temperature burn-in chambers are expensive and bulky.

[0003] A Chinese patent document with publication number CN220324145U, published on January 9, 2024, discloses a memory chip aging test system, comprising: a test device including: a mounting base for mounting the chip to be tested; a aging test board electrically connected to the chip to be tested; and a high-temperature box housing the mounting base and the aging test board; an input device having a reserved interface electrically connected to the aging test board; a controller electrically connected to the high-temperature box and the input device; a detection device electrically connected to the test device; and a display device electrically connected to the detection device, the display device including a test monitoring interface unit and an early warning unit, the early warning unit setting an early warning threshold to trigger an alarm signal, and the test monitoring interface unit displaying the alarm signal. This utility model can promptly detect abnormal memory chips, improving the detection efficiency of memory chips.

[0004] However, the technical solution with the above announcement number CN220324145U has the mounting base for the chip to be tested and the aging test board both set inside a high-temperature box, which reduces the life of the board, significantly reduces its performance, and even makes it unable to work stably. Utility Model Content

[0005] In order to solve the above technical problems, the utility model proposes a silicon photonic semiconductor high-temperature aging test device, which solves the problems of low working performance and reduced service life of the test board in a high-temperature environment.

[0006] The utility model is realized by adopting the following technical solutions:

[0007] A silicon photonic semiconductor high-temperature aging test device comprises an aging test host, a temperature control host, a monitoring host, and a sealed heating chamber. Several signal transmission interfaces are provided on the top of the aging test host, interface conversion boards are respectively provided above the signal transmission interfaces, a chip test interface is provided on the interface conversion board, one end of the chip test interface is connected to the signal transmission interface, and the other end is used to access the chip to be tested. The aging test host is internally provided with at least a power supply, a control board, and a detection board connected to the chip socket; the sealed heating chamber is fixedly connected to the top of the aging test host, the chip test interface is located in the sealed heating chamber, a heating device and a temperature sensor are provided in the sealed heating chamber, a door is provided on the top of the sealed heating chamber, the temperature control host is connected to the sealed heating chamber, and the monitoring host is connected to the aging test host and the temperature control host.

[0008] The chip test interface is a plug-in interface for plugging in and out of the chip to be tested or a probe interface for engaging with the chip to be tested.

[0009] The heating device is a heating tube or a heating plate.

[0010] The door body is a transparent glass cover plate.

[0011] There are 10-14 signal transmission interfaces and chip test interfaces, and the signal transmission interfaces correspond to the chip test interfaces one by one.

[0012] The exterior of the aging test host is further provided with a display panel and manual operation buttons.

[0013] The temperature control host is also provided with a display panel and manual operation buttons.

[0014] The connection between the sealed heating chamber and the aging test host is filled with high-temperature resistant silica gel to ensure the sealing of the chamber.

[0015] The shell of the aging test host is made of high-temperature resistant silicone material, and the shell of the sealed heating chamber is made of metal material.

[0016] The monitoring host is wirelessly connected to the aging test host and the temperature control host.

[0017] Compared with the prior art, the advantages of this utility model are:

[0018] 1. In the present invention, a plurality of signal transmission interfaces are provided on the top of the aging test host, and an interface conversion board is further provided above the signal transmission interface. A chip test interface is provided on the interface conversion board. One end of the chip test interface is connected to the signal transmission interface, and the other end is used to access the chip to be tested, so that the high temperature area in the aging test host is isolated and miniaturized, and a special high temperature cavity is provided. The main control board and the detection board are located in the low temperature area in the aging test host, which can be used for a long time, greatly improving the service life, and the control board signal and detection are not affected by high temperature, thereby improving the test accuracy. The temperature control host only needs to heat the sealed heating cavity, and the heating space is small, which reduces energy loss, and can be remotely monitored in real time through the monitoring host.

[0019] 2. In the present invention, the chip test interface can choose a plug-in interface or a probe interface. The plug-in interface provides a more solid physical connection by combining the pins of the chip with the slots of the interface, reduces the risk of poor contact, has better anti-interference performance, and can reduce costs; the probe interface can be flexibly adjusted according to chips of different types and sizes, is suitable for testing chips with various non-standard packages, and can reduce the impact of mechanical stress on the chip, and can quickly contact the chip and complete the test.

[0020] 3. In the present invention, the door of the sealed heating chamber is provided with a transparent glass cover, so that the condition of the chip in the heating chamber can be directly observed.

[0021] 4. In the present invention, the exterior of the aging test host and the temperature control host are also provided with a display panel and manual operation buttons, so that the equipment can be controlled both online and offline, and is flexible to use.

[0022] 5. In this utility model, one device can test multiple products at the same time; one PC can control the linkage of multiple devices at the same time.

[0023] 6. In this utility model, the monitoring host can remotely control the heating temperature, monitor aging conditions such as voltage monitoring, current monitoring and low current monitoring (nA level), configure the parameters of the aging test host and store historical data.

[0024] 7. In the present invention, the connection between the sealed heating chamber and the aging test host is filled with high-temperature resistant silicone, which can further ensure the sealing of the chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, wherein:

[0026] Figure 1 It is a structural diagram of the utility model;

[0027] Figure 2This is a schematic diagram of the direct plug-in interface of the utility model;

[0028] Figure 3 This is a schematic diagram of the probe-type interface of the utility model;

[0029] Figure 4 This is the principle diagram of the utility model.

[0030] Markings in the figure:

[0031] 1. Aging test host, 2. Sealed heating chamber, 3. Temperature control host, 4. Monitoring host, 5. Signal transmission interface, 6. Interface conversion board, 7. Direct plug-in interface, 8. Probe interface, 9. Door, 10. Chip to be tested, 11. Power supply, 12. Control board, 13. Detection board, 14. Chip test interface. DETAILED DESCRIPTION

[0032] Example 1

[0033] As the most basic embodiment of the present invention, a silicon photonic semiconductor high-temperature aging test device includes an aging test host 1, a temperature control host 3, a monitoring host 4, and a sealed heating chamber 2. The top of the aging test host 1 is provided with 12 signal transmission interfaces 5, and an interface conversion board 6 is also provided above the signal transmission interface 5. A chip test interface 14 is provided on the interface conversion board 6, and one end of the chip test interface 14 is connected to the signal transmission interface 5, and the other end is used to access the chip to be tested 10. The aging test host 1 is internally provided with at least a power supply 11, a control board 12 and a detection board 13 connected to the chip socket; the sealed heating chamber 2 is fixedly connected to the top of the aging test host 1, so that the chip test interface 14 is located in the sealed heating chamber 2, a heating plate and a temperature sensor are provided in the sealed heating chamber 2, and a door 9 is provided on the top of the sealed heating chamber 2, the temperature control host 3 is connected to the sealed heating chamber 2, and the monitoring host 4 is connected to the aging test host 1 and the temperature control host 3.

[0034] In this embodiment, a plurality of signal transmission interfaces 5 are provided on the top of the aging test host 1, and an interface conversion board 6 is further provided above the signal transmission interface 5. A chip test interface 14 is provided on the interface conversion board 6, and one end of the chip test interface 14 is connected to the signal transmission interface 5, and the other end is used to access the chip to be tested 10, so as to isolate the high temperature area in the aging test host 1, miniaturize the high temperature area, and set a special high temperature cavity. The control board 12 and the detection board 13 are located in the low temperature area in the aging test host 1, which can be used for a long time, greatly improving the service life, and the control board 12 signal and detection are not affected by high temperature, thereby improving the test accuracy. The temperature control host 3 only needs to heat the sealed heating chamber 2, and the heating space is small, which reduces energy loss and is more energy-saving. It can also be remotely monitored in real time through the monitoring host 4.

[0035] Example 2

[0036] As a preferred embodiment of the present invention, a silicon photonic semiconductor high-temperature aging test device includes an aging test host 1, a temperature control host 3, a monitoring host 4, and a sealed heating chamber 2. The top of the aging test host 1 is provided with 10 signal transmission interfaces 5, and an interface conversion board 6 is also provided above the signal transmission interface 5. A chip test interface 14 is provided on the interface conversion board 6, and one end of the chip test interface 14 is connected to the signal transmission interface 5, and the other end is used to access the chip to be tested 10. The aging test host 1 is internally provided with at least a power supply 11, a control board 12 and a detection board 13 connected to the chip socket; the sealed heating chamber 2 is fixedly connected to the top of the aging test host 1, so that the chip test interface 14 is located in the sealed heating chamber 2, a heating plate and a temperature sensor are provided in the sealed heating chamber 2, and a door 9 is provided on the top of the sealed heating chamber 2, the temperature control host 3 is connected to the sealed heating chamber 2, and the monitoring host 4 is connected to the aging test host 1 and the temperature control host 3.

[0037] The chip test interface 14 is a plug-in interface 7 for plugging in and out of the chip under test 10 .

[0038] In this embodiment, the chip test interface 14 is a plug-in interface 7, which provides a relatively strong physical connection by combining the pins of the chip inserted into the slot of the interface, reduces the risk of poor contact, has good anti-interference performance, and can reduce costs.

[0039] Example 3

[0040] As another preferred embodiment of the present invention, a silicon photonic semiconductor high-temperature aging test device includes an aging test host 1, a temperature control host 3, a monitoring host 4, and a sealed heating chamber 2. The top of the aging test host 1 is provided with 14 signal transmission interfaces 5, and an interface conversion board 6 is also provided above the signal transmission interface 5. A chip test interface 14 is provided on the interface conversion board 6, and one end of the chip test interface 14 is connected to the signal transmission interface 5, and the other end is used to access the chip to be tested 10. The aging test host 1 is internally provided with a power supply 11, a control board 12 and a detection board 13 connected to the chip socket; the sealed heating chamber 2 is fixedly connected to the top of the aging test host 1, so that the chip test interface 14 is located in the sealed heating chamber 2, a heating plate and a temperature sensor are provided in the sealed heating chamber 2, and a door 9 is provided on the top of the sealed heating chamber 2, the temperature control host 3 is connected to the sealed heating chamber 2, and the monitoring host 4 is connected to the aging test host 1 and the temperature control host 3.

[0041] The chip test interface 14 is a probe-type interface 8 for engaging with the chip to be tested 10 .

[0042] In this embodiment, the chip test interface 14 is a probe-type interface 8, which can be flexibly adjusted according to chips of different types and sizes. It is suitable for testing chips with various non-standard packages, and can reduce the impact of mechanical stress on the chip. It can quickly contact the chip and complete the test.

[0043] Example 4

[0044] As the best embodiment of the present utility model, a silicon photonic semiconductor high-temperature aging test device includes an aging test host 1, a temperature control host 3, a monitoring host 4, and a sealed heating chamber 2. The top of the aging test host 1 is provided with 12 signal transmission interfaces 5, and an interface conversion board 6 is also provided above the signal transmission interface 5. A chip test interface 14 is provided on the interface conversion board 6. One end of the chip test interface 14 is connected to the signal transmission interface 5, and the other end is used to access the chip to be tested 10. The signal transmission interface 5 and the chip test interface 14 correspond one-to-one to the inside of the aging test host 1. At least a power supply 11, a control board 12 and a detection board 13 connected to the chip socket are provided, which are used to provide the voltage, current and signal required for the chip to work, and detect the voltage, current and nA level current of the chip under high temperature state, and monitor in real time; the sealed heating chamber 2 is fixedly connected to the top of the aging test host 1, so that the chip test interface 14 is located in the sealed heating chamber 2, and a heating plate and a temperature sensor are provided in the sealed heating chamber 2. A door body 9 is provided on the top of the sealed heating chamber 2, the temperature control host 3 is connected to the sealed heating chamber 2, and the monitoring host 4 is connected to the aging test host 1 and the temperature control host 3.

[0045] The temperature control host 3 in this embodiment is a high-precision high-temperature / constant temperature control system. After testing in the range of 25-200 degrees Celsius, the error is stable at plus or minus 0.3 degrees Celsius, and the maximum does not exceed plus or minus 0.5 degrees Celsius. The maximum output power is 2000w, which meets the power output during application. It can correspond to heating materials such as heating tubes and ceramic heating plates, and has a constant temperature control system. Through PID adjustment, high-precision temperature control is achieved. The control software of the monitoring host 4 can monitor temperature changes in real time and generate curves.

[0046] The chip test interface 14 is a probe-type interface 8, which is used to engage with the chip to be tested 10. It can be flexibly adjusted according to chips of different types and sizes. It is suitable for testing chips with various non-standard packages, and can reduce the impact of mechanical stress on the chip. It can quickly contact the chip and complete the test.

[0047] The door 9 is a transparent glass cover, so that the condition of the chip in the heating chamber can be directly observed during the test.

[0048] The exterior of the aging test host 1 and the temperature control host 3 are also provided with a display panel and manual operation buttons, so that the equipment can be controlled both online and offline, and is flexible to use.

[0049] The connection between the sealed heating chamber 2 and the aging test host 1 is filled with high-temperature resistant silica gel to ensure the sealing of the chamber.

[0050] The shell of the aging test host 1 is made of high-temperature resistant silicone material, and the shell of the sealed heating chamber 2 is made of metal material.

[0051] The monitoring host 4 is wirelessly connected to the aging test host 1 and the temperature control host 3. The monitoring host can remotely control and display the heating temperature, monitor the aging conditions such as voltage monitoring, current monitoring and low current monitoring (nA level), configure the parameters of the aging test host and store historical data.

[0052] In this embodiment, the high-temperature area in the aging test host is isolated and miniaturized, and a special high-temperature chamber is set up. The main control board 12 and the detection board 13 are located in the low-temperature area in the aging test host, which can be used for a long time, greatly improving the service life. In addition, the signal and detection of the control board 12 are not affected by high temperature, which improves the accuracy of the test. The temperature control host only needs to heat the sealed heating chamber, and the heating space is small, which reduces energy loss. The aging condition of the internal chip can be intuitively observed from the top of the heating chamber, and can be remotely monitored in real time and historical data can be stored through the monitoring host.

Claims

1. A silicon photonic semiconductor high temperature aging test device, comprising an aging test host (1), a temperature control host (3), and a monitoring host (4), characterized in that: The apparatus further comprises a sealed heating chamber (2), wherein the top of the aging test host (1) is provided with a plurality of signal transmission interfaces (5), and interface conversion boards (6) are respectively provided above the signal transmission interfaces (5), and a chip test interface (14) is provided on the interface conversion board (6), wherein one end of the chip test interface (14) is connected to the signal transmission interface (5), and the other end is used to access the chip to be tested (10), and the inside of the aging test host (1) is provided with at least a power supply (11), a control board (12), and a detection board (13) connected to the chip socket; the sealed heating chamber (2) is fixedly connected to the top of the aging test host (1) so that the chip test interface (14) is located in the sealed heating chamber (2), a heating device and a temperature sensor are provided in the sealed heating chamber (2), and a door (9) is provided on the top of the sealed heating chamber (2), the temperature control host (3) is connected to the sealed heating chamber (2), and the monitoring host (4) is connected to the aging test host (1) and the temperature control host (3).

2. The silicon photonic semiconductor high temperature aging test equipment according to claim 1, characterized in that: The chip test interface (14) is a plug-in interface (7) for plugging in and out of the chip to be tested (10), or a probe interface (8) for engaging with the chip to be tested (10).

3. The silicon photonic semiconductor high temperature aging test equipment according to claim 2, characterized in that: The heating device is a heating tube or a heating plate.

4. The silicon photonic semiconductor high temperature aging test equipment according to claim 1, characterized in that: The door body (9) is a transparent glass cover.

5. The silicon photonic semiconductor high temperature aging test equipment according to claim 2, characterized in that: There are 10-14 signal transmission interfaces (5) and chip test interfaces (14), and the signal transmission interfaces (5) correspond to the chip test interfaces (14) in a one-to-one manner.

6. The silicon photonic semiconductor high temperature aging test equipment according to claim 1, characterized in that: The aging test host (1) is also provided with a display panel and manual operation buttons on the outside.

7. The silicon photonic semiconductor high temperature aging test equipment according to claim 1, characterized in that: The temperature control host (3) is also provided with a display panel and manual operation buttons.

8. The silicon photonic semiconductor high temperature aging test equipment according to claim 1, characterized in that: The connection between the sealed heating chamber (2) and the aging test host (1) is filled with high-temperature resistant silica gel to ensure the sealing of the chamber.

9. The silicon photonic semiconductor high temperature aging test equipment according to claim 1, characterized in that: The shell of the aging test host (1) is made of high-temperature resistant silicone material, and the shell of the sealed heating chamber (2) is made of metal material.

10. The silicon photonic semiconductor high temperature aging test equipment according to claim 1, characterized in that: The monitoring host (4) is wirelessly connected to the aging test host (1) and the temperature control host (3).

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