Multifunctional reset driving circuit

Abstract

The utility model relates to the technical field of interactive machine reset drive circuits, in particular to a multifunctional reset drive circuit, which comprises a reset button SW1, a CPU (central processing unit), a logic AND gate control module and a watchdog control module, the reset button SW1 and the CPU are respectively connected with the input end of the logic AND gate control module, and the watchdog control module is connected with the input end of the logic AND gate control module. The logic AND gate control module is in signal connection with the watchdog control module; the reset key SW1 pulls down the level of the input end of the watchdog control module so as to drive the watchdog control module to be used for outputting a low level for resetting; and the CPU outputs a high level or a low level to the input end of the logic AND gate control module so as to drive the logic AND gate control module to output the high level or the low level to the watchdog control module. The reset circuit has high output driving capability, and a reset system is more stable and reliable; the multifunctional reset effect is achieved, the cost is reduced, and the use efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of reset drive circuits for interactive machines, in particular to a multifunctional reset drive circuit. Background Art

[0002] The market is increasingly demanding multifunctional switches, significantly increasing product complexity. Simple reset chips are no longer sufficient for these products. While some highly integrated reset chips may offer advanced technology and performance, they come at a high price. Therefore, the market urgently needs a low-cost, high-drive, multifunctional reset design to accommodate complex products and improve reliability. Summary of the Invention

[0003] In response to the problems of the prior art, the utility model provides a multifunctional reset drive circuit with an ingenious design and a logic control method having a high output drive capability, which means that they can generate a clear output signal after receiving a logic signal, ensure the output signal quality, and effectively transmit and process digital information. Therefore, the logic control method is used to enhance the driving capability of the reset signal, and the reset system is more stable and reliable; at the same time, the reset button SW1 or the CPU can be used to control the reset, which has strong versatility and achieves a multifunctional reset effect, which is conducive to reducing costs and improving usage efficiency.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0005] The utility model provides a multifunctional reset drive circuit, which includes a reset button SW1, a CPU, a logic and gate control module and a watchdog control module. The reset button SW1 and the CPU are respectively connected to the input end of the logic and gate control module, and the logic and gate control module is connected to the watchdog control module signal;

[0006] The reset button SW1 pulls down the input level of the watchdog control module, thereby driving the watchdog control module to output a low level for reset;

[0007] The CPU drives the logic AND gate control module to output a high level or a low level to the watchdog control module by outputting a high level or a low level to the input end of the logic AND gate control module; when the logic AND gate control module outputs a high level to the watchdog control module, it is used to disable the watchdog control module; when the logic AND gate control module outputs a low level to the watchdog control module, it is used to drive the watchdog control module to output a low level for reset.

[0008] The multifunctional reset circuit further includes a single-way buffer, and the CPU is connected to the input end of the logic AND gate control module via the single-way buffer.

[0009] The single-channel buffer includes a chip U1, and the model of the chip U1 is SN74LVC1G125.

[0010] The watchdog control module includes a chip U2, the model of the chip U2 is PT7A7514WEX, an input end of the chip U2 is provided with an MR pin, and the output end of the logic AND gate control module is connected to the MR pin.

[0011] The logic AND gate control module includes a chip U3, the model of the chip U3 is SN74LVC08A, and the reset button SW1 is connected to the BT_RESET pin of the chip U3.

[0012] The multifunctional reset circuit further includes an eight-channel buffer, and the output end of the logic AND gate control module is connected to the input end of the eight-channel buffer.

[0013] The eight-channel buffer includes a chip U4, and the model of the chip U4 is SN74LVC244A.

[0014] Beneficial effects of the utility model:

[0015] When the present invention is working, the CPU outputs a low level to the logic AND gate control module, and the logic AND gate control module then outputs a low level to the watchdog control module. The watchdog control module triggers the output of a low level to reset all chips connected to the logic AND gate control module. When the system is performing important operations, it is not desired that the watchdog control module trigger a reset operation due to a minor fault or error. The CPU outputs a high level to the watchdog control module to disable the watchdog control module, thereby achieving the reset effect of disabling the watchdog and maintaining stable operation of the system. Of course, the present invention can also drive the watchdog control module to work by pressing the reset button SW1. After pressing the reset button SW1, the watchdog control The input level of the module will be pulled low, and the reset operation will be triggered by the built-in timer of the watchdog control module. The output low level is used to reset all chips connected to the logic and gate control module. The utility model is cleverly designed and adopts a logic control method of a watchdog control module in combination with a logic and gate control module. The logic control method has high output driving capability, which means that they can generate a clear output signal after receiving a logic signal, ensure the quality of the output signal, and effectively transmit and process digital information. Therefore, the logic control method is used to enhance the driving capability of the reset signal, and the reset system is more stable and reliable. At the same time, the reset button SW1 or the CPU can be used to control the reset, which has strong versatility and can achieve a multi-functional reset effect, which is conducive to reducing costs and improving usage efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a principle framework diagram of a multifunctional reset drive circuit of the present utility model.

[0017] Figure 2 This is a circuit diagram of the watchdog control module and single-channel buffer of the utility model.

[0018] Figure 3 This is a circuit diagram of the logic AND gate control module and the eight-channel buffer of the present utility model. DETAILED DESCRIPTION

[0019] In order to facilitate the understanding of those skilled in the art, the present invention is further described below in conjunction with the embodiments and drawings. The contents mentioned in the embodiments are not intended to limit the present invention. The present invention is described in detail below in conjunction with the drawings.

[0020] A multifunctional reset drive circuit, such as Figures 1 to 3 As shown, it includes a reset button SW1, a CPU, a logic and gate control module and a watchdog control module, wherein the reset button SW1 and the CPU are respectively connected to the input end of the logic and gate control module, and the logic and gate control module is signal-connected to the watchdog control module;

[0021] The reset button SW1 pulls down the input level of the watchdog control module, thereby driving the watchdog control module to output a low level for reset;

[0022] The CPU drives the logic AND gate control module to output a high level or a low level to the watchdog control module by outputting a high level or a low level to the input end of the logic AND gate control module; when the logic AND gate control module outputs a high level to the watchdog control module, it is used to disable the watchdog control module; when the logic AND gate control module outputs a low level to the watchdog control module, it is used to drive the watchdog control module to output a low level for reset.

[0023] Specifically, when the embodiment of the present application is working, the CPU outputs a low level to the logic AND gate control module, and the logic AND gate control module then outputs a low level to the watchdog control module. The watchdog control module triggers the output of a low level to reset all chips connected to the logic AND gate control module. When the system is performing important operations, it is not desired that the watchdog control module trigger a reset operation due to a minor fault or error. The CPU disables the watchdog control module by outputting a high level to the watchdog control module, thereby achieving the reset effect of disabling the watchdog to maintain stable operation of the system. Of course, the embodiment of the present application can also drive the watchdog control module to work by pressing the reset button SW1. After pressing the reset button SW1, the watchdog The input level of the control module will be pulled low, and the reset operation will be triggered by the built-in timer of the watchdog control module, and the output low level is used to reset all chips connected to the logic and gate control module; the embodiment of the present application is cleverly designed, and adopts a watchdog control module with a logic control method of the logic and gate control module. The logic control method has high output driving capability, which means that they can generate a clear output signal after receiving the logic signal, ensure the output signal quality, and effectively transmit and process digital information. Therefore, the logic control method is used to enhance the driving capability of the reset signal, and the reset system is more stable and reliable; at the same time, the reset button SW1 or the CPU can be used to control the reset, which has strong versatility and can achieve a multi-functional reset effect, which is conducive to reducing costs and improving usage efficiency.

[0024] In this embodiment of the present application, the multifunctional reset circuit further includes an eight-channel buffer, the output of the logic AND gate control module being connected to the input of the eight-channel buffer. The eight-channel buffer includes chip U4, model number SN74LVC244A. Specifically, this embodiment of the present application distributes the reset signal to each chip via an eight-way buffer. The eight-way buffer enhances signal strength, ensuring undistorted signal transmission over long distances and improving the overall performance and reliability of the reset distribution system.

[0025] In an embodiment of the present application, the multifunctional reset circuit further includes a single-channel buffer, through which the CPU is connected to the input of the logic AND gate control module. The single-channel buffer includes a chip U1, the model of which is SN74LVC1G125; the watchdog control module includes a chip U2, the model of which is PT7A7514WEX; the input of the chip U2 is provided with an MR pin, and the output of the logic AND gate control module is connected to the MR pin; the logic AND gate control module includes a chip U3, the model of which is SN74LVC08A, and the reset button SW1 is connected to the BT_RESET pin of the chip U3.

[0026] Specifically, the watchdog control module mainly monitors the power rail to ensure that the system powers on normally; the chip U2 of the watchdog control module has its own 2.93V voltage detection. When powered on, after VCC reaches 1V, Reset_n will output a logic low level; when VCC rises, Reset_n still remains in a low level state; when VCC rises to the Reset_n threshold value, the internal timer will release Reset_n after 200ms; after pressing the reset button SW1, the MR pin of the chip U2 of the watchdog control module will be pulled low, and the timer of the chip U2 of the watchdog control module will trigger Reset_n to output a low level for a global reset; the CPU can output a low level to the logic AND gate control module through the GPIO port, and the chip U3 of the logic AND gate control module outputs a low level to the MR pin of the chip U2 of the watchdog control module, and then the chip U2 of the watchdog control module triggers Reset_n to output a low level to reset all chips.

[0027] The specific control logic of the multifunctional reset drive circuit in the embodiment of the present application is:

[0028] Power-on reset part:

[0029] After power-on, when VCC reaches 1V, Reset_N of the chip U2 of the watchdog control module will output a logic low level. When VCC rises, Reset_N remains in a low level state until VCC rises to the Reset_N threshold. The internal timer of the chip U2 of the watchdog control module will release Reset_N after 200ms; the WDI signal of the chip U2 of the watchdog control module is connected to the GPIO port of the CPU. WDI requires the CPU to continuously output high and low levels. After the board is powered on and the CPU starts sending the WDI dog feeding signal, the system starts normally.

[0030] The Reset_N of the chip U2 of the watchdog control module is connected to a channel of the chip U3 of the logic AND gate control module to output the reset signal RESET; the RESET signal is connected to the chip U4 of the eight-channel buffer, and after reset distribution, 8 groups of reset signals (1*CPU, 4*PHY, 1*LED, 1*POE, 1*flash) are distributed.

[0031] Reset after system abnormality:

[0032] When the CPU is abnormal or the single-board software runs abnormally, WDI will hang. At this time, WDI will only output a high level or a low level, and cannot feed the dog and clear it normally. When this abnormal situation occurs, the WDO signal of the chip U2 of the watchdog control module will output a low level to the chip U1 of the single-channel buffer, and after logical judgment, it will output a low level to the chip U3 of the logic AND gate control module. The chip U3 of the logic AND gate control module will then output a low level to the MR pin of the chip U2 of the watchdog control module, and then the chip U2 of the watchdog control module will output Reset_N to the chip U3 of the logic AND gate control module. The chip U3 of the logic AND gate control module will output a low level to the chip U4 of the eight-channel buffer for global reset.

[0033] Software online control reset:

[0034] The CPU can output a low level to the chip U3 of the logic AND gate control module through the GPIO port, and the chip U3 of the logic AND gate control module then outputs a low level to the chip U4 of the eight-channel buffer. Then the chip U4 of the eight-channel buffer distributes the reset signal to each IC to complete the reset of each chip in the system.

[0035] Reset button part:

[0036] After pressing the reset button SW1, a low-level signal is output to the chip U3 of the logic AND gate control module. After logical judgment, the chip U3 of the logic AND gate control module outputs a low level to the MR pin of the chip U2 of the watchdog control module. At this time, the timer of the chip U2 of the watchdog control module triggers Reset_N to output a low level, and finally a global reset is achieved through the chip U4 of the eight-way buffer.

[0037] Disable the watchdog:

[0038] When the system is performing important operations, it is not desired that the watchdog control module trigger a reset operation due to minor faults or errors. The CPU can output a high level to the single-channel buffer chip U1 through the GPIO port. At this time, WDO_N will only output a high level, thereby disabling the reset function of the watchdog control module to maintain stable operation of the system.

[0039] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention is disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of the above-disclosed technical contents without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technology of the present invention, which do not depart from the content of the technical solution of the present invention, are within the scope of the technical solution of the present invention.

Claims

1. A multifunctional reset drive circuit, characterized in that: It includes a reset button SW1, a CPU, a logic and gate control module and a watchdog control module, wherein the reset button SW1 and the CPU are respectively connected to the input end of the logic and gate control module, and the logic and gate control module is signal-connected to the watchdog control module; The reset button SW1 pulls down the input level of the watchdog control module, thereby driving the watchdog control module to output a low level for reset; The CPU drives the logic AND gate control module to output a high level or a low level to the watchdog control module by outputting a high level or a low level to the input end of the logic AND gate control module; when the logic AND gate control module outputs a high level to the watchdog control module, it is used to disable the watchdog control module; when the logic AND gate control module outputs a low level to the watchdog control module, it is used to drive the watchdog control module to output a low level for reset.

2. The multifunctional reset driving circuit according to claim 1, characterized in that: The multifunctional reset circuit further includes a single-way buffer, and the CPU is connected to the input end of the logic AND gate control module via the single-way buffer.

3. The multifunctional reset driving circuit according to claim 2, wherein: The single-channel buffer includes a chip U1 , and the model of the chip U1 is SN74LVC1G125.

4. The multifunctional reset driving circuit according to claim 1, characterized in that: The watchdog control module includes a chip U2, the model of the chip U2 is PT7A7514WEX, an input end of the chip U2 is provided with an MR pin, and the output end of the logic AND gate control module is connected to the MR pin.

5. The multifunctional reset driving circuit according to claim 1, characterized in that: The logic AND gate control module includes a chip U3 , the model of the chip U3 is SN74LVC08A, and the reset button SW1 is connected to the BT_RESET pin of the chip U3 .

6. The multifunctional reset driving circuit according to claim 1, characterized in that: The multifunctional reset circuit further includes an eight-channel buffer, and the output end of the logic AND gate control module is connected to the input end of the eight-channel buffer.

7. The multifunctional reset driving circuit according to claim 6, characterized in that: The eight-channel buffer includes a chip U4 , and the model of the chip U4 is SN74LVC244A.

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