Package structure

Abstract

The present disclosure provides a package structure including a substrate, a wafer disposed on the substrate, the wafer having a wafer back surface remote from the substrate, a heat sink disposed over the substrate, and a substrate disposed over the heat sink. The heat sink has a surface facing the wafer, a thermal interface material disposed between the wafer and the heat sink, and a twin layer disposed on at least one side of the thermal interface material and in direct contact with the thermal interface material.

Description

Technical Field

[0001] The embodiments of the present utility model relate to packaging technology, and in particular to a packaging structure with a twin layer. Background Art

[0002] Electronic components are becoming increasingly lightweight, thin, short, and compact, with high performance, high transmission efficiency, and high heat generation per unit area. For example, the heat generation of a Pentium processor-based central processing unit (CPU) was only 20W in the past, but the Pentium 4 exceeds 80W, with CPU operating temperatures reaching over 150°C. According to the International Technology Roadmap for Semiconductors (ITRS), the future semiconductor industry development path, the heat generation of low-end computers will increase from the current approximately 100W to nearly 120W within the next few years, while the heat generation of high-end computers will rise significantly from the original 150W to over 180W. Operating frequencies will also increase from 2GHz to over 4GHz.

[0003] Traditional components generate low heat. The simplest solution is to add heat sinks or fans to improve heat dissipation. However, as the functionality and thermal power density of electronic components increase significantly, the requirements for thermal management technology become increasingly stringent. In the path by which component heat is transferred to the external environment, in addition to the low thermal resistance of the chip itself and the use of high-performance heat dissipation components, the connection density between components and the thermal conductivity of the bonding materials will become key factors in achieving breakthroughs in heat dissipation technology. Typical mechanical contact interfaces are rough or even wavy, with numerous insulating gaps between materials, which can significantly hinder heat conduction. Thermal interface materials (TIMs) are commonly used in integrated circuit (IC) assembly and electronic component heat dissipation. Their primary function is to fill the contact gap between two materials, improving system heat dissipation while effectively reducing thermal impedance. A good thermal interface material must have the following conditions: (1) good heat dissipation properties, that is, high thermal conductivity and low thermal impedance; (2) easy assembly and rework; (3) high compressibility so that it can withstand external compressive stress when fixed to the bonding surface and can properly fill the gaps between the interfaces to facilitate heat flow; (4) good wettability with electronic components and heat sink fins; and (5) high reliability and long service life.

[0004] Thermal grease is one of the earliest thermal interface materials. It is composed of silicone or hydrocarbons with different fillers. The thermal resistance of traditional thermal grease is about 1K·cm. 2 / W. In recent years, the thermal resistance value can be reduced to about 0.2K·cm 2 / W. However, conventional thermal pastes still present numerous problems. Due to the inherently high viscosity of the material, they are unable to completely fill gaps on the bonding surface, requiring a pressure of approximately 300 kPa to achieve ideal heat dissipation performance. Furthermore, because thermal pastes are made of polymers, they cannot withstand the relative displacement between the heat sink fins and the chip, resulting in a pump-out effect. Furthermore, prolonged exposure to high temperatures can cause the polymer to chemically react and separate from the internal filler, significantly reducing the wettability of the bonding surface. This phenomenon is known as dry-out.

[0005] Elastomeric thermal pads are thermal interface materials based on polymer silicone rubber, used to replace thermal paste. Their thermal resistance is 1K·cm 2 / W to 3K·cm 2 / W, making it unsuitable for higher-end cooling systems. While it has the advantage of being easy to form and assemble, it requires the application of a high pressure of approximately 700kPa to function properly. Another thermal interface material, thermal tapes, are adhesive-coated substrates such as polyimide (PI), fiberglass, or aluminum foil. While this material has the advantage of not requiring additional mechanical clamping, its heat dissipation performance remains suboptimal.

[0006] Phase change materials combine the excellent heat dissipation of thermal paste with the ease of processing of elastic thermal pads. They can exhibit good thermal conductivity above or below the melting point (approximately 50°C to 80°C). However, when the temperature is above the melting point, the adhesion will decrease, so additional mechanical force (approximately 300KPa) must be applied during use. Although phase change materials have a good thermal impedance value comparable to thermal paste (approximately 0.3K·cm 2 / W to 0.7K·cm 2 / W), and can effectively solve the problems of pumping effect and drying out, but due to reworkability considerations, thermal paste is generally chosen in high-end cooling systems.

[0007] To address the shortcomings of polymer materials, the industry has developed low-melting-point alloy thermal interface materials (melting points range from approximately 40°C to 200°C). These utilize the low melting points of certain eutectic indium-based alloys. When electronic components operate, the heat dissipated melts the low-melting-point alloys into a liquid state, allowing them to fill the interfacial pores. Furthermore, metals themselves have excellent thermal conductivity, resulting in excellent heat dissipation.

[0008] However, voids in the thermal interface material may reduce the heat dissipation effect, thereby affecting the reliability of the package structure. Although existing packaging technologies are generally sufficient to meet their intended purposes, they are not yet completely satisfactory in all aspects. Utility Model Content

[0009] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0010] One embodiment of the present disclosure relates to a packaging structure, which includes a substrate, a chip arranged on the substrate, the chip having a back surface away from the substrate, a heat sink arranged above the substrate, the heat sink having a surface facing the chip, a thermal interface material arranged between the chip and the heat sink, and a twin layer arranged on at least one side of the thermal interface material and in direct contact with the thermal interface material.

[0011] According to one embodiment of the present invention, the twin layer is disposed between the thermal interface material and the heat sink, and the twin layer includes a plurality of separated portions spaced apart from each other at the same level.

[0012] According to one embodiment of the present invention, the crystal structure of the twin layer contains at least 1% twin structures.

[0013] According to one embodiment of the present invention, the twin layer has a thickness of 0.1 to 100 microns.

[0014] According to one embodiment of the present invention, the metal layer has a thickness of 0.001 to 10 microns.

[0015] According to one embodiment of the present invention, the heat sink is a metal heat dissipation cover and / or heat dissipation fins.

[0016] According to one embodiment of the present invention, the heat sink includes a metal layer located on the surface, and the metal layer has a thickness of 0.001 to 10 microns.

[0017] According to one embodiment of the present invention, the metal layer includes a plurality of separated parts spaced apart from each other on the same level.

[0018] According to one embodiment of the present invention, the chip has a vertical projection area on the surface of the heat sink, and the coverage rate of the thermal interface material on the back surface of the chip or the vertical projection area is greater than 90%.

[0019] According to one embodiment of the present invention, the twin layer is configured to at least partially blend into the thermal interface material.

[0020] The beneficial effect of the present invention is that the present invention provides a twin layer located between the thermal interface material and the chip and / or the heat sink. In the hot pressing process of pressing the heat sink and the chip, the generation of pores can be reduced at the interface of the thermal interface material close to the chip and / or the heat sink, thereby improving the chip side coverage of the thermal interface material on the back surface of the chip and / or the heat sink side coverage on the surface of the heat sink. This is beneficial to improving the heat dissipation effect and reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale and are provided for illustrative purposes only. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the components of the embodiments of the present invention. It should also be noted that the accompanying drawings illustrate only exemplary embodiments of the present disclosure and, therefore, should not be considered to limit its scope. The present disclosure is equally applicable to other embodiments.

[0022] Figures 1 to 4 1 is a schematic cross-sectional view illustrating a package structure at different manufacturing stages according to some embodiments of the present disclosure.

[0023] Figure 5 is a schematic cross-sectional view showing a packaging structure according to some embodiments of the present disclosure.

[0024] Figures 6 to 8 1 is a schematic cross-sectional view illustrating a packaging structure at different manufacturing stages according to other embodiments of the present disclosure.

[0025] Figure 9 1 is a schematic cross-sectional view showing a packaging structure according to other embodiments of the present disclosure.

[0026] Figures 10 to 15 1 is a cross-sectional schematic diagram showing various packaging structures according to some other embodiments of the present disclosure.

[0027] The reference numerals are as follows:

[0028] 100:Package structure

[0029] 102:Substrate

[0030] 104: Chip

[0031] 104B: back surface

[0032] 105:Metal layer

[0033] 108: Twin layer

[0034] 200: packaging structure

[0035] 202: Radiator

[0036] 202S: Surface

[0037] 202B: bottom surface

[0038] 205:Metal layer

[0039] 208 / 208a / 208b: Twin layer

[0040] 210: Groove

[0041] 214 / 214':Viscose

[0042] 300: packaging structure

[0043] 302: Thermal interface material

[0044] 304: pressure head

[0045] 305: Indentation

[0046] 306:Hot pressing process

[0047] 402: Radiator

[0048] 404: Thermal interface material

[0049] 400 / 500 / 600 / 700 / 800: packaging structure

[0050] W1 / W2: Width DETAILED DESCRIPTION

[0051] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first element formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or configurations discussed.

[0052] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "higher," and the like may be used to facilitate description of the relationship between one component or parts and another component or parts in the accompanying drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is rotated to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after rotation. When spatially relative terms such as those listed above are used to describe a first component relative to a second component, the first component can be directly on the other component or can be between components or layers. When a component or layer is referred to as being "on" another component, it will be directly on the other component or layer and in direct contact with the other component or layer.

[0053] The terms used herein are intended only to illustrate specific embodiments and are not intended to limit the concepts of the present invention. Unless the expression has a clearly different meaning in the context, the expression used in the singular also encompasses the expression in the plural. In this specification, it should be understood that terms such as "comprising," "having," and "including" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or be added.

[0054] The following describes some embodiments of the present invention. Additional steps may be provided before, during, and / or after the various stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional components may be added to the packaging structure. Some of the components described may be replaced or deleted in different embodiments. Although some embodiments are discussed as performing steps in a specific order, these steps may also be performed in another logical order.

[0055] The present disclosure provides a packaging structure with a twin layer. The twin layer located between the thermal interface material and the chip and / or the heat sink can reduce the generation of pores at the interface of the thermal interface material close to the chip and / or the heat sink during the hot pressing process of pressing the heat sink and the chip, thereby improving the chip side coverage of the thermal interface material on the back surface of the chip and / or the heat sink side coverage on the surface of the heat sink, which is beneficial to improving the heat dissipation effect and reliability of the packaging structure. In addition, before the heat sink and the chip are pressed together, the thermal interface material can be temporarily fixed on the twin layer by applying pressure to avoid the thermal interface material from slipping before the heat sink and the chip are pressed together, thereby omitting the known organic adhesive to reduce production costs. Furthermore, performing the hot pressing process can not only melt the thermal interface material, but also simultaneously complete the soft baking of the adhesive, thereby simplifying the process steps and reducing production costs.

[0056] Figures 1 to 4 1 is a schematic cross-sectional view illustrating a package structure 100 at different manufacturing stages according to some embodiments of the present disclosure.

[0057] refer to Figure 1 , wafer 104 is placed on substrate 102. In some embodiments, substrate 102 may include a printed circuit board (PCB), a wafer substrate, an integrated circuit (IC) substrate, an interposer, a wafer carrier, a circuit carrier, and a display device. In some embodiments, wafer 104 may include a semiconductor wafer. A semiconductor wafer may be, for example, a small piece of semiconductor wafer formed by performing a semiconductor process on a semiconductor wafer and then separating the semiconductor wafer into individual dies. Wafer 104 may include an integrated circuit for processing and / or storing data, such as a field programmable gate array (FPGA), a processing unit (such as a graphics processing unit (GPU)) or a central processing unit (CPU), an application-specific integrated circuit (ASIC), a memory device (such as a memory controller, memory), etc. In some embodiments, wafer 104 may include a single crystal of the following materials: silicon (Si), germanium (Ge), silicon carbide (SiC), sapphire, gallium arsenide (GaAs), or gallium nitride (GaN). In some embodiments, disposing the chip 104 on the substrate 102 may include physically connecting the chip 104 to the substrate 102 using polymer adhesive, solder, or a combination thereof.

[0058] In some embodiments, the wafer 104 has a backside surface 104B ( Figure 1 In some embodiments, the wafer 104 may optionally include a metal layer 105 on the back surface 104B. The metal layer 105 is configured to improve the heat dissipation effect of the package structure 100 and reduce the thermal impedance of the package structure 100, but the present disclosure is not limited thereto.

[0059] In some embodiments, the metal layer 105 may include at least one of the following: aluminum / titanium / nickel vanadium / gold (Al / Ti / NiV / Au), aluminum / chromium / nickel vanadium / gold (Al / Cr / NiV / Au), aluminum / nickel vanadium / gold (Al / NiV / Au), aluminum / tungsten / gold (Al / W / Au), titanium / nickel vanadium / gold (Ti / NiV / Au), titanium tungsten / gold (TiW / Au), tungsten titanium / gold (WTi / Au), tungsten titanium / titanium / gold (WTi / Ti / Au), aluminum / titanium / nickel / gold (Al / Ti / Ni / Au), chromium / nickel vanadium / gold (Cr / NiV / Au), chromium / gold (Cr / Au), tungsten / gold (W / Au), titanium / nickel / silver (Ti / Ni / Ag ), titanium / silver (Ti / Ag), aluminum / titanium / nickel vanadium / silver (Al / Ti / NiV / Ag), aluminum / chromium / nickel vanadium / silver (Al / Cr / NiV / Ag), aluminum / nickel vanadium / silver (Al / NiV / Ag), aluminum / tungsten / silver (Al / W / Ag), titanium / nickel vanadium / silver (Ti / NiV / Ag), titanium tungsten / silver (TiW / Ag), tungsten titanium / silver (WTi / Ag), tungsten titanium / titanium / silver (WTi / Ti / Ag), aluminum / titanium / nickel / silver (Al / Ti / Ni / Ag), chromium / nickel vanadium / silver (Cr / NiV / Ag), chromium / silver (Cr / Ag), tungsten / silver (W / Ag), rhodium (Rh), iridium (Ir), palladium (Pd), and platinum (Pt). In some embodiments, the thickness of the metal layer 105 can be 0.001 to 10 microns (e.g., 0.5 to 1.6 microns or 0.1 to 2 microns). In some embodiments, the metal layer 105 may be formed by sputtering, evaporation, electroplating, or any suitable deposition process.

[0060] refer to Figure 2, a twin layer 108 is formed on the wafer 104 (or metal layer 105, if present). In some embodiments, the formation of the twin structure is due to the accumulated strain energy inside the material driving the atoms in a partial region to uniformly shear (shear) to a lattice position that is mirror-symmetrical with the unsheared atoms inside the die in which it is located. Twins may include: annealing twins and mechanical twins. In addition to the properties of the metal itself, the twin structure has properties such as better oxidation resistance, corrosion resistance, electrical conductivity, thermal conductivity, high temperature stability, etc. In some embodiments, the twin layer 108 has at least 1% (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80% or at least 90%) of twin structures in its crystal structure, which may have a high diffusion rate and, therefore, is compatible with the thermal interface material 302 (shown in FIG. 1 ). Figure 3 ) has a better bonding force, which can prevent the thermal interface material 302 from slipping. In addition, in the hot pressing process 306 of pressing the heat sink 202 and the chip 104 together, the generation of pores can be reduced at the interface of the thermal interface material 302 close to the chip 104. This part will be discussed later with Figure 4 In some embodiments, the twin structure may include various types (such as annealed twins or mechanical twins) and various sizes (such as nano twins), which may include multiple twin boundaries, such as Σ3, Σ9, or Σ27.

[0061] In some embodiments, the twin layer 108 may include gold, silver, copper, or a silver-copper alloy. In some embodiments, the twin layer 108 may have a thickness of 0.1 to 100 microns (e.g., 0.5 to 10 microns). When the thickness of the twin layer 108 is less than 0.1 microns, the advantages of twinning (e.g., high diffusion rate) are not significant. When the thickness of the twin layer 108 is greater than 100 microns, the twin layer 108 is easily peeled off from the wafer 104 (or the metal layer 105, if present).

[0062] refer to Figure 3 , a thermal interface material 302 is provided on the twin layer 108. The thermal interface material 302 is configured to fill the heat sink 202 (shown in FIG. Figure 4 ) and the wafer 104 when pressed together, improve the overall heat dissipation of the package structure 100, and effectively reduce the thermal impedance of the package structure 100, for example, by transferring the heat generated by the wafer 104 to the heat sink 202. In some embodiments, the thermal interface material 302 may include a phase change material, a metal alloy, or any other suitable thermal interface material.

[0063] In this embodiment, the thermal interface material 302 may include an indium-based alloy or a tin-based alloy. In this document, "indium-based alloy" refers to an alloy comprising at least indium, and the alloy may be formed from (1) indium and (2) at least one of bismuth, tin, or silver, such as an indium-bismuth-tin alloy, an indium-bismuth alloy, an indium-tin alloy, or an indium-silver alloy. In some embodiments, the indium-based alloy includes at least one of the following: 30 to 35 wt% bismuth, 15 to 18 wt% tin, and the balance indium, and having a melting point of 55 to 65°C; 30 to 35 wt% bismuth and the balance indium, and having a melting point of 70 to 75°C; 52 to 60 wt% bismuth, 15 to 18 wt% tin, and the balance indium, and having a melting point of 80 to 85°C; 48 to 50 wt% tin and the balance indium, and having a melting point of 110 to 120°C; 0.1 to 15 wt% silver and the balance indium, and having a melting point of 140 to 280°C; and 100 wt% indium, and having a melting point of 150 to 160°C. As used herein, "tin-based alloy" refers to an alloy comprising at least tin, which may be formed of (1) tin and (2) at least one of copper, nickel, silver, or germanium. In some embodiments, the tin-based alloy includes at least one of the following: tin, tin-silver, tin-silver-copper, or tin-silver-copper-nickel-germanium.

[0064] In some embodiments, in order to prevent the thermal interface material 302 from being pressed between the heat sink 202 and the chip 104 ( Figure 4 ), causing position slippage of the thermal interface material 302 before the thermal interface material 302 is formed, resulting in the thermal interface material 302 not completely covering the entire back surface 104B of the wafer 104, thereby reducing the heat dissipation effect. An organic adhesive (not shown) may be applied before the thermal interface material 302 is applied to prevent position slippage of the thermal interface material 302. The organic adhesive may include a fixing glue, flux, or any other suitable adhesive material.

[0065] In other embodiments, the thermal interface material 302 can be pressed against the surface of the twin layer 108 (for example, using a press head 304), with the downward arrow indicating the direction of pressure, so that the thermal interface material 302 is temporarily fixed on the twin layer 108. Specifically, the thermal interface material 302 is laid on the twin layer 108, and then pressure is applied to the surface of the thermal interface material 302 (for example, using a press head 304) to create an indentation 305. It should be noted that although the drawings only show that pressure is applied to one point on the surface of the thermal interface material 302 to create one indentation 305, the present disclosure is not limited thereto. In other embodiments, pressure can be applied to multiple points at any position on the surface of the thermal interface material 302 to create multiple indentations 305 according to actual needs. In other words, the thermal interface material 302 can be pressed against the surface of the twin layer 108 (for example, using a press head 304) at one or more points. In addition, although the figures show that the indenter 304 and the indentation 305 have circular contours, the present disclosure is not limited thereto. In other embodiments, the indenter 304 may have a contour of any shape, and the indentation 305 may have a contour corresponding to the indenter 304 .

[0066] In some embodiments, a pressure greater than 0.1 gf / mm can be applied to the surface of the thermal interface material 302 at room temperature. 2 (gf / mm 2 ) and lasts for more than 0.1 seconds (e.g., 1 second) to temporarily fix the thermal interface material 302 on the twin layer 108. As mentioned above, since the twin layer 108 has a high diffusion property, after applying pressure (e.g., using the press head 304), the twin layer 108 can be bonded and fixed to the thermal interface material 302 by room temperature diffusion bonding, so as to avoid the thermal interface material 302 being pressed between the heat sink 202 and the chip 104 ( Figure 4 ) before slipping. It should be noted that the thermal interface material 302 is temporarily fixed to the twin layer 108 by applying pressure to its surface (e.g., using a press head 304), so that conventional organic adhesives (e.g., fixing glue or flux) can be omitted. In other words, the thermal interface material 302 is in direct contact with the twin layer 108.

[0067] refer to Figure 4A heat sink 202 is provided, having a surface 202S corresponding to the wafer back surface 104B. In some embodiments, the heat sink 202 may be a heat sink metal lid and / or a heat sink fin, but the present disclosure is not limited thereto. In other embodiments, the heat sink 202 may also be a passive heat sink such as a heat pipe, or an active heat sink such as a heat fan or a water cooling loop. Any type and shape of heat sink may be selected according to actual needs. In some embodiments, the heat sink 202 may be made of a metal and / or metal alloy, such as copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), nickel-plated copper, or a combination thereof, or any suitable metal material. In other embodiments, the heat sink 202 may also be a composite material, such as an alloy, silicon carbide (SiC), aluminum nitride (AlN), graphite, the like, or a combination thereof.

[0068] The following describes this embodiment using a heat dissipation metal cover (as shown) as the heat sink 202. In this embodiment, the heat sink 202 has a groove 210, and the groove 210 is located on one side of the heat sink 202 adjacent to the chip 104 ( Figure 4 The lateral width W1 of the groove 210 is greater than the lateral width W2 of the chip 104 to ensure that the heat sink 202 and the chip 104 are pressed together ( Figure 4 ), the chip 104 can be accommodated in the groove 210.

[0069] In some embodiments, the heat sink 202 optionally includes a metal layer 205 located on the surface 202S. The metal layer 205 is configured to improve the heat dissipation effect of the package structure 100 and reduce the thermal impedance of the package structure 100, but the present disclosure is not limited thereto. In some embodiments, the metal layer 205 may include at least one of the following: gold (Au), silver (Ag), copper (Cu), titanium / silver (Ti / Ag), titanium / nickel / silver (Ti / Ni / Ag), titanium / copper (Ti / Cu), titanium / nickel / copper (Ti / Ni / Cu), nickel / silver (Ni / Ag), nickel / gold (Ni / Au), nickel / copper (Ni / Cu), rhodium (Rh), iridium (Ir), palladium (Pd), and platinum (Pt). In some embodiments, the thickness of the metal layer 205 may be 0.001 to 10 microns (e.g., 0.5 to 1.6 microns or 0.1 to 2 microns). In some embodiments, the metal layer 205 may be formed by sputtering, evaporation, electroplating, or any other suitable deposition process.

[0070] Still refer to Figure 4The heat sink 202 is pressed together with its surface 202S facing the back surface 104B of the wafer 104, so that the twin layer 108 is located on the side of the thermal interface material 302 adjacent to the wafer 104, thereby forming the package structure 100 of the present invention. Specifically, an adhesive 214 is applied to the substrate 102, and the bottom surface 202B of the heat sink 202 is bonded to the substrate 102 via the adhesive 214. A hot pressing process 306 is then performed to melt the thermal interface material 302.

[0071] In some embodiments, the hot pressing process 306 may include applying a force greater than 1 gram force per centimeter on the heat sink 202 in a process chamber at a temperature greater than 50°C (e.g., 135°C, 145°C, 155°C, or 165°C) under pressure or vacuum. 2 (gf / cm 2 ) (e.g., 55 gf / cm 2 , 900 gf / cm 2 or 3700 gf / cm 2 ) for a period of 2 seconds to 10 minutes (e.g., 5 seconds, 10 seconds, 20 seconds, or 1 minute). Within this condition range, the pores in the thermal interface material 302 can be effectively eliminated, thereby improving the heat dissipation effect and reliability of the package structure 100.

[0072] During the hot pressing process 306, the twin layer 108 provided by the present disclosure can reduce the formation of pores at the interface between the thermal interface material 302 and the wafer 104, thereby increasing the wafer-side coverage of the thermal interface material 302 on the back surface 104B of the wafer 104 (e.g., coverage greater than 90%, greater than 95%, or greater than 99%), thereby improving the heat dissipation and reliability of the package structure 100. Furthermore, the hot pressing process 306 not only melts the thermal interface material 302 but also simultaneously soft-bakes the adhesive 214 (i.e., converting the adhesive 214 into a semi-cured adhesive 214'), thereby simplifying the process steps and reducing production costs. As used herein, the term "wafer-side coverage" refers to the ratio of the coverage area of ​​the thermal interface material 302 on the back surface 104B of the wafer 104 to the surface area of ​​the back surface 104B. Generally speaking, a higher coverage indicates fewer pores in the thermal interface material 302.

[0073] Figure 5FIG2 is a schematic cross-sectional view of a package structure 100 according to some embodiments of the present disclosure. In some embodiments, the package structure 100 includes a substrate 102, a chip 104 disposed on the substrate 102, the chip 104 having a backside surface 104B facing away from the substrate 102, a heat sink 202 disposed above the substrate 102, the heat sink 202 having a surface 202S facing the chip 104, a thermal interface material 302 disposed between the chip 104 and the heat sink 202, and a twin layer 108 disposed on at least one side of the thermal interface material 302 and in direct contact with the thermal interface material 302. In this embodiment, the twin layer 108 is disposed on a side of the thermal interface material 302 adjacent to the chip 104. In other words, the twin layer 108 is disposed between the thermal interface material 302 and the chip 104.

[0074] Figures 6 to 8 Schematic cross-sectional views of package structure 200 at various stages of fabrication are provided, according to other embodiments of the present disclosure. It should be noted that processes or components identical or similar to those in the previous embodiments will retain the same reference numerals, and their details will not be repeated. In this embodiment, a twin layer 208 is present between thermal interface material 302 and heat sink 202, while a twin layer 108 is not present between wafer 104 and thermal interface material 302.

[0075] Figure 6 Continued in Figure 1 Then, a heat sink 202 is provided, which has a surface 202S corresponding to the back surface 104B, and a twin layer 208 is formed on the surface 202S of the heat sink 202 (or the metal layer 205, if present). In some embodiments, the twin layer 208 has at least 1% twin structure in its crystal structure and can have a high diffusion rate, so that it can be easily bonded to the thermal interface material 302 (shown in FIG. Figure 8 ) has a better bonding force, which can prevent the thermal interface material 302 from slipping. In addition, in the hot pressing process 306 of pressing the heat sink 202 and the chip 104 together, the generation of pores can be reduced at the interface of the thermal interface material 302 close to the heat sink 202. This part will be discussed later with Figure 8 Provide detailed explanation.

[0076] In some embodiments, the material, thickness, and formation method of the twin layer 208 can be referred to Figure 2 For the sake of brevity, the twin layer 108 is not described in detail here. In some embodiments, the twin layer 208 completely covers the entire horizontal portion of the surface 202S of the heat sink 202 to ensure that the thermal interface material 302 to be formed later directly contacts the twin layer 208 rather than the heat sink 202.

[0077] refer to Figure 7In some embodiments, a thermal interface material 302 is disposed on the twin layer 208. In this embodiment, the thermal interface material 302 can be pressed against the surface of the twin layer 208 (e.g., using a press head 304), with the upward arrow indicating the direction of pressure, so that the thermal interface material 302 is temporarily fixed on the twin layer 208. Specifically, the thermal interface material 302 is laid on the twin layer 208, and then pressure is applied to the surface of the thermal interface material 302 (e.g., using a press head 304) to create an indentation 305.

[0078] In some embodiments, a pressure greater than 0.1 gf / mm can be applied to the surface of the thermal interface material 302 at room temperature. 2 (gf / mm 2 ) and lasts for more than 0.1 seconds (e.g., 1 second) to temporarily fix the thermal interface material 302 on the twin layer 208. As mentioned above, since the twin layer 208 has a high diffusion property, after applying pressure (e.g., using the press head 304), the twin layer 208 can be bonded and fixed to the thermal interface material 302 through room temperature diffusion bonding to avoid the thermal interface material 302 being pressed between the heat sink 202 and the chip 104 ( Figure 8 ) before slipping. It should be noted that because the thermal interface material 302 is temporarily fixed to the twin layer 208 by applying pressure to its surface (e.g., using a press head 304), conventional organic adhesives (e.g., fixing glue or flux) can be omitted. In other words, the thermal interface material 302 is in direct contact with the twin layer 208.

[0079] refer to Figure 8 In some embodiments, the surface 202S of the heat sink 202 is pressed toward the back surface 104B of the wafer 104, so that the twin layer 208 is located on one side of the thermal interface material 302, thereby forming the package structure 200 of the present invention. Specifically, an adhesive 214 is applied to the substrate 102, and the bottom surface 202B of the heat sink 202 is bonded to the substrate 102 via the adhesive 214. Then, a hot pressing process 306 is performed to melt the thermal interface material 302.

[0080] During the thermal pressing process 306, the twin layer 208 provided by the present disclosure can reduce the generation of pores at the interface between the thermal interface material 302 and the heat sink 202, thereby increasing the heat sink side coverage of the thermal interface material 302 on the surface 202S of the heat sink 202 (e.g., coverage greater than 90%, greater than 95%, or greater than 99%), thereby improving the heat dissipation and reliability of the package structure 200. In this context, the chip 104 has a vertical projection area on the surface 202S of the heat sink 202, and the term "heat sink side coverage" refers to the ratio of the coverage area of ​​the thermal interface material 302 at the vertical projection area as projected by ultrasound or X-ray to the vertical projection area. Generally speaking, a higher coverage indicates fewer pores generated in the thermal interface material 302.

[0081] It should be understood that after performing the hot pressing process 306 , subsequent packaging processes may be performed according to actual needs to complete the production of the packaging structure 100 . Since this process is not relevant to the present disclosure, it will not be described in detail here.

[0082] Figure 9 2 is a schematic cross-sectional view of a package structure 200 according to some other embodiments of the present disclosure. Figure 9 The package structure 200 is similar to Figure 5 The packaging structure 100 is different in that the twin layer 208 is disposed on a side of the thermal interface material 302 adjacent to the heat sink 202. In other words, the twin layer 208 is disposed between the thermal interface material 302 and the heat sink 202, while there is no twin layer 108 between the chip 104 and the thermal interface material 302.

[0083] Figures 10 to 15 1 is a schematic cross-sectional view showing various packaging structures 300 / 400 / 500 / 600 / 700 / 800 according to yet other embodiments of the present disclosure.

[0084] In some embodiments, Figure 10 The package structure 300 is similar to Figure 9 The difference between the package structure 200 and the package structure 200 is that multiple chips 104 are disposed on the substrate 102, and a single thermal interface material 302 is disposed corresponding to the multiple chips 104. The use of a single large-area thermal interface material 302 can simplify the process and ensure that each chip 104 is covered. It should be noted that although only two chips 104 are shown in the drawings, the present disclosure is not limited to this. In other embodiments, various numbers of chips 104 can be disposed on the substrate 102 according to actual needs, such as three, four, or more than four chips 104.

[0085] In some embodiments, Figure 11 The package structure 400 is similar to Figure 10The packaging structure 300 differs in that multiple chips 104 correspond to respective thermal interface materials 302, rather than a single thermal interface material 302 corresponding to multiple chips 104. The use of multiple separate thermal interface materials 302 allows different types of thermal interface materials 302 to be configured according to the differences of each chip 104 (for example, material properties or operating temperature of the chip 104).

[0086] In some embodiments, Figure 12 The package structure 500 is similar to Figure 11 The package structure 400 is different in that the twin layer 208 includes multiple separate portions (e.g., twin layers 208a and 208b), each corresponding to a wafer 104. As shown, the twin layers 208a and 208b are spaced apart from each other at the same level and disposed on the metal layer 205. Because the twin structure in the twin layer 208 has a better thermal reactivity with the thermal interface material 302 than with ordinary metal (e.g., rough bare metal), the use of multiple separate twin layers 208a and 208b can limit the reactivity of the thermal interface material 302 with ordinary metal.

[0087] In some embodiments, Figure 12 The metal layer 205 in the package structure 500 may include multiple separated portions (not shown) spaced apart from each other at the same level, each corresponding to multiple separated portions of the twin layer 208 (e.g., twin layers 208a and 208b). This configuration can reduce the material usage of the metal layer 205, thereby reducing production costs, but the present disclosure is not limited to this. In other embodiments, the metal layer 205 may include multiple separated portions (not shown) that collectively correspond to a single twin layer 208 to simplify the process (that is, reduce process complexity).

[0088] In some embodiments, Figure 13 The package structure 600 is similar to Figure 5 The package structure 100 and Figure 9 Specifically, in addition to providing the twin layer 108 between the chip 104 and the thermal interface material 302, the twin layer 208 is also provided between the heat sink 202 and the thermal interface material 302. Compared to providing the twin layer 108 only on one side of the thermal interface material 302, providing the twin layers 108 / 208 on both sides of the thermal interface material 302 can reduce the generation of pores at the interface between the thermal interface material 302 and the chip 104 and at the interface between the thermal interface material 302 and the heat sink 202, thereby further helping to improve the heat dissipation effect and reliability of the package structure 600.

[0089] In some embodiments, Figure 14 The package structure 700 is similar to Figure 13The difference between the package structure 600 and the package structure 600 is that the heat sink 402 is a heat dissipation fin. Compared with the heat dissipation metal cover, the heat dissipation fin has a larger heat dissipation area and can more quickly dissipate the heat generated by the chip 104 during operation, achieving a better heat dissipation effect.

[0090] In some embodiments, Figure 15 The package structure 800 is similar to Figure 13 The packaging structure 600 is different in that the heat sink 202 bonded to the substrate 102 is a heat dissipation metal cover, and after the heat sink 202 is bonded to the chip 104, another heat sink 402 is provided on the heat dissipation metal cover, wherein the heat sink 402 is a heat dissipation fin. Therefore, the packaging structure 800 can further increase the heat dissipation area through the heat dissipation fins to achieve a better heat dissipation effect. Specifically, after the heat sink 202 is bonded to the chip 104, a thermal interface material 404 is provided on the surface of the heat sink 202 away from the chip 104, and then the heat sink 402 is provided on the thermal interface material 404, so that the thermal interface material 404 is fixed on the surface of the heat sink 202 away from the chip 104. The method of providing the thermal interface material 404 on the heat sink 202 can refer to Figure 3 The method of setting the thermal interface material 302 is described in detail for the sake of brevity. After the heat sink 402 is set on the thermal interface material 404, the heat pressing process 306 (shown in FIG. Figure 4 ) to melt the thermal interface material 404 to fill the contact gap between the heat sink 202 and the heat sink 402. In this way, the heat generated by the chip 104 can be transferred to the heat sink 202 through the thermal interface material 302, and then transferred to the heat sink 402 through the thermal interface material 404.

[0091] In some embodiments, the heat energy generated by the operation of the wafer 104 may cause the thermal interface material 302 and the metal layer 105 to react at their interface, causing the metal layer 105 to at least partially dissolve into the thermal interface material 302. Specifically, the outermost metal layer (e.g., gold (Au), silver (Ag), rhodium (Rh), iridium (Ir), palladium (Pd), or platinum (Pt)) in the metal layer 105 may fully or partially dissolve into the thermal interface material 302 due to its thin thickness. For example, when the thickness of the outermost metal layer is less than 0.1 micrometers, the outermost metal layer in the metal layer 105 may completely dissolve into the thermal interface material 302.

[0092] In some embodiments, the heat energy generated by the operation of the wafer 104 may cause the thermal interface material 302 and the metal layer 205 to react at the interface between the two, causing the metal layer 205 to at least partially dissolve into the thermal interface material 302. Specifically, the outermost metal layer of the metal layer 205 (e.g., gold (Au), silver (Ag), copper (Cu), rhodium (Rh), iridium (Ir), palladium (Pd), or platinum (Pt)) may fully or partially dissolve into the thermal interface material 302 due to its thin thickness. For example, when the thickness of the outermost metal layer is less than 0.1 micrometers, the outermost metal layer of the metal layer 205 will completely dissolve into the thermal interface material 302.

[0093] In some embodiments, the heat generated by the operation of the wafer 104 may cause the thermal interface material 302 to react with the twin layers 108, 208 at the interface between the two, causing the twin layers 108, 208 to at least partially dissolve into the thermal interface material 302. Specifically, the twin layers 108, 208 may be fully or partially dissolved into the thermal interface material 302 due to their thin thickness. For example, when the thickness of the twin layers 108, 208 is less than 0.1 micrometers, the gold (Au), silver (Ag), or copper (Cu) in the twin layers 108, 208 may be completely dissolved into the thermal interface material 302.

[0094] It should be noted that the metal layer 105, metal layer 205, twin layer 108, or twin layer 208 may melt into the thermal interface material 302 during operation of the wafer 104. For example, during the thermal compression process 306, a portion of the metal layer 105, metal layer 205, twin layer 108, or twin layer 208 may melt into the thermal interface material 302. After the packaging process is completed, such melting may continue to occur while the wafer 104 is in operation. However, the present disclosure is not limited to this, and any thermal process during the packaging process may cause such melting.

[0095] The following describes some experimental examples and comparative examples of the packaging structures disclosed herein to more specifically illustrate the effects that can be achieved by bonding the twin layer and the thermal interface material according to the embodiments of the present disclosure.

[0096] Comparative Example 1-2: Thermal interface material is directly placed on the metal layer

[0097] A wafer 104 having a metal layer 105 (made of Al / Ti / NiV / Au) is provided, and a thermal interface material 302 (made of 100 wt% indium) is directly placed on the metal layer 105 (that is, there is no twin layer 108 between the wafer 104 and the thermal interface material 302). Then, a pressure head 304 is used to apply pressure (applying 0.1 gf / mm) on the surface of the thermal interface material 302. 2The thermal interface material 302 is temporarily fixed on the chip 104 at two points by applying a force. After the heat sink 202 is pressed onto the chip 104, a hot pressing process 306 is performed under different conditions. The detailed conditions are shown in [Table 1].

[0098] [Table 1]

[0099]

[0100] Example 1-4: Thermal interface material is provided on the twin layer

[0101] A wafer 104 having a metal layer 105 (made of Ti / Ni) and a twin layer 108 (made of Ag with a twin structure) is provided. A thermal interface material 302 (made of 100 wt% indium) is placed on the twin layer 108. Then, a pressure head 304 is used to apply pressure (applying 0.1 gf / mm) on the surface of the thermal interface material 302. 2 The thermal interface material 302 is temporarily fixed on the chip 104 at two points by applying a force. After the heat sink 202 is pressed onto the chip 104, a hot pressing process 306 is performed under different conditions. The detailed conditions are shown in [Table 2].

[0102] [Table 2]

[0103]

[0104] [Wafer side coverage measurement]

[0105] After the hot pressing process 306 was completed, the thermal interface material 302 on the wafer 104 was scraped off using a scraper from the structures of Comparative Examples 1-2 and Experimental Examples 1-4. The coverage of the thermal interface material 302 on the wafer 104 was then calculated using an LM-X automatic image dimension measuring instrument manufactured by Keyence Corporation (Taiwan). The results are shown in Table 3.

[0106] [Table 3]

[0107] Coverage Comparative Example 1 >40％ Comparative Example 2 0％ Example 1 >99％ Example 2 >99％ Example 3 >95％ Example 4 >95％

[0108] According to Table 3, under the same hot pressing process 306 conditions, compared with directly disposing the thermal interface material 302 on the metal layer 105 (Comparative Example 1), disposing the thermal interface material 302 on the twin layer 108 can improve the coverage (Experimental Example 1).

[0109] In summary, some embodiments of the present disclosure provide some benefits. The present disclosure provides a twin layer located between the thermal interface material and the chip and / or the heat sink. During the hot pressing process of pressing the heat sink and the chip, the generation of pores can be reduced at the interface of the thermal interface material close to the chip and / or the heat sink, thereby improving the chip side coverage of the thermal interface material on the back surface of the chip and / or the heat sink side coverage on the surface of the heat sink. This is beneficial to improving the heat dissipation effect and reliability of the packaging structure. In addition, before pressing the heat sink and the chip, the thermal interface material can be temporarily fixed on the twin layer by applying pressure to avoid the thermal interface material from slipping before the heat sink and the chip are pressed, thereby omitting the known organic adhesive to reduce production costs. Furthermore, performing the hot pressing process not only melts the thermal interface material, but also simultaneously completes the soft baking of the adhesive, thereby simplifying the process steps and reducing production costs.

[0110] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art will understand that they can use the embodiments of the present invention as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: a substrate; a wafer disposed on the substrate and having a back surface away from the substrate; a heat sink disposed above the substrate, wherein the heat sink has a surface facing the chip; a thermal interface material disposed between the chip and the heat sink; and A twin layer is disposed on at least one side of the thermal interface material and is in direct contact with the thermal interface material.

2. The packaging structure according to claim 1, wherein: The twin layer is disposed between the thermal interface material and the heat sink, and the twin layer includes a plurality of separated portions spaced apart from each other on the same level.

3. The packaging structure according to claim 1, wherein: The twin layer has a crystal structure containing at least 1% of a twin structure.

4. The packaging structure according to claim 1, wherein: The twin layer has a thickness of 0.1 to 100 micrometers.

5. The packaging structure according to claim 1, wherein: The chip includes a metal layer on the back surface of the chip, and the metal layer has a thickness of 0.001 to 10 microns.

6. The packaging structure according to claim 1, wherein: The heat sink is a metal heat dissipation cover and / or heat dissipation fins.

7. The packaging structure according to claim 1, wherein: The heat sink includes a metal layer located on the surface, and the metal layer has a thickness of 0.001 to 10 microns.

8. The packaging structure according to claim 7, wherein: The metal layer includes a plurality of separated portions that are spaced apart from each other on the same level.

9. The packaging structure according to claim 1, wherein: The chip has a vertical projection area on the surface of the heat sink, and the coverage rate of the thermal interface material on the back surface of the chip or the vertical projection area is greater than 90%.

10. The packaging structure according to claim 1, wherein: The twin layer is used to at least partially blend into the thermal interface material.

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