Groove type MOSFET with improved dynamic characteristics
By optimizing the structural design of the trench MOSFET, reducing the capacitance and power between the gate and drain electrodes, the loss problem caused by overlapping voltage and current in the switching power supply is solved, and the synchronous reduction of power loss is achieved.
Patent Information
- Application Number
- CN202421778606.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-26
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-07-26
AI Technical Summary
The existing MOSFET devices are not instantly completed in the switching power supply due to the on-off and off, resulting in overlapping voltage and current, increasing losses and affecting efficiency.
By optimizing the structure of the trench MOSFET, including the design of the epitaxial layer, the trench gate unit, the P well region, the N+ well region, the P+ well region and the dielectric layer, the capacitance Cgd between the gate and the drain electrode and the capacitance Cgs between the gate and the source electrode are reduced, and the dynamic characteristics of the device are optimized.
Without affecting the static characteristics, the charging amount Qgd between the gate and the drain pole and the charging amount Qgs between the gate and the source pole are reduced, and the power loss of the device is simultaneously reduced.
Smart Images
Figure CN223297937U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the fields of electronic components, semiconductors and integrated circuits, and particularly relates to a trench MOSFET with improved dynamic characteristics. Background Art
[0002] MOSFET devices are common components in switching power supplies. When evaluating the efficiency of a switching power supply, the selection of MOSFET devices is crucial. If the selected MOSFET device is inappropriate, the heat generated in that circuit will be severe, affecting efficiency. Therefore, when considering the efficiency of a switching power supply, the loss of MOSFET devices cannot be ignored.
[0003] The fundamental reason for MOSFET switching losses is that the turn-on and turn-off of a MOSFET are not instantaneous. When the voltage is turned off, the current does not immediately drop to zero, and there is an overlap between the voltage and current. Therefore, how to effectively reduce MOSFET device losses has been a hot topic of research and discussion in this field. Utility Model Content
[0004] In order to overcome the above-mentioned shortcomings, the present invention provides a trench MOSFET with improved dynamic characteristics. By optimizing its structure, the dynamic characteristics Qgd and Qgs of the device can be optimized simultaneously, thereby simultaneously reducing the power loss of the device.
[0005] The main technical solutions adopted in this utility model are:
[0006] A trench MOSFET with improved dynamic characteristics includes a plurality of repetitive units, wherein any one of the repetitive units includes:
[0007] an epitaxial layer disposed on a substrate;
[0008] A trench gate unit, wherein the trench gate unit is located in the epitaxial layer;
[0009] A P-well region is formed on the inner surface of the epitaxial layer;
[0010] An N+ well region is formed on the surface of the epitaxial layer and is located on both sides of the trench gate unit, and the bottom of the N+ well region is in contact with the surface of the P well region;
[0011] a dielectric layer located on the upper surface of the trench gate unit and the N+ well region;
[0012] A P+ well region is formed on the inner surface of the P well region, and both ends of the P+ well region are in contact with the N+ well region. Metal contact holes are provided on the dielectric layer and the N+ well region to expose the upper surface of the P+ well region;
[0013] A metal layer is deposited on the upper surface of the dielectric layer, and the metal layer sequentially passes through the dielectric layer and the metal contact holes of the N+ well region from top to bottom to contact the upper surface of the P+ well region.
[0014] Preferably, the trench gate unit includes a bottom oxide layer, a gate oxide layer, a gate polysilicon and an oxide layer, wherein the bottom oxide layer is located at the bottom of the trench, the gate polysilicon is located on the upper surface of the bottom oxide layer, and a gate oxide layer is arranged in the gap between the gate polysilicon and the inner side wall of the trench, and the oxide layer is located on the upper surface of the gate polysilicon and is flush with the trench surface.
[0015] Preferably, both sides of the P-well region are in contact with outer sidewalls of the gate oxide layer of the trench gate unit.
[0016] Preferably, the epitaxial layer is an N-epitaxial layer, and the concentration of the N-epitaxial layer is ≥1e16cm -3 above.
[0017] Preferably, the bottom oxide layer has a thickness greater than 0.15 μm, and the bottom oxide layer has a thickness greater than that of the gate oxide layer.
[0018] Preferably, the thickness of the gate oxide layer is in the range of 0.02-0.1 um.
[0019] Preferably, the thickness of the gate polysilicon is greater than the depth difference between the P-well region and the N+-well region, and the thickness of the gate polysilicon is less than 0.4 um.
[0020] Preferably, the doping concentration of the P-well region is 5e12~5e13 cm -2 .
[0021] Preferably, the doping concentration of the N+ well region is 5e14~1e16 cm -2 .
[0022] Preferably, the doping concentration of the P+ well region is 1e14~1e15cm -2 .
[0023] Beneficial effects: The utility model provides a trench MOSFET with improved dynamic characteristics. By adjusting the structure of the trench gate unit, the capacitance Cgd between the gate and the drain and the capacitance Cgs between the gate and the source are reduced without affecting the static characteristics of the device, thereby reducing the charging quantity Qgd between the gate and the drain and the charging quantity Qgs between the gate and the source, thereby optimizing the dynamic characteristics of the device and simultaneously reducing the power loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 This is a schematic diagram of the overall structure of the utility model (the substrate is omitted).
[0025] In the figure: epitaxial layer 1, trench gate cell 2, bottom oxide layer 201, gate oxide layer 202, gate polysilicon 203, oxide layer 204, P well region 3, N+ well region 4, dielectric layer 5, P+ well region 6, metal layer 7. DETAILED DESCRIPTION
[0026] In order to help those skilled in the art better understand the technical solutions in this application, the technical solutions in the embodiments of this application are clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application. Example
[0027] like Figure 1 As shown, a trench MOSFET with improved dynamic characteristics includes a plurality of repetitive units, and any repetitive unit structure includes:
[0028] Epitaxial layer 1, disposed on a substrate;
[0029] A trench gate unit 2, the trench gate unit 2 is located in the epitaxial layer 1;
[0030] P-well region 3, formed inside epitaxial layer 1;
[0031] N+ well region 4 is formed on the surface of epitaxial layer 1 and is located on both sides of the trench gate unit 2. The bottom of the N+ well region 4 contacts the surface of the P well region 3.
[0032] A dielectric layer 5 is located on the upper surface of the trench gate unit 2 and the N+ well region 4;
[0033] A P+ well region 6 is formed on the inner surface of the P-well region 3, and both ends of the P+ well region 6 are in contact with the N+ well region 7. Metal contact holes are provided on the dielectric layer 5 and the N+ well region 4 to expose the upper surface of the P+ well region 6;
[0034] The metal layer 7 is deposited on the upper surface of the dielectric layer 5 , and the metal layer 7 sequentially passes through the dielectric layer 5 and the metal contact holes of the N+ well region 4 from top to bottom to contact the upper surface of the P+ well region 6 .
[0035] In this embodiment 1, the trench gate unit 2 includes a bottom oxide layer 201, a gate oxide layer 202, a gate polysilicon 203 and an oxide layer 204, wherein the bottom oxide layer 201 is located at the bottom of the trench, the gate polysilicon 203 is located on the upper surface of the bottom oxide layer 201, and the gate oxide layer 202 is arranged in the gap between the gate polysilicon 203 and the inner side wall of the trench, and the oxide layer 204 is located on the upper surface of the gate polysilicon 203 and is flush with the trench surface.
[0036] In this embodiment 1, the thickness of the bottom oxide layer 201 is greater than 0.15um, and the thickness of the bottom oxide layer is much greater than that of the gate oxide layer; the thickness of the left and right walls of the gate oxide layer 202 ranges from 0.02 to 0.1um; the thickness of the gate polysilicon is greater than the depth difference between the P-well region 3 and the N+ well 4, and the thickness of the gate polysilicon is less than 0.4um.
[0037] In the first embodiment, both sides of the P-well region 3 are in contact with the outer sidewalls of the gate oxide layer 202 of the trench gate cell 2 .
[0038] In this embodiment 1, the epitaxial layer 1 is an N-epitaxial layer, and the concentration of the N-epitaxial layer is ≥1e16cm -3 In the above, the doping ion type is phosphorus; the doping concentration of the P-well region is 5e12~5e13 cm -2 , the doping ion type is boron; the doping concentration of the N+ well region is 5e14~1e16 cm -2 The doping ion type is arsenic or phosphorus; the doping concentration of the P+ well region is 1e14~1e15cm -2 , and its doping ion type is boron difluoride.
[0039] In this embodiment 1, the thickness of the dielectric layer is 0.8um-1.3um.
[0040] In the present invention, the extraction and arrangement of the source, drain and gate are the same as those in the prior art, and therefore are not described in detail.
[0041] The design principle of this utility model is as follows:
[0042] The present invention first thickens the bottom oxide layer 201 in the trench before depositing the gate polysilicon 203. Figure 1As shown, the thickness of the bottom oxide layer 201 is related to the gate-drain capacitance Cgd. The thicker the bottom oxide layer 201, the smaller the capacitance Cgd, resulting in a smaller gate-drain charge Qgd. The thickness of the gate polysilicon 203 can then be controlled to be only slightly greater than the depth difference between the P-well region 3 and the N+ well region 4 on the outer side of the gate oxide layer 202. Based on the structural design of the present invention, this thickness effectively turns the device on without affecting its static characteristics. As the thickness of the gate polysilicon 203 decreases, the thickness of the oxide layer 204 located above the gate polysilicon 203 increases. The thicker the oxide layer 204, the smaller the capacitance Cgs, resulting in a smaller gate-source charge Qgs. Therefore, based on the above structural design, both the device's Qgd and Qgs can be reduced, thereby simultaneously reducing the device's power loss.
[0043] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.
Claims
1. A trench MOSFET with improved dynamic characteristics, characterized in that: Includes multiple repeating units, and any repeating unit structure includes: an epitaxial layer disposed on a substrate; A trench gate unit, wherein the trench gate unit is located in the epitaxial layer; A P-well region is formed on the inner surface of the epitaxial layer; An N+ well region is formed on the surface of the epitaxial layer and is located on both sides of the trench gate unit, and the bottom of the N+ well region is in contact with the surface of the P well region; a dielectric layer located on the upper surface of the trench gate unit and the N+ well region; A P+ well region is formed on the inner surface of the P well region, and both ends of the P+ well region are in contact with the N+ well region. Metal contact holes are provided on the dielectric layer and the N+ well region to expose the upper surface of the P+ well region; A metal layer is deposited on the upper surface of the dielectric layer, and the metal layer sequentially passes through the dielectric layer and the metal contact holes of the N+ well region from top to bottom to contact the upper surface of the P+ well region.
2. The trench MOSFET with improved dynamic characteristics according to claim 1, wherein: The trench gate unit includes a bottom oxide layer, a gate oxide layer, a gate polysilicon and an oxide layer, wherein the bottom oxide layer is located at the bottom of the trench, the gate polysilicon is located on the upper surface of the bottom oxide layer, and a gate oxide layer is arranged in the gap between the gate polysilicon and the inner side wall of the trench, and the oxide layer is located on the upper surface of the gate polysilicon and is flush with the trench surface.
3. The trench MOSFET with improved dynamic characteristics according to claim 1, wherein: Both sides of the P-well region are in contact with the outer sidewalls of the gate oxide layer of the trench gate unit.
4. The trench MOSFET with improved dynamic characteristics according to claim 1, wherein: The epitaxial layer is an N-epitaxial layer.
5. The trench MOSFET with improved dynamic characteristics according to claim 2, wherein: The thickness of the bottom oxide layer is greater than 0.15 μm, and the thickness of the bottom oxide layer is greater than that of the gate oxide layer.
6. The trench MOSFET with improved dynamic characteristics according to claim 2, wherein: The thickness of the gate oxide layer is in the range of 0.02-0.1 μm.
7. The trench MOSFET with improved dynamic characteristics according to claim 2, wherein: The thickness of the gate polysilicon is greater than the depth difference between the P-well region and the N+-well region, and the thickness of the gate polysilicon is less than 0.4 μm.