Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device. The fin field effect transistor semiconductor includes an active first set of fin structures, a source / drain region in contact with the first set of fin structures, a second set of fin structures separated from the first set of fin structures by a shallow trench isolation feature, a contact etch stop layer over the source / drain region and the second set of fin structures, and a source / drain region over the contact etch stop layer. And a gate over the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode over the gate dielectric. The second set of fin structures includes one or more inactive fin structures in contact with the contact etch stop layer and not with the source / drain region structures.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a FinFieldEffectTransistor device with extra fins. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in numerous generations of ICs, each with smaller and more complex circuits than the previous one. Throughout IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or circuit) that can be created using a process) has decreased. This process of downsizing often offers advantages by increasing production efficiency and reducing associated costs. However, this downsizing presents new challenges.

[0003] In pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including FinFETs. In FinFETs, the channel region includes a non-planar fin shape, and the gate electrode surrounds three sides of the non-planar fin shape, which allows for more complete depletion in the channel and results in smaller short channel effects and better gate control. As transistor dimensions continue to shrink, FinFETs need further improvement. Utility Model Content

[0004] One aspect of the present disclosure relates to a semiconductor device including a fin field-effect transistor, wherein the fin field-effect transistor includes: a first set of fin structures, a source / drain region, a second set of fin structures, a contact etch stop layer, and a gate. The first set of fin structures is an active fin structure. The source / drain region is in contact with the first set of fin structures. The second set of fin structures is separated from the first set of fin structures by shallow trench isolation. The contact etch stop layer is located above the source / drain region and the second set of fin structures, wherein the second set of fin structures includes one or more non-active fin structures, wherein the non-active fin structures are in contact with the contact etch stop layer but not in contact with the source / drain region. The gate is located above the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode located on the gate dielectric.

[0005] One aspect of the present disclosure relates to a semiconductor device including a fin field-effect transistor, wherein the fin field-effect transistor includes: a first set of fin structures, a source / drain region, a second set of fin structures, a contact etch stop layer, and a gate. The first set of fin structures is an active fin structure. The source / drain region contacts the first set of fin structures. The second set of fin structures is separated from the first set of fin structures by shallow trench isolation, the second set of fin structures including a first fin structure having a first height and a second fin structure having a second height, wherein the first height is different from the second height. The contact etch stop layer is located above the source / drain region and the second set of fin structures. A gate is located above the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode located on the gate dielectric.

[0006] One aspect of the present disclosure relates to a semiconductor device including a fin field-effect transistor, wherein the fin field-effect transistor includes: a first set of fin structures, a source / drain region, a second set of fin structures, a contact etch stop layer, and a gate. The first set of fin structures are active fin structures. The source / drain region contacts the first set of fin structures. The second set of fin structures is separated from the first set of fin structures by shallow trench isolation, wherein the height of the second set of fin structures outside the gate region of the fin field-effect transistor is less than or equal to the height of the first set of fin structures. The contact etch stop layer is located above the source / drain region and the second set of fin structures, wherein the second set of fin structures includes one or more inactive fin structures, wherein the inactive fin structures contact the contact etch stop layer but do not contact the source / drain region. The gate is located above the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode located on the gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practices, various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A schematic top view of an exemplary semiconductor device according to some embodiments of the present disclosure is shown;

[0009] Figure 2 According to some embodiments of the present disclosure, Figure 1 A schematic cross-sectional view of an exemplary FinFET device taken along section line AA';

[0010] Figure 3 According to some embodiments of the present disclosure, Figure 1 A schematic cross-sectional view of another exemplary FinFET device taken along section line BB';

[0011] Figure 4 According to some embodiments of the present disclosure, Figure 1 A schematic cross-sectional view of an exemplary FinFET device taken along section line CC';

[0012] Figure 5 According to some embodiments of the present disclosure, Figure 1 A schematic cross-sectional view of another exemplary FinFET device taken along section line DD';

[0013] Figure 6 A schematic top view of a semiconductor device illustrating an example of controlling the spacing of additional fin structures according to some embodiments of the present disclosure;

[0014] Figure 7 According to some embodiments of the present disclosure, Figure 6 A schematic cross-sectional view of an example FinFET device;

[0015] Figure 8 According to some embodiments of the present disclosure, Figure 6 A schematic cross-sectional view of another exemplary FinFET device;

[0016] Figures 9 to 12 According to some embodiments of the present disclosure, Figure 1 or Figure 6 A schematic cross-sectional view of an example FinFET device;

[0017] Figures 13 to 15 According to some embodiments of the present disclosure, Figure 1 or Figure 6 A schematic cross-sectional view of an example FinFET device taken outside the gate region;

[0018] 16A to 16C According to some embodiments of the present disclosure, forming Figure 14 The various stages of epitaxial features;

[0019] 17A to 17C According to some embodiments of the present disclosure, forming Figure 15 The various stages of epitaxial features;

[0020] Figure 18 A schematic top view of an example semiconductor device incorporating one or more aspects described herein is shown according to some embodiments of the present disclosure;

[0021] Figure 19 A flow chart of a method for forming a FinFET of a semiconductor device is shown according to some embodiments of the present disclosure.

[0022]

Explanation of symbols

[0023] 100:Semiconductor device

[0024] 102a: First FinFET device

[0025] 102b: Second FinFET device

[0026] 104a: first active area

[0027] 104b: Second active area

[0028] 106:Substrate

[0029] 108a: First S / D zone

[0030] 108b: Second S / D zone

[0031] 110a: The first set of fin structures

[0032] 110b: The third set of fin structures

[0033] 112a: The second set of fin structures

[0034] 112b: The fourth set of fin structures

[0035] 114: Insulation material

[0036] 116: Gate

[0037] 116a: first gate

[0038] 116b: second gate

[0039] 118: Gate dielectric

[0040] 120: Gate electrode

[0041] 122: Gate terminal dielectric characteristics

[0042] 124: Etch stop dielectric layer

[0043] 126:ILD layer

[0044] 128: Metal wire

[0045] 130: Gate contact through hole / gate contact through hole first position

[0046] 130': Gate contact through hole second position

[0047] 132:IMD layer

[0048] 134,134a,134b: Epitaxial S / D characteristics

[0049] 136:S / D contact

[0050] 138: S / D contact through hole

[0051] 140:CESL

[0052] 142:ILD layer

[0053] 148: Sidewall spacer covering layer

[0054] 200:Semiconductor devices

[0055] 202a: First FinFET device

[0056] 202b: Second FinFET device

[0057] 210a, 210b: Fin structure

[0058] 212a, 212b: Additional fin structure

[0059] 212a', 212b': Additional fin structure

[0060] 302:FinFET device

[0061] 310: The first set of fin structures

[0062] 312: First additional fin structure

[0063] 312': Second additional fin structure

[0064] 316: Gate

[0065] 320: Gate electrode

[0066] 320a: Part 1

[0067] 320b: Part 2

[0068] 320c: Part 3

[0069] 402a, 402b: FinFET devices

[0070] 410a: first set of fin structures

[0071] 410b: Second set of fin structures

[0072] 412a: first additional fin structure

[0073] 412a': second additional fin structure

[0074] 416: Gate

[0075] 420: Gate electrode

[0076] 420a: Part 1

[0077] 420b: Part 2

[0078] 502:FinFET device

[0079] 510: The first set of fin structures

[0080] 512: first additional fin structure

[0081] 512': Second additional fin structure

[0082] 516: Gate

[0083] 520: Gate electrode

[0084] 520a: Part 1

[0085] 520b: Part 2

[0086] 520c: Part 3

[0087] 602:FinFET device

[0088] 610: The first set of fin structures

[0089] 612: First additional fin structure

[0090] 612': Second and third additional fin structures

[0091] 616: Gate

[0092] 620: Gate electrode

[0093] 620a: Part 1

[0094] 620b: Part 2

[0095] 702: FinFET device

[0096] 708:S / D area

[0097] 710: The first set of fin structures

[0098] 712: Second set of additional fin structures

[0099] 734:S / D Features

[0100] 740:CESL

[0101] 802:FinFET device

[0102] 808:S / D area

[0103] 810: The first set of fin structures

[0104] 810': Depression

[0105] 812: Additional fin structure

[0106] 812': Depression

[0107] 834: Epitaxial Features

[0108] 840:CESL

[0109] 844: Epitaxial Features

[0110] 850: Spacer material

[0111] 902:FinFET device

[0112] 908:S / D area

[0113] 910: The first set of fin structures

[0114] 910': Depression

[0115] 912: Additional fin structure

[0116] 912': Depression

[0117] 934: Epitaxial Features

[0118] 940:CESL

[0119] 944: Epitaxial Characteristics

[0120] 950: Spacer material

[0121] 1002:FinFET device

[0122] 1010: Active fin structure

[0123] 1012: Additional fin structure

[0124] 1102:FinFET device

[0125] 1110: Active fin structure

[0126] 1112: Additional fin structure

[0127] 1202:FinFET device

[0128] 1210: Active fin structure

[0129] 1212: Additional fin structure

[0130] 1302:FinFET device

[0131] 1310: Active fin structure

[0132] 1312: Additional fin structure

[0133] 1402:FinFET device

[0134] 1410: Active fin structure

[0135] 1412: Additional fin structure

[0136] 1502:FinFET device

[0137] 1510: Active fin structure

[0138] 1512: Additional fin structure

[0139] 1602:FinFET device

[0140] 1610: Active fin structure

[0141] 1612: Additional fin structure

[0142] 1644: Small epitaxial features

[0143] 1702:FinFET device

[0144] 1710: Active fin structure

[0145] 1712: Additional fin structure

[0146] 1800: Method

[0147] 1802,1804,1806,1808,1810,1812,1814,1816,1818,1820,1822,1824: Box

[0148] A: Width

[0149] A-A', B-B', C-C', D-D': hatching

[0150] B': Depth

[0151] C, C': spacing

[0152] CD: critical dimension

[0153] D: Height

[0154] h0,h1,h2: height

[0155] w1,w2: width

[0156] x1: distance

[0157] x2: length

[0158] X,X' : width

[0159] Y,Y': Spacing

[0160] Z,Z' : Spacing DETAILED DESCRIPTION

[0161] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature hereinafter may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in each example. This repetition is for simplicity and clarity purposes and does not, in itself, specify the relationship between the various embodiments and / or configurations discussed.

[0162] Furthermore, for ease of description, the present disclosure may use spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0163] Although the discussion of the embodiments of the present disclosure is about FinFETs, some aspects of the embodiments of the present disclosure can be used for other processes and / or other devices, such as planar FETs, nanosheet channel FETs, horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, and other suitable devices. It will be readily understood by those skilled in the art that other modifications can be made within the scope of the present disclosure. In the case of a gate all around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multi-patterning processes) can be used to pattern the structure. In general, double patterning or multi-patterning processes combine lithography processes with self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch smaller than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0164] The foregoing broadly summarizes some aspects of the embodiments described in this disclosure. Those skilled in the art will readily appreciate that other modifications are contemplated within the scope of this disclosure. Additionally, although method embodiments may be described in a particular order, various other method embodiments can be performed in any logical order and may include fewer or more steps than those described herein. In this disclosure, reference to a source / drain region may refer to a source or drain, individually or collectively, depending on the context.

[0165] Figure 1 According to some embodiments of the present disclosure, a schematic top view of an exemplary semiconductor device 100 is shown. Figure 1 As shown, the semiconductor device 100 may include a first FinFET device 102a and a second FinFET device 102b. The first FinFET device 102a may include a first active region 104a, wherein the first active region 104a includes, for example, a first source / drain (S / D) region 108a. The second FinFET device 102b may include a second active region 104b, wherein the second active region 104b includes, for example, a second S / D region 108b. As used herein, the term "active region" refers to a device region (e.g., a region) associated with (e.g., contacting) one or more n-type or p-type doped S / D features. Figure 1The first active region 104a and the second active region 104b may be materially and / or functionally different from each other (e.g., based on material and / or functional differences between the first S / D region 108a and the second S / D region 108b, as described in more detail below).

[0166] The semiconductor device 100 may include a substrate 106. The first FinFET device 102a and the second FinFET device 102b may be fabricated on the substrate 106. The substrate 106 may be a semiconductor substrate. The substrate 106 may include a single crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), indium phosphide (InP), and / or combinations thereof. In some embodiments, the substrate 106 may be made of silicon. In some embodiments, the substrate 106 may be a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers. For example, the insulating layer may be an oxygen-containing layer.

[0167] The substrate 106 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, boron for a p-type field effect transistor (p-type FET) and phosphorus for an n-type field effect transistor (n-type FET). For example, the substrate 106 may include one or more p-type wells ("p-wells") and n-type wells ("n-wells"). The semiconductor device 100 may include a plurality of fin structures defined on (e.g., formed on) the substrate 106. In some embodiments, the fin structures may be made of Si, Ge, GaAs, SiC, GaN, C, In, other suitable materials, and / or combinations thereof. Prior to forming the fin structures, a mask structure may be formed over the substrate 106. The mask structure may include a pad layer and a hard mask. The pad layer may be an oxygen-containing layer (e.g., a SiO2 layer) or a nitrogen-containing layer (e.g., Si3N4). The mask structure may be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0168] The fin structure can be manufactured using a suitable process including a lithography and an etching process. For example, the photolithography process can include forming a photoresist layer over a mask structure, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a patterned photoresist. The patterned photoresist can then be used to protect areas of the substrate 106 and the layers formed thereon, while the etching process forms grooves through the mask structure and into the substrate 106 in the unprotected areas, leaving an extended fin structure. The trenches can be etched using dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or a combination thereof.

[0169] The first FinFET device 102a may include a first set of fin structures 110a and a second set of fin structures 112a. As used herein, the term "set" may include one or more corresponding features (e.g., one or more fin structures). The first set of fin structures 110a is an active fin structure (e.g., defined in the first active region 104a, or connected to the first source / drain region 108a). For example, at least some portions (e.g., longitudinal ends) of the fin structures 110a may be recessed to allow corresponding S / D features of the first S / D region 108a to be epitaxially grown from the fin structures 110a.

[0170] The second set of fin structures 112a may be referred to as "extra fin structures" or "auxiliary fin structures". Depending on the structure of the FinFET device, the extra fin structures may be active fin structures or passive fin structures. Figures 1 to 5 In FIG. 1 , the second set of fin structures 112 a are non-active fin structures (eg, defined outside the first active region 104 a or not connected to the first source / drain region 108 a ).

[0171] The second FinFET device 102b may include a third group of fin structures 110b and a fourth group of fin structures 112b. The third group of fin structures 110b is an active fin structure (e.g., defined in the second active region 104b, or connected to the second source / drain region 108b). For example, at least some portions of the fin structure 110b (e.g., longitudinal ends) may be recessed to allow corresponding S / D features of the first S / D region 108b to be epitaxially grown from the fin structure 110b. Similar to the second group of fin structures, the fourth group of fin structures 112b may be referred to as "additional fin structures" or "auxiliary fin structures." Depending on the structure of the FinFET device, the additional fin structure may be an active fin structure or a passive fin structure. In Figures 1 to 5In the embodiment, the fourth group of fin structures 112b are non-active fin structures (e.g., defined outside the second active region 104b or not connected to the second source / drain region 108b). For example, the fin structures 112b can be separated from the second S / D region 108b by one or more dielectric materials (e.g., CESL 140), which will be described in more detail below.

[0172] Figure 2 According to some embodiments of the present disclosure, Figure 1 A schematic cross-sectional view of an exemplary FinFET device taken along section line AA′ is shown. Figure 3 According to some embodiments of the present disclosure, Figure 1 A schematic cross-sectional view of another exemplary FinFET device taken along section line BB′ is shown.

[0173] like Figures 2 to 3 As shown, the semiconductor device 100 may include a shallow trench isolation (STI) feature (e.g., insulating material 114) surrounding the lower portion of the fin structures 110a, 112a, 110b, 112b. For example, the insulating material 114 may be formed in a trench between the fin structures 110a, 112a, 110b, 112b. In some embodiments, the fin structures 110a, 110b are partially embedded in the insulating material 114. In some embodiments, depending on the function of the fin structures 112a, 112b, the fin structures 112a, 112b may be partially or completely embedded in the insulating material 114. In some embodiments, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, may be performed to remove a portion of the insulating material 114 and / or expose the fin structure (e.g., the top surface of the fin structure). The insulating material 114 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 114 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0174] The first FinFET device 102a may include a first gate 116a. The first gate 116a spans the first set of fin structures 110a and the second set of fin structures 112a. The second FinFET device 102b may include a second gate 116b. The second gate 116b spans the third set of fin structures 110b and the fourth set of fin structures 112b. The portion of the fin structure located between the two source / drain regions 108a, 108b or within the gate region (e.g., the portion overlapping the first gate 116a or the second gate 116b) may be defined as a "channel." In some embodiments, the first gate 116a and the second gate 116b may be combined together as a single, integral gate structure. The gate 116 (e.g., the first gate 116a and the second gate 116b) may include a gate dielectric 118 and a gate electrode 120. The gate dielectric 118 may be located between the fin structure (e.g., the top and side surfaces of the fin structure) and the gate electrode 120 (e.g., at the interface therebetween). In some embodiments, the gate dielectric 118 can be made of Si, O, Hf, La, Zr, Zn, N, other suitable materials, and / or combinations thereof. In some embodiments, the gate dielectric 118 can include an interfacial layer and a high-k dielectric layer. For example, the interfacial layer can include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. As used and described herein, the high-k dielectric layer includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermal silicon oxide, approximately 3.9). For example, the high-k dielectric layer may include hafnium oxide, titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, europium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), other suitable materials and / or combinations thereof.

[0175] In some embodiments, the gate electrode 120 may include a single layer or a multilayer structure including a metal layer having a selected work function to enhance device performance (work function metal layer), a liner, a wetting layer, an adhesion layer, a metal alloy, a metal silicide, and / or a combination thereof. For example, the gate electrode 120 may include Ag, Au, Rh, Mo, Zn, Nb, Ta, Zr, aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), copper (Cu), a metal alloy (e.g., titanium nitride (TiN), brass, phosphor bronze, cast steel, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), tantalum carbide (TaC), or tantalum silicon nitride (TaSiN)), other refractory metals, other suitable metal materials, and / or a combination thereof.

[0176] Indeed, certain aspects of the material of gate electrode 120 (which may also be referred to herein as a "work function metal" or "WFM") are related to device performance. For example, the material composition and / or thickness of the WFM can be used to adjust (e.g., optimize) or otherwise tune device performance. However, device scaling (to smaller dimensions) can result in gate volume limitations, making the WFM more difficult to fill and device threshold voltage (Vt) adjustment more difficult to perform, thereby limiting the types of devices that can be used. Embodiments of the present disclosure address one or more of these issues, for example, by controlling one or more additional fin structures, as described in more detail below.

[0177] Common Reference Figures 1 to 3, the gate 116 may extend longitudinally in a direction perpendicular to the fin structure. The gate 116 may terminate at one or more gate end dielectric features 122 (e.g., a dielectric fin structure). For example, the one or more gate end dielectric features 122 may be located at a first longitudinal end and a second longitudinal end opposite the gate 116. In some embodiments, the one or more gate end dielectric features 122 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, porous oxide, and / or combinations thereof. In some embodiments, an optional etch stop dielectric layer 124 may be formed over the gate 116. For example, the etch stop dielectric layer 124 may be a capping layer formed over the top surface of the gate 116 and over the one or more gate end dielectric features 122. In some embodiments, the etch stop dielectric layer 124 may be formed of a low-k dielectric material (e.g., tetraethylorthosilicate (TEOS) oxide, undoped silicate glass), or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)), and / or combinations thereof.

[0178] In some embodiments, an interlayer dielectric (ILD) layer 126 may be formed over the etch stop dielectric layer 124. In some embodiments, the ILD layer 126 may be formed of the same or similar material composition as the etch stop dielectric layer 124.

[0179] In some embodiments, one or more metal lines 128 of a conductive layer may be formed over the ILD layer 126. For example, the one or more metal lines 128 may extend longitudinally in a direction perpendicular to the gate 116 and / or parallel to the fin structure. In some embodiments, a gate contact via 130 may extend from the metal line 128 of the conductive layer to the gate 116. For example, the gate contact via 130 may extend vertically in a direction perpendicular to the gate 116 and the fin structure. In some embodiments, the one or more metal lines 128 and the gate contact via 130 may be formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), copper (Cu), aluminum (Al), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), and / or combinations thereof.

[0180] In some embodiments, an intermetal dielectric (IMD) layer 132 may be formed over the conductive layer (e.g., around one or more metal lines 128). In some embodiments, the IMD layer 132 may be formed of the same or similar material composition as the etch stop dielectric layer 124 and / or the ILD layer 126.

[0181] Figure 4 According to some embodiments of the present disclosure, Figure 1 Schematic cross-sectional view of an exemplary FinFET device taken along section line CC′. Figure 5 According to some embodiments of the present disclosure, Figure 1 A schematic cross-sectional view of another exemplary FinFET device taken along section line DD′ is shown.

[0182] like Figure 4 As shown, outside the gate region, the first FinFET device 102a may include a first S / D region 108a. For example, the first S / D region 108a may include an n-type epitaxial S / D feature 134a (eg, in contact with the first set of fin structures 110a). Figure 5 As shown, outside the gate region, the second FinFET device 102b can include a second S / D region 108b. For example, the second S / D region 108b can include a p-type epitaxial S / D feature 134b (e.g., in contact with the third set of fin structures 110b). In some embodiments, the epitaxial S / D features 134a, 134b (collectively referred to as 134) described herein can be made of SiC, SiP, SiGe, other suitable materials such as metal features, and / or combinations thereof. S / D contacts 136 can be formed above the S / D regions 108a, 108b (collectively referred to as 108) and / or above the epitaxial S / D features 134. For example, the S / D contacts 136 can be coupled to (e.g., in contact with) the epitaxial S / D features 134. In some embodiments, the S / D contacts can be made of W, Co, Al, Cu, Ag, Au, other suitable materials, and / or combinations thereof. The S / D contact vias 138 may be formed in the ILD layer 126 and extend from the metal lines 128 of the IMD layer 132 to the S / D contacts 136 .

[0183] Outside the gate region, a sidewall spacer capping layer 148 may be formed over the second set of fin structures 112a. The sidewall spacer capping layer 148 may help control epitaxial growth. For example, the sidewall spacer capping layer 148 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, porous oxide, and / or combinations thereof. Outside the gate region, a CESL 140 is formed over the S / D devices 134a, 134b. In some embodiments, the CESL 140 may be formed over additional fin structures (e.g., the second set of fin structures 112a and the fourth set of fin structures 112b). In some embodiments, the CESL 140 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, porous oxide, and / or combinations thereof. The CESL 140 may be located between the insulating material 114 of the STI features and another ILD layer 142 deposited over the CESL 140.

[0184] Figures 1 to 5 The additional fin structures 112a, 112b provide certain benefits related to device performance. For example, compared to traditional technologies that are limited by the material and thickness of the WFM, the additional fins can adjust the work function of the gate electrode by changing the spatial composition of the WFM. In addition, the spacing, height, number and shape of the additional fins affect the WFM filling, thereby further achieving the adjustment of the threshold voltage and / or leakage current. The additional fins can provide design density, reduce contact resistance, reduce the loading effect during fin formation, can adjust the electrode volume (for example, based on the fin height in the gate area), help contact positioning, reduce contact resistance, and assist in adjusting the shape and / or volume of the epitaxial S / D (for example, based on the fin height outside the gate area).

[0185] Figure 6 A schematic top view of a semiconductor device 200 is shown illustrating an example of controlling the spacing of additional fin structures according to some embodiments of the present disclosure. The semiconductor device 200 is similar to the semiconductor device 100 except that the additional fins are varied in height, position, shape, number, and / or distance. For clarity, Figure 6 Certain aspects of the semiconductor device are omitted (e.g., S / D regions, metal lines, contact vias, and S / D contacts). In some embodiments, the spacing may depend, at least in part, on the fin width, fin shape, and / or fin volume. Thus, Figure 6Two different examples are shown in FIG. In the first FinFET device 202 a, the width X of the additional fin structure 212 a can be in the range of about 8 nanometers (nm) or less, such as about 6 nm to about 8 nm. The minimum spacing Y between the additional fin structure 212 a and the adjacent fin structure 210 a can be in the range of about 2X to about 3X (e.g., about 20 nm to about 22 nm). The maximum spacing Z between the additional fin structure 212 a′ and the adjacent fin structure 210 a can be in the range of about 5X to about 7X (e.g., about 32 nm to about 42 nm).

[0186] In the second FinFET device 202b, a width X' of the additional fin structure 212b (e.g., measured at the top surface of the fin structure 212b) can be in a range of about 0.5X to about 1X (e.g., about 3 nm to about 8 nm, such as about 3 nm to about 6 nm or about 4 nm to about 8 nm). A minimum spacing Y' between the additional fin structure 212b and the adjacent fin structure 210b can be in a range of about 4X' to about 6X' (e.g., about 20 nm to about 22 nm). A maximum spacing Z' between the additional fin structure 212b' and the adjacent fin structure 210b can be in a range of about 10X' to about 14X' (e.g., about 32 nm to about 42 nm).

[0187] Figure 7 According to some embodiments of the present disclosure, Figure 6 For clarity, Figure 7 Certain aspects of FinFET devices (such as dielectric layers, conductive layers, contact vias, and IMD layers) are omitted. Figure 7 As shown, the additional fin structure 212a of the first FinFET device 202a can be a non-tapered shape (e.g., a rectangular cross-section). For example, the width X of the fin structure 212a can be constant. The volume of the non-tapered fin structure 212a is greater than the volume of a similar tapered fin structure, as will be described in more detail below.

[0188] like Figure 7 As shown, there may be a height difference between the active fin structure 210a and the one or more additional fin structures 212a. For example, the height h0 of the one or more active fin structures 210a may be greater than the individual heights h1 and h2 of the additional fin structures 212a. In some embodiments, the ratio of h1 / h0 or h2 / h0 may be in the range of 0 to 1, such as about 0.2 to about 0.9, about 0.4 to about 0.6, or about 0.5. Figure 7As shown, there may be height differences between one or more additional fin structures 212a. For example, a first height h1 of a first additional fin structure 212a (e.g., on the left side of the fin structure 210a) may be less than a second height h2 of a second additional fin structure 212a (e.g., on the right side of the fin structure 210a). In some embodiments, the ratio h1 / h2 is in a range of 0 to 1, such as approximately 0.2 to approximately 0.95, approximately 0.4 to approximately 0.6, or approximately 0.5. In some other embodiments, the individual heights of the additional fin structures 212a may be equal.

[0189] Figure 8 According to some embodiments of the present disclosure, Figure 6 For clarity, a cross-sectional view of another exemplary FinFET device is shown. Figure 8 Certain aspects of FinFET devices (such as dielectric layers, conductive layers, contact vias, and IMD layers) are omitted. Figure 8 As shown, the additional fin structure 212b of the second FinFET device 202b can be tapered (e.g., decreasing in size toward the top surface). For example, the width X' of the fin structure 212b can be narrowest at the top surface. For example, the tapered width (ratio of X' to X) can be in the range of about 0.5X to about 1X. The volume of the tapered fin structure 212b is less than the volume of a similar non-tapered fin structure (e.g., having a rectangular cross-section). Figure 8 As shown, the heights of the additional fin structures 212b are equal. In some other embodiments, the individual heights of the additional fin structures 212b may be different.

[0190] As described above, differences in fin pitch, fin width, fin shape, fin height, and fin volume can independently or collectively provide many different knobs for adjusting device performance. The following provides examples illustrating controlling device performance based on the various control knobs identified herein.

[0191] Figures 9 to 12 According to some embodiments of the present disclosure, Figure 1 or Figure 6 Schematic cross-section of an exemplary FinFET device. FinFET devices 302, 402a, 402b, 502, 602 are similar to FinFET devices 102a, 102b, 202a, 202b, except for changes in gate electrode material composition and changes in the height, position, shape, number and / or distance of additional fins. For clarity, Figures 9 to 12Certain aspects of the FinFET device (e.g., dielectric layers, conductive layers, contact vias, and IMD layers) are omitted from the present disclosure. In some embodiments, the FinFET device can be patterned to deposit WFMs of varying compositions in the gate electrode 120, as will be described in greater detail below. As used herein, the terms "pattern," "patterned," and "patterning" can refer to a multi-step process that includes, for example, forming a mask over the upper surface of a corresponding layer, patterning the mask using lithography to remove portions of the mask and expose portions of the upper surface of the corresponding layer, etching through the patterned mask to remove portions of the corresponding layer, and / or removing the patterned mask using a suitable process (e.g., ashing or dissolving with a solvent, etc.).

[0192] like Figure 9 As shown, FinFET device 302 includes a first set of fin structures 310, a second set of additional fin structures 312 / 312', and a gate 316 located above the first set of fin structures and the second set of fin structures. Gate 316 may include a gate electrode 320 having multiple (e.g., three) different material compositions. For example, gate electrode 320 may include a first portion 320a (e.g., surrounding the first set of fin structures 310), a second portion 320b (e.g., surrounding the first additional fin structure 312), and a third portion 320c (e.g., surrounding the second additional fin structure 312'). In some embodiments, the material composition of one or more of the first portion 320a, the second portion 320b, or the third portion 320c is different from the material composition of one or more other portions of gate electrode 320. For example, all material compositions may be different from each other. In some embodiments, the material composition of the second portion 320b and the third portion 320c may be the same as each other and may be different from the material composition of the first portion 320a. For example, all material compositions may be different from each other. In some embodiments, the material composition of the second portion 320b and the third portion 320c can be the same as each other and can be different from the material composition of the first portion 320a. In some embodiments, the material composition can include p-type dopants, n-type dopants, low resistance, high resistance, different work functions, etc. In some embodiments, the material composition and physical state of the additional fin structure 312 / 312' can be implemented independently or in combination to adjust device performance. For example, Figure 9As shown, the height of the additional fin structure 312 located in the second portion 320b of the gate electrode 320 is less than the height of the additional fin structure 312' located in the third portion 320c. This height difference and the difference in material composition between the second portion 320b and the third portion 320c can independently or collectively provide improved modulation of device performance (e.g., a synergistic effect). In some other embodiments, the heights of the additional fin structures 312 / 312' can be equal.

[0193] like Figure 10 As shown, another FinFET device 402a / b includes a first set of fin structures 410a of the first FinFET device 402a, a second set of fin structures 410b of the second FinFET device 402b, a third set of additional fin structures 412a / a', and a gate 416 located above the first, second, and third sets of fin structures. The gate 416 may include a gate electrode 420 having multiple (e.g., two) different material compositions. For example, the gate electrode 420 may include a first portion 420a (e.g., surrounding the first set of fin structures 410a and the second set of fin structures 410b) and a second portion 420b (e.g., surrounding the first additional fin structure 412a and the second additional fin structure 412a'). In some embodiments, the first portion 420a and the second portion 420b may be alternating. In some embodiments, the first portion 420a and the second portion 420b may have different material compositions from each other. In some other embodiments, the material compositions may be the same. In some embodiments, the material composition may include p-type dopants, n-type dopants, low resistance, high resistance, different work functions, and the like.

[0194] like Figure 10 As shown, the second additional fin structure 412a' is adjacent to (e.g., between) the fin structures of both the first FinFET device 402a and the second FinFET device 402b. Thus, the second additional fin structure 412a' can be referred to as an "inner" fin, while the first additional fin structure 412a can be referred to as an "outer" fin. The proximity of the internal fin to the active fin structure on more than one side (e.g., two opposing sides) can provide improved regulation of device performance. Figure 10 As shown, the heights of the additional fin structures 412a / a' are equal. In some other embodiments, the individual heights of the additional fin structures 412a / a' may be different.

[0195] like Figure 11As shown, FinFET device 502 includes a first set of fin structures 510, a second set of additional fin structures (first additional fin structures 512 / second additional fin structures 512'), and a gate 516 located above the first set of fin structures and the second set of fin structures. Gate 516 may include a gate electrode 520 having multiple (e.g., three) different material compositions. For example, gate electrode 520 may include a first portion 520a (e.g., surrounding the first set of fin structures 510), a second portion 520b (e.g., surrounding the first additional fin structures 512), and a third portion 520c (e.g., surrounding the second additional fin structures 512'). In some embodiments, one or more of the first portion 520a, the second portion 520b, or the third portion 520c may have a different material composition than one or more other portions of gate electrode 520. For example, all material compositions may be different from each other. In some embodiments, the material composition of the second portion 520b and the third portion 520c may be the same as each other and may be different from the material composition of the first portion 520a. In some embodiments, the material composition may include p-type dopants, n-type dopants, low resistance, high resistance, different work functions, and the like.

[0196] In some embodiments, the material composition and physical properties of the additional fin structures 512 / 512' can be implemented independently or in combination to adjust device performance. Figure 11 As shown, the additional fin structure 512 located in the second portion 520b of the gate electrode 520 is non-tapered, while the additional fin structure 512' located in the third portion 520c is tapered. The volume of the tapered additional fin structure 512' is smaller than the volume of the similar non-tapered fin structure 512. Figure 11 As shown, the additional fin structures 512 / 512' are of equal height. In some other embodiments, the additional fin structures 512 / 512' may have different heights. Differences in shape / volume or material composition between the second portion 520b and the third portion 520c may independently or collectively provide improved modulation of device performance (e.g., a synergistic effect).

[0197] like Figure 12As shown, the FinFET device 602 includes a first set of fin structures 610, a second set of additional fin structures (first additional fin structure 612 / second and third additional fin structures 612'), and a gate 616 located above the first set of fin structures and the second set of fin structures. The gate 616 may include a gate electrode 620 having multiple (e.g., two) different material compositions. For example, the gate electrode 620 may include a first portion 620a (e.g., surrounding the first set of fin structures 610 and the first additional fin structure 612) and a second portion 620b (e.g., surrounding the second and third additional fin structures 612'). In some embodiments, the first portion 620a and the second portion 620b may have different material compositions from each other. In some other embodiments, the material compositions may be the same as each other. In some embodiments, the material compositions may include p-type dopants, n-type dopants, low resistance, high resistance, different work functions, etc.

[0198] In some embodiments, the material composition and physical state of the additional fin structures 612 / 612' can be implemented independently or in combination to adjust device performance. Figure 12 As shown, the additional fin structure 612 does not extend into the gate 616 (e.g., terminates below the gate dielectric 118). In some embodiments, the height of the additional fin structure 612 can be formed so that the top surface of the additional fin structure 612 is located below the gate 616. The FinFET device 602 can include the gate 616 without the additional fin structure 612 to adjust device performance.

[0199] like Figure 12 As shown, more than one (eg, two) additional fin structures 612' are located on the same side (eg, a first side and an opposite second side) of the first set of fin structures 610. Figure 12 As shown, the additional fin structures 612' are of equal height. In some other embodiments, the heights of the additional fin structures 612' can vary. The differences in number and / or distance, along with the differences in material composition between the first portion 620a and the second portion 620b, can independently or collectively provide improved modulation of device performance (e.g., a synergistic effect).

[0200] Figures 13 to 15 According to some embodiments of the present disclosure, Figure 1 or Figure 6 Schematic cross-sectional view of an exemplary FinFET device taken outside the gate region. FinFET devices 702, 802, 902 are similar to FinFET devices 102a, 102b except for variations in aspects such as the height of the additional fins, the presence of sidewall spacer capping layers, and / or the presence of epitaxial S / D features. For clarity, Figures 13 to 15Certain aspects of FinFET devices (eg, dielectric layers, conductive layers, contact vias, and IMD layers) are omitted.

[0201] like Figure 13 As shown, FinFET device 702 includes an S / D region 708, a first set of fin structures 710, and a second set of additional fin structures 712 outside the gate region. S / D region 708 may include epitaxial S / D features 734 (e.g., p-type or n-type). Epitaxial S / D features 734 may be formed above (e.g., in contact with) the corresponding fin structures 710 of the first set. FinFET device 702 may include a CESL 740 located above the additional fin structures 712 and surrounding the S / D features 734.

[0202] like Figure 13 As shown, the additional fin structure 712 does not extend above the fin structure 710 (e.g., terminates below the ILD layer 142). In some embodiments, the additional fin structure 712 can be formed or cut to a height equal to or less than the height of the fin structure 710, such that the top surface of the additional fin structure 712 is located at or below the top surface of the fin structure 710. In some embodiments, the CESL 740 can be flat (e.g., located in a plane extending above the top surface of the additional fin structure 712). Device performance can be adjusted based on the FinFET device 702, wherein the FinFET device 702 includes the cut additional fin structure 712.

[0203] like Figure 14 As shown, FinFET device 802 includes an S / D region 808, a first set of fin structures 810, and a second set of additional fin structures 812 outside the gate region. S / D region 808 may include epitaxial S / D features 834 (e.g., p-type or n-type). Epitaxial S / D features 834 may be formed above (e.g., in contact with) the corresponding first set of fin structures 810. FinFET device 802 may include CESL 840 surrounding S / D features 834. FinFET device 802 may include epitaxial features 844. Epitaxial features 844 may be formed above (e.g., in contact with) the corresponding second set of additional fin structures 812. Epitaxial features 844 may be separate from epitaxial S / D features 834 or not merged with epitaxial S / D features 834 (e.g., with ILD layer 142 therebetween). In some embodiments, increasing the spacing between the additional fin structure 812 and the adjacent fin structure 810 can further prevent the additional fin structure 812 from merging with the adjacent fin structure 810. In some embodiments, the epitaxial feature 844 can be formed using the same process (e.g., simultaneously) as the epitaxial S / D feature 834. The CESL 840 can surround the epitaxial feature 844.

[0204] like Figure 14 As shown, the additional fin structure 812 does not extend above the fin structure 810 (e.g., terminates below the ILD layer 142). In some embodiments, the additional fin structure 812 can be formed or cut to a height equal to or less than the height of the fin structure 810, such that the top surface of the additional fin structure 812 is at or below the top surface of the fin structure 810. In some embodiments, the additional fin structure 812 can be lower than the fin structure 810, and the depth of the epitaxial feature 844 can extend below the top surface of the insulating material 114 of the STI feature. Device performance can be adjusted based on the FinFET device 802 including the epitaxial feature 844.

[0205] like Figure 15 As shown, outside the gate region, the FinFET device 902 includes an S / D region 908, a first set of fin structures 910, and a second set of additional fin structures 912. The S / D region 908 may include epitaxial S / D features 934 (e.g., p-type or n-type). The epitaxial S / D features 934 may be formed over (e.g., in contact with) the corresponding first set of fin structures 910. The FinFET device 902 may include a CESL 940 surrounding the S / D devices 934. The FinFET device 902 may include epitaxial features 944. The epitaxial features 944 may be similar to Figure 14 Epitaxial features 844 are shown. Epitaxial features 944 can be formed over (e.g., in contact with) corresponding second set of additional fin structures 912. Epitaxial features 944 can be merged with epitaxial S / D features 934. In some embodiments, epitaxial features 944 can be formed using the same process as (e.g., simultaneously with) epitaxial S / D features 934. CESL 940 can surround epitaxial features 944.

[0206] like Figure 15 As shown, the additional fin structure 912 does not extend above the fin structure 910 (e.g., terminates below the ILD layer 142). In some embodiments, the additional fin structure 912 can be formed or cut to a height equal to or less than the height of the fin structure 910, such that the top surface of the additional fin structure 912 is at or below the top surface of the fin structure 910. In some embodiments, the additional fin structure 912 can be lower than the fin structure 910, and the depth of the epitaxial feature 944 can extend below the top surface of the insulating material 114 of the STI feature. Device performance can be adjusted based on the FinFET device 902 including the epitaxial feature 944.

[0207] Compare Figure 14 and Figure 15, the additional fin structure 912 is shorter than the additional fin structure 812. A shorter fin structure and / or a greater depth may cause the epitaxial features 944 to be larger (e.g., wider), which may facilitate merging and provide a larger landing area for the S / D contacts 136. Figure 14 Due to the larger size of epitaxial feature 944 and / or the larger landing area of ​​S / D contact 136 compared to epitaxial feature 844, for example, device resistance can be reduced (and correspondingly higher current), which can be particularly beneficial for device performance.

[0208] 16A to 16C According to some embodiments of the present disclosure, forming Figure 14 The various stages of epitaxial features 834 / 844. Figure 16A As shown, fin structures 810 / 812 are formed and spacer material 850 is deposited over the fin structures 810 / 812. Some dimensions of the fin structures 810 / 812 are shown, including fin width A, fin-to-fin spacing C, and fin height D. Figure 17A Describe these dimensions in more detail. Figure 16B As shown, an etch-back process is performed to remove a portion of the fin structure 810 / 812 and open the corresponding recess 810' / 812' to define the growth pattern of the epitaxial features 834 / 844. Figure 16C As shown, epitaxial features 834 / 844 are formed and CESL 840 is deposited over the epitaxial features 834 / 844 .

[0209] 17A to 17C According to some embodiments of the present disclosure, forming Figure 15 The various stages of epitaxial features 934 / 944. Figure 17A As shown, fin structures 910 / 912 are formed and spacer material 950 is deposited over the fin structures 910 / 912. In some embodiments, the fin-to-fin spacing C' of the fin structures 910 / 912 can be less than the fin-to-fin spacing C' of the fin structures 810 / 812. For example, the fin-to-fin spacing C' can be in the range of 2*A to 0.85*C. In some embodiments, the depth B' of the fin structures 910 / 912 can be greater than the depth of the corresponding fin structures 810 / 812. For example, the depth B' can be greater than or equal to 0.4*D. Figure 17B As shown, an etch-back process is performed to remove portions of the fin structures 910 / 912 and to open corresponding recesses 910' / 912' to define the growth pattern of the epitaxial features 934 / 944. Figure 17C As shown, epitaxial features 934 / 944 are formed and CESL 940 is deposited over the epitaxial features 934 / 944 .

[0210] Compare 16A to 16C and 17A to 17C , the depth of recess 912' is greater than the depth of recess 812', the critical dimension (CD) of the top surface of the resulting fin structure 912 adjacent to recess 912' is wider than the top surface of the resulting fin structure 812 adjacent to recess 812', and the epitaxial feature 944 is larger than the epitaxial feature 844, as described above with reference to Figure 14 and Figure 15 As stated.

[0211] Figure 18 According to some embodiments of the present disclosure, a schematic top view of an exemplary semiconductor device incorporating one or more aspects described herein is shown. For clarity, Figure 18 Some aspects of the semiconductor device (eg, metal lines) are omitted.

[0212] Device 1 shows a FinFET device 1002 having an additional fin structure 1012 of a first width w1. Figure 18 As with other devices shown, the additional fin structures may be active fin structures and may provide transistor functionality. Device 1 may include one or more active fin structures 1010 (e.g., 2-3 active fin structures located within the active region defined by box 1010). In some embodiments, the additional fin structures 1012 may have different heights (e.g., high and low fin heights). For example, device 1 may incorporate FinFET device 202a ( Figure 7 ) and / or FinFET device 302 ( Figure 9 ) one or more aspects. Device 2 shows a FinFET device 1102 having a small (e.g., narrower or tapered) additional fin structure 1112, for example, having a second width w2 that is smaller than the first width wl of device 1. Device 2 may include one or more active fin structures 1110 (e.g., 2-3 active fin structures located within the active area defined by box 1110). In some embodiments, device 2 may incorporate a FinFET device 202b ( Figure 8 ) and / or FinFET device 502 Figure 11 ). Device 3 shows a FinFET device 1202 with one or more additional fin structures 1212, where the additional fin structures 1212 are internal fin structures (e.g., 1-2 internal fin structures located within the active area defined by box 1212). For example, one or more internal fin structures can be located between active fin structures 1210. In some embodiments, device 3 can incorporate FinFET devices 402a / b ( Figure 10). Device 4 shows a FinFET device 1302 with one or more additional fin structures 1312, where the additional fin structures 1312 are external fin structures (e.g., two sets of external fin structures are shown). The one or more external fin structures can be (e.g., surrounding) the exterior of the active fin structure 1310. Each external fin structure can include one or more external fin structures (e.g., 1-2 external fin structures located within the active area defined by the corresponding box 1312). In some embodiments, device 4 can incorporate a FinFET device 602 ( Figure 12 ). Device 5 shows a FinFET device 1402 having one or more additional fin structures 1412 alternating with active fin structures 1410. For example, the additional fin structures 1412 may include internal fin structures and external fin structures (e.g., one set of internal fin structures and another set of external fin structures are shown). Each internal and external fin structure may include one or more fin structures (e.g., 1-2 fin structures located within the active area defined by the corresponding box 1412).

[0213] Device 6 shows a FinFET device 1502 having an additional fin structure 1512 that is shorter in length (e.g., extending only through the gate region (e.g., channel) and / or discontinuously through the S / D region). For example, the short fin structure can be spaced apart from the S / D contact 136 by a distance X1. When the gate length is X2, the ratio of X1 / X2 is in the range of 0.03 to 1.5. Device 6 may include one or more short fin structures (e.g., two or more short fin structures, such as two short fin structures). In some embodiments, portions of the short fin structures outside the gate region may be cut. Device 6 may include one or more active fin structures 1510 (e.g., 2-3 active fin structures located within the active region defined by box 1510). In some embodiments, the epitaxial structure of device 6 may be a non-merged epitaxial structure. In some embodiments, device 6 may be incorporated into FinFET device 702 ( Figure 13 )

[0214] Device 7 shows a FinFET device 1602 with an additional fin structure 1612 that includes a small epitaxial feature 1644 (e.g., a dummy feature) outside the gate region. Device 7 may include one or more small epitaxial features 1644 (e.g., only one small epitaxial feature is shown for each additional fin structure). Device 7 may include one or more active fin structures 1610 (e.g., 1-2 active fin structures located within the active region defined by box 1610). In some embodiments, the small epitaxial structures 1644 of device 7 may be non-merged epitaxial features. In some embodiments, device 7 may be incorporated into FinFET device 802 ( Figure 14 )

[0215] Device 8 shows a FinFET device 1702 with an additional fin structure 1712 that is covered (e.g., with a spacer material) outside of the gate region. Device 8 may include one or more active fin structures 1710 (e.g., 2-3 active fin structures located within the active region defined by box 1710). In some embodiments, the epitaxial structures of device 8 may be non-merged epitaxial features. In some embodiments, device 8 may be incorporated into FinFET devices 102a / b ( Figure 4 or Figure 5 )

[0216] Figure 18 The example semiconductor device of FIG. 1 shows two different selected locations for a gate contact via. For example, the gate contact via can be positioned between a first location 130 that does not overlap with the additional fin structure and a second location 130′ (shown in dashed lines) that overlaps with the additional fin structure. The location of the gate contact via provides additional adjustment of the work function and / or Vt.

[0217] Figure 19 According to some embodiments of the present disclosure, a flowchart of a method 1800 for forming a FinFET of a semiconductor device is shown. The method 1800 may be understood as involving the methods described herein and / or Figures 1 to 18any embodiment or combination of embodiments shown, but not limited thereto. At box 1802, method 1800 may include forming a first set of semiconductor fin structures and a second set of semiconductor fin structures on a substrate. For example, the semiconductor fin structures may include an active first set of fin structures and an additional second set of fin structures. As described above, the second set of fin structures may be active or passive. At box 1804, method 1800 may include trimming (reshaping) the second set of fin structures according to a configuration for adjusting device performance. For example, the second set of fin structures is trimmed relative to the first set of fin structures. In some embodiments, method 1800 may include selectively trimming the second set of fin structures to improve device performance. For example, selectively trimming (e.g., using a patterning process) the second group of fin structures may include one or more of the following: causing the second group of fin structures to have a different height than the first group of fin structures, causing the heights of the first and second fin structures of the second group of fin structures to be different from each other; causing one or more fin structures in the second group to be tapered; causing at least one internal fin structure of the second group to be located between the first active fin structure of the first group and the second active fin structure of the other group of active fin structures; or causing at least two fin structures in the second group of fin structures to be located on a first side of the first and second sides of the first group of fin structures.

[0218] At block 1806, method 1800 may include filling one or more dielectric materials between the fin structures. For example, the one or more dielectric materials may include shallow trench isolation (STI) features and one or more other dielectric layers. For example, the one or more dielectric materials may be deposited over and / or around the first set of fin structures and the second set of fin structures. At block 1808, method 1800 may include forming a sacrificial (dummy) gate structure over the fin structure. For example, the sacrificial gate may include a sacrificial gate dielectric layer and a sacrificial gate electrode layer that are deposited and then patterned to form a sacrificial gate structure.

[0219] At block 1810, method 1800 may include selectively forming a sidewall spacer capping layer over the second set of fin structures. In some embodiments, the sidewall spacer capping layer is formed before block 1812 to prevent etching back the second set of fin structures. In some embodiments, the sidewall spacer capping layer is formed before block 1814 to prevent epitaxial growth on the second set of fin structures. At block 1812, method 1800 may include etching back the first set of fin structures outside the sacrificial gate structure and selectively etching back the second set of fin structures. At block 1814, method 1800 may include forming corresponding one or more epitaxial S / D features over the first set of fin structures and selectively over the second set of fin structures outside the sacrificial gate structure.

[0220] In some embodiments, method 1800 may include selectively controlling the second set of fin structures to improve device performance. For example, as described in more detail above, selectively controlling the second set of fin structures outside the gate region of the FinFET may include one or more of the following: forming a spacer material over the second set of fin structures; causing the height of the second set of fin structures to be equal to or less than the height of the first set of fin structures; causing the second set of fin structures to include epitaxial features that are not merged with the epitaxial S / D features of the first set of fin structures; or causing the second set of fin structures to include epitaxial features that are merged with the epitaxial S / D features of the first set of fin structures.

[0221] At block 1816, method 1800 may include forming a CESL and an ILD layer (ILD0) over the fin structure. At block 1818, method 1800 may include forming a replacement gate structure over the fin structure. For example, forming the replacement gate structure may include depositing a gate dielectric over the fin structure and then depositing a gate electrode over the gate dielectric. In some embodiments, a single deposition process may be used to deposit the gate electrode. In some other embodiments, for example Figures 9 to 12 As shown, the gate electrode can be deposited using multiple sequential deposition processes to form different portions of the gate electrode having a variety of different material compositions. For example, different portions of the gate electrode can be formed using separate patterning and deposition processes.

[0222] At block 1820, the method 1800 may include selectively forming an etch stop dielectric layer over the replacement gate structure. At block 1822, the method 1800 may include forming S / D contacts over the epitaxial S / D features. At block 1824, the method 1800 may include forming an ILD layer, one or more gate contact vias, one or more S / D contact vias, one or more metal lines, and an intermetallic dielectric (IMD) layer.

[0223] It should be understood that not all advantages are necessarily discussed herein, and that each embodiment or example is not necessarily endowed with a particular advantage, and that other embodiments or examples may provide different advantages.

[0224] Some embodiments disclosed herein provide a semiconductor device including a fin field-effect transistor (FinFET). The FinFET includes: a first set of active fin structures; source / drain (S / D) regions contacting the first set of fin structures; a second set of fin structures separated from the first set of fin structures by shallow trench isolation (STI); a contact etch stop layer (CESL) located above the S / D regions and the second set of fin structures, wherein the second set of fin structures includes one or more inactive fin structures, wherein the inactive fin structures contact the S / D regions but not the CESL; and a gate located above the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode located above the gate dielectric.

[0225] In some embodiments, wherein the one or more inactive fin structures are located outside the active region, the active region is associated with the S / D regions contacting the first set of fin structures.

[0226] In some embodiments, the FinFET is a first FinFET, the S / D region is a first S / D region, and the gate electrode is a first gate electrode. The semiconductor device further includes a second FinFET. The second FinFET includes a third set of fin structures, a second S / D region, a fourth set of fin structures, and a second gate. The third set of fin structures is in contact with the second S / D region, wherein the third set of fin structures is an active fin structure. The fourth set of fin structures is separated from the third set of fin structures by another STI feature, wherein the fourth set of fin structures is configured to further adjust device performance. The second gate includes a second gate dielectric formed above the third set of fin structures and above the fourth set of fin structures; and a second gate electrode formed above the second gate dielectric.

[0227] In some embodiments, the FinFET further includes forming a sidewall spacer capping layer, wherein the sidewall spacer capping layer is formed over a second set of fin structures outside a gate region of the FinFET. In some embodiments, the second set of fin structures includes a first fin structure having a first height and a second fin structure having a second height different from the first height. In some embodiments, the second set of fin structures includes one or more tapered fin structures, wherein a tapered width of the one or more tapered fin structures is in a range from about 0.5 times to about 1 times a base width.

[0228] In some embodiments, the second group of fin structures includes a first fin structure having a first height and a second fin structure having a second height different from the first height, wherein a portion of the gate electrode surrounding the first fin structure includes a material composition different from a material composition of another portion of the gate electrode surrounding the second fin structure. In some embodiments, the second group of fin structures includes at least an inner fin structure, wherein the inner fin structure is located between a first active fin structure in the first group of fin structures and a second active fin structure in the other group of active fin structures. In some embodiments, the second group of fin structures includes a non-tapered first fin structure and a tapered second fin structure.

[0229] In some embodiments, the second set of fin structures includes at least two fin structures, wherein the two fin structures are located on a first side of the first set of fin structures. In some embodiments, the second set of fin structures is cut to a height equal to or less than that of the first set of fin structures outside the gate region of the FinFET. In some embodiments, the S / D region includes a first epitaxial S / D feature, and the semiconductor device further includes a second epitaxial S / D feature formed on the second set of fin structures, wherein the second epitaxial S / D feature is not merged with the first epitaxial S / D feature. In some embodiments, the S / D region includes a first epitaxial S / D feature, and the semiconductor device further includes a second epitaxial S / D feature formed on the second set of fin structures, wherein the second epitaxial S / D feature is merged with the first epitaxial S / D feature.

[0230] Some embodiments disclosed herein provide methods for manufacturing a semiconductor device, including: forming a first set of fin structures and a second set of fin structures on a substrate; trimming the second set of fin structures without affecting the first set of fin structures; forming a sacrificial gate structure above the first set of fin structures and the second set of fin structures; etching back the first set of fin structures outside the sacrificial gate structure; forming one or more corresponding epitaxial S / D features above the first set of fin structures outside the sacrificial gate structure; forming a CESL and an interlayer dielectric (ILD) layer above the fin structures; and forming a replacement gate above the first set of fin structures and the second set of fin structures.

[0231] In some embodiments, forming a replacement gate includes forming a gate dielectric over the fin structure; then depositing a gate electrode over the gate dielectric, wherein the gate electrode is deposited using multiple sequential deposition processes to form different portions of the gate electrode having multiple different material compositions. In some embodiments, the method further includes forming an S / D contact over the epitaxial S / D feature. Forming another ILD layer. Forming one or more gate contact vias to the replacement gate. Forming one or more S / D contact vias to the S / D contact. Forming one or more metal lines over the ILD layer. Forming an intermetallic dielectric (IMD) layer over the one or more metal lines. In some embodiments, the method further includes etching back a second set of fin structures outside the sacrificial gate structure. Forming one or more epitaxial S / D features over the second set of fin structures outside the sacrificial gate structure.

[0232] Some embodiments disclosed herein provide a method for fabricating a semiconductor device, including forming a FinFET, wherein the FinFET includes a first set of active fin structures; S / D regions contacting the first set of fin structures; a second set of fin structures separated from the first set of fin structures by STI features; a contact etch stop layer (CESL) over the S / D regions and the second set of fin structures, wherein the second set of fin structures includes one or more S / D regions, wherein the S / D regions contact the CESL but do not contact the passive fin structures; and a gate over the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode over the gate dielectric layer.

[0233] In some embodiments, forming the second set of fin structures includes one or more of the following: forming a first fin structure and a second fin structure of the second set of fin structures, wherein the first fin structure and the second fin structure have different heights; one or more fin structures forming the second set of fin structures are tapered; at least one internal fin structure forming the second set of fin structures is positioned between a first active fin structure of the first set of fin structures and a second active fin structure of the other set of active fin structures; and at least two fin structures forming the second set of fin structures are positioned on a first side of the first set of fin structures.

[0234] In some embodiments, forming a second set of fin structures outside of a gate region of the FinFET comprises one or more of the following: forming a sidewall spacer capping layer over the second set of fin structures; forming the second set of fin structures to have a height equal to or less than a height of the first set of fin structures; forming the second set of fin structures to include a plurality of epitaxial features, wherein the epitaxial features are not merged with the epitaxial S / D features of the first set of fin structures; forming the second set of fin structures to include a plurality of epitaxial features, wherein the epitaxial features are merged with the epitaxial S / D features of the first set of fin structures.

[0235] Some embodiments disclosed herein provide a semiconductor device including a fin field-effect transistor (FinFET). The FinFET includes: a first set of active fin structures; source / drain regions contacting the first set of fin structures; a second set of fin structures separated from the first set of fin structures by shallow trench isolation, wherein the second set of fin structures includes a first fin structure having a first height and a second fin structure having a second height different from the first height; a contact etch stop layer (CESL) located above the source / drain regions and the second set of fin structures; and a gate located above the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode located above the gate dielectric.

[0236] Some embodiments disclosed herein provide a semiconductor device including a fin field-effect transistor (FinFET). The FinFET includes: a first set of active fin structures; source / drain regions contacting the first set of fin structures; a second set of fin structures separated from the first set of fin structures by shallow trench isolation (STI), wherein a height of the second set of fin structures outside a gate region of the FinFET is less than or equal to a height of the first set of fin structures; a contact etch stop layer (CESL) located above the source / drain regions and the second set of fin structures, wherein the second set of fin structures includes one or more inactive fin structures, wherein the inactive fin structures contact the source / drain regions but not the CESL; and a gate located above the first set of fin structures and the second set of fin structures, wherein the gate includes a gate dielectric and a gate electrode located above the gate dielectric.

[0237] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be easily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: A fin field effect transistor, comprising: a first set of fin structures, the first set of fin structures being active fin structures; a source / drain region contacting the first set of fin structures; a second set of fin structures separated from the first set of fin structures by a shallow trench isolation feature; a contact etch stop layer over the source / drain region and above the second set of fin structures; wherein the second set of fin structures includes an inactive fin structure or a plurality of inactive fin structures in contact with the contact etch stop layer but not in contact with the source / drain region; and a gate located above the first set of fin structures and the second set of fin structures, wherein the gate comprises: a gate dielectric; and A gate electrode is on the gate dielectric.

2. The semiconductor device according to claim 1, wherein The inactive fin structure or structures are located outside an active region associated with the source / drain regions contacting the first set of fin structures.

3. The semiconductor device according to claim 1, wherein The fin field effect transistor is a first fin field effect transistor, the source / drain region is a first source / drain region, the gate electrode is a first gate electrode, and the semiconductor device further includes a second fin field effect transistor, including: a third set of fin structures and a second source / drain region contacting the third set of fin structures, wherein the third set of fin structures are active fin structures; a fourth set of fin structures separated from the third set of fin structures by another shallow trench isolation feature, wherein the fourth set of fin structures is configured to further adjust device performance; and a second gate, comprising: a second gate dielectric formed over the third set of fin structures and over the fourth set of fin structures; and A second gate electrode is formed on a second gate dielectric.

4. The semiconductor device according to claim 1, wherein The FinFET further includes forming a sidewall spacer capping layer, wherein the sidewall spacer capping layer is formed over the second set of fin structures outside a gate region of the FinFET.

5. The semiconductor device according to claim 1, wherein The second set of fin structures includes at least one inner fin structure, wherein the inner fin structure is located between a first active fin structure in the first set of fin structures and a second active fin structure in the other set of active fin structures.

6. The semiconductor device according to claim 1, wherein The second set of fin structures includes: a first fin structure having a non-tapered shape; and A second fin structure is tapered.

7. The semiconductor device according to claim 1, wherein The second set of fin structures includes at least two fin structures, wherein the two fin structures are located on a first side of the first set of fin structures.

8. A semiconductor device, characterized in that: include: A fin field effect transistor, comprising: a first set of fin structures, the first set of fin structures being active fin structures; a source / drain region contacting the first set of fin structures; A second set of fin structures separated from the first set of fin structures by a shallow trench isolation feature, the second set of fin structures comprising: a first fin structure having a first height; and a second fin structure having a second height different from the first height; a contact etch stop layer over the source / drain region and above the second set of fin structures; and a gate located above the first set of fin structures and the second set of fin structures, wherein the gate comprises: a gate dielectric; and A gate electrode is on the gate dielectric.

9. The semiconductor device according to claim 8, wherein The second set of fin structures includes a tapered fin structure or a plurality of tapered fin structures, wherein a tapered width of the tapered fin structure or the plurality of tapered fin structures is in a range of 0.5 times to 1 times a bottom width.

10. A semiconductor device, characterized in that: include: A fin field effect transistor, comprising: a first set of fin structures, the first set of fin structures being active fin structures; a source / drain region contacting the first set of fin structures; a second set of fin structures separated from the first set of fin structures by a shallow trench isolation feature, wherein a height of the second set of fin structures outside a gate region of the FinFET is less than or equal to a height of the first set of fin structures; a contact etch stop layer over the source / drain region and above the second set of fin structures; wherein the second set of fin structures includes an inactive fin structure or a plurality of inactive fin structures in contact with the contact etch stop layer but not in contact with the source / drain region; and a gate located above the first set of fin structures and the second set of fin structures, wherein the gate comprises: a gate dielectric; and A gate electrode is on the gate dielectric.

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